CN207651483U - A kind of anti-locking devicen, CMOS chip and PCB - Google Patents
A kind of anti-locking devicen, CMOS chip and PCB Download PDFInfo
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- CN207651483U CN207651483U CN201721592778.1U CN201721592778U CN207651483U CN 207651483 U CN207651483 U CN 207651483U CN 201721592778 U CN201721592778 U CN 201721592778U CN 207651483 U CN207651483 U CN 207651483U
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- switch
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- controlled circuit
- locking devicen
- resistance
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Abstract
The utility model provides a kind of anti-locking devicen, CMOS chip and PCB, wherein the anti-locking devicen is serially connected in the power path between controlled circuit and power input port, and the anti-locking devicen includes：First resistor, the second resistance of belt switch and logic control circuit；The first resistor is connected in the power path between the controlled circuit and the power input port；One end of switch is not arranged for the second resistance, is connected in the power path between controlled circuit and the first resistor, the second resistance is in parallel with the controlled circuit；The logic control circuit is connected with the switch, is controlled the switch and is opened or closed.By anti-locking devicen provided by the utility model, latch can be effectively released without cutting off the power.
Description
Technical field
The utility model is related to field of computer technology, more particularly to a kind of anti-locking devicen, CMOS chip and PCB
(printed circuit board).
Background technology
CMOS (Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductor) is
A kind of widely used integrated circuit processing technique, and in space flight radiation environment, integrated circuit will appear single particle effect and
Total dose effect.Wherein, single event latch-up be it is a kind of prodigious single particle effect is endangered to CMOS chip circuit, penetrated by single-particle
Enter to induce the positive feedback of SCR structure, CMOS chip circuit burnout may be caused.
The main method of anti-single particle latch includes using SOI (Silicon-On-Insulator, in dielectric substrate
Silicon) technique, special reinforcement is carried out to CMOS technology library and using external anti-latch measure etc..When can not be anti-by process improving
When single event latch-up performance, then external anti-latch measure is relied only on.
The existing anti-latch measure in outside includes mainly resistance current limliting and detects and cut off the power two kinds.Resistance current-limiting mode
Realize that this kind of method can not be effective by simply sealing in resistance on the power path between power input port and controlled circuit
It releases latch and controlled circuit normal work may be influenced；It detects and mode of cutting off the power, is detecting controlled circuit
It cuts off the power when latch, although this kind of mode cocoa releases the latch mode of controlled circuit, CMOS cores can be destroyed by cutting off the power
Piece operating status.
Utility model content
The utility model provides a kind of anti-locking devicen, with solve can not be not present in existing anti-latch scheme
The problem of controlled circuit latch mode is effectively released under the premise of power-off.
To solve the above-mentioned problems, the utility model discloses a kind of anti-locking devicen, the anti-locking devicen is serially connected in
In power path between controlled circuit and power input port, the anti-locking devicen includes：The of first resistor, belt switch
Two resistance and logic control circuit；The first resistor is connected between the controlled circuit and the power input port
In power path；One end of switch is not arranged for the second resistance, the electricity being connected between controlled circuit and the first resistor
In the access of source, the second resistance is in parallel with the controlled circuit；The logic control circuit is connected with the switch, controls institute
Switch is stated to be opened or closed.
To solve the above-mentioned problems, the utility model discloses a kind of CMOS chips, wherein the chip includes this practicality
Any one anti-locking devicen described in new embodiment.
To solve the above-mentioned problems, the utility model discloses a kind of PCB, wherein the PCB includes that the utility model is real
Apply any one anti-locking devicen described in example.
Compared with prior art, the utility model has the following advantages：
Anti- locking devicen provided by the utility model is gone here and there in the power path between controlled circuit and power input port
Join first resistor, the second resistance of the access belt switch in parallel with controlled circuit between first resistor and controlled circuit, and by
Logic control circuit control second resistance switch is opened or closed.Specifically, when logic control circuit detects controlled circuit
When latch occurs, power source loads are instantly increased when of short duration closure switch second resistance accesses power path, and correspondingly circuit is instantaneous
Electric current increases suddenly, and to release the latch mode of controlled circuit, latch can be effectively released without cutting off the power.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of anti-locking devicen of the utility model embodiment one；
Fig. 2 is a kind of structural schematic diagram of anti-locking devicen of the utility model embodiment two.
Specific implementation mode
To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, below in conjunction with the accompanying drawings and have
Body embodiment is described in further detail the utility model.
Embodiment one
Referring to Fig.1, a kind of structural schematic diagram of anti-locking devicen of the utility model embodiment one is shown.
As shown in Figure 1, the anti-locking devicen 101 of the utility model embodiment is serially connected in controlled circuit 102 and power input
In power path between port 103.Anti- locking devicen 101 includes：First resistor 1011, the second resistance of belt switch 1012 with
And logic control circuit 1013.
First resistor 1011 is connected in the power path between controlled circuit 102 and power input port 103；Second electricity
One end of switch is not arranged for resistance 1012, is connected in the power path between controlled circuit 102 and first resistor 1011, the second electricity
Resistance 1012 is in parallel with controlled circuit 102；Logic control circuit 1013 is connect with the switch of second resistance 1012, and control switch disconnects
Or it is closed.
Anti- locking devicen operation principle is as follows：When latch occurs for controlled circuit 102, controlled circuit 102 is by first resistor
1011 current limlitings are in latch stable state.At this point, if the switch of second resistance 1012 is closed, second resistance 1012 is successfully accessed electricity
In the access of source, power source loads increase suddenly, and the transient current of power input port input increases suddenly, is correspondingly input to controlled
The electric current of circuit 102 rises sharply, and the latch mode of controlled circuit 102 releases.It should be noted that the switch of second resistance 1012 closes
When conjunction, for avoid influence controlled circuit normal operation answer of short duration closure switch after disconnect.
Logic control circuit 1013 can control switch and be closed and disconnect according to predetermined period.Such as：It was closed every 5 seconds
Primary switch, each switch are closed 10 milliseconds.This kind of mode is not necessarily to judge whether controlled circuit 102 occurs latch, but mechanical
Formula is closed according to predetermined period, disconnects switch.Specifically, it can be closed by sending high low pulse signal control switch
It closes, disconnect.
It is pulse signal radiating circuit that a kind of preferred realization method, which is by logic control circuit,；Pulse signal radiating circuit
According to predetermined period, alternate emission high level signal and low level signal are opened or closed with control switch.
When pulse signal radiating circuit emits high level signal, switch disconnects；Between controlled circuit and power input port
The electric current of the electric current of power path, power path when being closed compared to switch between controlled circuit and power inlet increases, by
The input current of controlled circuit increases when controlling the input current of circuit compared to switch closure；When pulse signal radiating circuit emits
When low level signal, switch is closed.
This kind of mode controls the mode that switch is disconnected, is closed, and even controlled circuit 102 is in front and back closure switch twice
Latch has occurred in interval, is also only of short duration latch, latch can be still released from after switch is closed again.
Logic control circuit 1013 can also detect whether controlled circuit 102 is sent out in the course of work of controlled circuit 102
Raw latch is closed the switch of second resistance 1012, switch is disconnected again after short time closure switch, to solve when latch occurs
Except the latch mode of controlled circuit 102.
During specific implementation, those skilled in the art can select any one of the above mode to set according to actual demand
Logic control circuit 1013 is set, this is not particularly limited in the embodiment of the present invention.
First resistor, the resistance value of second resistance need the resistance value according to controlled circuit to determine.First resistor need to select not shadow
The resistance value of controlled circuit normal work, i.e. input current and the divided difference between currents of first resistor are rung, to be equal to controlled circuit just
Normal operating current.Equivalent resistance size when latch occurs for second resistance and controlled circuit is close, preferably second resistance with
Equivalent resistance when latch occurs for controlled circuit.This is because if second resistance resistance value is excessive, when controlled circuit is fastened with a bolt or latch
Can not effectively be shunted when lock, it is too small to further result in the current increase that power input port is inputted, can not effectively release by
Control circuit latch mode.If second resistance resistance value is too small, the input current of controlled circuit increases excessive when the switch is closed, then can
Influence the normal work of controlled circuit.
The anti-locking devicen that the utility model embodiment provides, can be arranged inside CMOS chip or be arranged
Outside CMOS chip.Anti- locking devicen provided by the utility model can effectively release single event latch-up state.
Anti- locking devicen provided by the utility model is gone here and there in the power path between controlled circuit and power input port
Join first resistor, the second resistance of the access belt switch in parallel with controlled circuit between first resistor and controlled circuit, and by
Logic control circuit control second resistance switch is opened or closed.Specifically, when logic control circuit detects controlled circuit
When latch occurs, power source loads are instantly increased when of short duration closure switch second resistance accesses power path, and correspondingly circuit is instantaneous
Electric current increases suddenly, and to release the latch mode of controlled circuit, latch can be effectively released without cutting off the power.
Embodiment two
With reference to Fig. 2, a kind of structural schematic diagram of anti-locking devicen of the two of the utility model embodiment is shown.
As shown in Fig. 2, to be serially connected in controlled circuit 202 defeated with power supply for the anti-locking devicen 201 in the utility model embodiment
In power path between inbound port 203, anti-locking devicen includes：First resistor 2011, the second resistance of belt switch 2012, ratio
Compared with device 2013 and logic control element 2014, wherein comparator 2013 and logic control element 2014 forms logic control electricity
Road.
First resistor 2011 is connected in the power path between controlled circuit 202 and power input port 203；Second electricity
One end of switch is not arranged for resistance 2012, is connected in the power path between controlled circuit 202 and first resistor 2011, the second electricity
Resistance 2012 is in parallel with controlled circuit 202.
The first input end of comparator 2013, that is, "-" end is connected to the electricity between first resistor 2011 and second resistance 2012
In the access of source, the second input terminal of comparator 2013, that is, "+" terminates reference voltage, that is, Vref, the output end of comparator 2013 with patrol
Control unit 2014 is collected to connect；Logic control element 2014 is connect with the switch of second resistance 2012, and control switch is disconnected or closed
It closes.
The operation principle of anti-locking devicen is as follows：
First, comparator 2013 detects whether controlled circuit 202 occurs latch；
The input voltage of first input end is compared by comparator 2013 with reference voltage；When input voltage is less than reference
When voltage, determine that latch occurs for controlled circuit.
This is because controlled circuit current limliting when latch, the first input end voltage of comparator 2013 occur for controlled circuit 202
Decline, the level signal that comparator 2013 is exported is got higher by low.
Secondly, when detecting that latch occurs for controlled circuit 202, comparator 2013 exports high level signal to logic control
Unit 2014；Logic control element 2014 generates short pulse so as to switch of short duration closure according to the high level signal received.
Switch that of short duration closing time is equal with single pulse duration, the specific duration for switching of short duration closure can be by this field
Technical staff is configured according to actual demand, to being not specifically limited in the embodiment of the present invention.
If the switch of second resistance 2012 is closed, second resistance 2012 is successfully accessed in power path, and power source loads are unexpected
Increase, the transient current of power input port input increases suddenly, and the electric current moment for being correspondingly input to controlled circuit 202 increases
Add, the latch mode of controlled circuit 202 releases.
During specific implementation, first resistor need to select not the resistance value for influencing controlled circuit normal work, i.e. input electricity
Stream and the divided difference between currents of first resistor will be equal to the running current of controlled circuit.Second resistance occurs with controlled circuit
Equivalent resistance size when latch is close, preferably second resistance and equivalent resistance when controlled circuit generation latch.
Preferably, the anti-locking devicen of the utility model implementation offer further includes：(portion is not shown in capacitance in fig. 2
Part)；In power path of the capacitance connection between controlled circuit 202 and first resistor 2011, and capacitance is in parallel with controlled circuit,
The set capacitance can provide electric current supply for controlled circuit.Specifically, in the state that latch does not occur for controlled circuit,
(certain specific functions startup of controlled circuit when increment of the working current value of controlled circuit in preset time exceeds preset value
When need relatively large electric current), capacitance be controlled circuit supply electric current to ensure the normal work of controlled circuit.
Anti- locking devicen provided by the utility model is gone here and there in the power path between controlled circuit and power input port
Join first resistor, the second resistance of the access belt switch in parallel with controlled circuit between first resistor and controlled circuit, and by
Logic control circuit control second resistance switch is opened or closed.Specifically, when logic control circuit detects controlled circuit
When latch occurs, power source loads are instantly increased when of short duration closure switch second resistance accesses power path, and correspondingly circuit is instantaneous
Electric current increases suddenly, and to release the latch mode of controlled circuit, latch can be effectively released without cutting off the power.
A kind of CMOS chip is additionally provided in the utility model, CMOS chip is anti-comprising any one heretofore described
Locking devicen.Anti- locking devicen can be arranged inside CMOS chip, can also be arranged outside CMOS chip.
The utility model discloses a kind of printing board PCBs, wherein the PCB includes in the utility model embodiment
The anti-locking devicen of any one described.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiment, the same or similar parts between the embodiments can be referred to each other.It is new to this practicality above
A kind of anti-locking devicen that type is provided is described in detail, and specific case used herein is to the principles of the present invention
And embodiment is expounded, the explanation of above example is only intended to methods and its core that help understands the utility model
Thought；Meanwhile for those of ordinary skill in the art, according to the thought of the utility model, in specific implementation mode and application
There will be changes in range, in conclusion the content of the present specification should not be construed as a limitation of the present invention.
Claims (9)
1. a kind of anti-locking devicen, which is characterized in that the anti-locking devicen be serially connected in controlled circuit and power input port it
Between power path in, the anti-locking devicen includes：First resistor, the second resistance of belt switch and logic control circuit；
The first resistor is connected in the power path between the controlled circuit and the power input port；
One end of switch is not arranged for the second resistance, the power path being connected between controlled circuit and the first resistor
In, the second resistance is in parallel with the controlled circuit；
The logic control circuit is connected with the switch, is controlled the switch and is opened or closed.
2. anti-locking devicen according to claim 1, it is characterised in that：The logic control circuit emits for pulse signal
Circuit；
The pulse signal radiating circuit is according to predetermined period, alternate emission high level signal and low level signal, with control
The switch is opened or closed.
3. anti-locking devicen according to claim 2, it is characterised in that：
When the pulse signal radiating circuit emits high level signal, the switch disconnects；The controlled circuit and power input
The electric current of power path between port, power supply when being closed compared to the switch between the controlled circuit and power inlet are logical
The electric current on road increases, the input current of the input current of controlled circuit controlled circuit when being closed compared to the switch
Increase；
When the pulse signal radiating circuit emits low level signal, the switch is closed.
4. anti-locking devicen according to claim 1, which is characterized in that the logic control circuit includes：Comparator with
And logic control element；
The first input end of the comparator is connected in the power path between the first resistor and the second resistance, institute
The second input termination reference voltage of comparator is stated, the output end of the comparator is connect with the logic control element, described
Logic control element is connected with the switch；
The comparator detects whether the controlled circuit occurs latch；When detecting that latch occurs for the controlled circuit, institute
It states comparator and exports high level signal to the logic control element；
The logic control element generates short pulse so that described switch of short duration close according to the high level signal received
It closes.
5. anti-locking devicen according to claim 1, it is characterised in that：The resistance value of the second resistance and the controlled electricity
Equivalent resistance when the generation latch of road is equal.
6. anti-locking devicen according to claim 1, which is characterized in that the anti-locking devicen further includes：Capacitance；
In power path of the capacitance connection between controlled circuit and the first resistor, the capacitance and the controlled electricity
Road is in parallel.
7. anti-locking devicen according to claim 6, it is characterised in that：
In the state that latch does not occur for the controlled circuit, the increasing of the working current value of the controlled circuit in preset time
When amount is beyond preset value, the capacitance is that the controlled circuit supplies electric current.
8. a kind of CMOS chip, which is characterized in that the chip includes the anti-latch dress described in any one of claim 1-7
It sets.
9. a kind of PCB, which is characterized in that the PCB includes the anti-locking devicen described in any one of claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721592778.1U CN207651483U (en) | 2017-11-24 | 2017-11-24 | A kind of anti-locking devicen, CMOS chip and PCB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721592778.1U CN207651483U (en) | 2017-11-24 | 2017-11-24 | A kind of anti-locking devicen, CMOS chip and PCB |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207651483U true CN207651483U (en) | 2018-07-24 |
Family
ID=62881146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721592778.1U Active CN207651483U (en) | 2017-11-24 | 2017-11-24 | A kind of anti-locking devicen, CMOS chip and PCB |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207651483U (en) |
-
2017
- 2017-11-24 CN CN201721592778.1U patent/CN207651483U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |