CN207638859U - Analog-to-digital conversion Acquisition Circuit - Google Patents
Analog-to-digital conversion Acquisition Circuit Download PDFInfo
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- CN207638859U CN207638859U CN201721604258.8U CN201721604258U CN207638859U CN 207638859 U CN207638859 U CN 207638859U CN 201721604258 U CN201721604258 U CN 201721604258U CN 207638859 U CN207638859 U CN 207638859U
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- analog
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- digital conversion
- acquisition circuit
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Abstract
The utility model provides a kind of analog-to-digital conversion Acquisition Circuit, including：Audio analog signals Acquisition Circuit, fixed gain amplifying circuit, programme control circut, differential amplifier circuit and analog to digital conversion circuit；Each circuit is electrically connected successively；Audio analog signals Acquisition Circuit is for exporting audio analog signals；The enhanced processing of gain is fixed in the audio analog signals that fixed gain amplifying circuit exports audio analog signals Acquisition Circuit；Programme control circut is used to carry out decaying or enhanced processing to the audio analog signals that fixed gain amplifying circuit exports according to the control signal at its input control end；Differential amplifier circuit is used to the differential signal that programme control circut exports being converted to Single-end output analog signal；Analog to digital conversion circuit is used to Single-end output analog signal being converted to digital signal.The circuit can coordinate FPGA to emulate digital-to-analogue audio-frequency unit function, and circuit is simple, and integrated level is high.
Description
Technical field
The utility model is related to audio interface artificial circuit technical fields, more particularly, to analog-to-digital conversion Acquisition Circuit.
Background technology
Since FPGA is digital logic chip, there is no analog signal module.It is mixed using the practical digital-to-analogue of FPGA emulation when needing
When closing chip audio partial circuit, then need to build relevant circuit and FPGA cooperation completion emulation in outside.But do not have also at present
There is the analog-to-digital conversion Acquisition Circuit for coordinating with FPGA and completing audio emulation.
Utility model content
The purpose of this utility model is that in view of the deficiencies of the prior art, provides a kind of analog-to-digital conversion Acquisition Circuit and be used for
Solve the deficiencies in the prior art.
The utility model provides a kind of analog-to-digital conversion Acquisition Circuit, including：Audio analog signals Acquisition Circuit, fixed increasing
Beneficial amplifying circuit, programme control circut, differential amplifier circuit and analog to digital conversion circuit；
The audio analog signals Acquisition Circuit, the fixed gain amplifying circuit, the programme control circut, the difference are put
Big circuit and analog-digital conversion circuit as described are electrically connected successively；
The audio analog signals Acquisition Circuit is for acquiring audio analog signals；
The audio analog signals are fixed the enhanced processing of gain in the fixed gain amplifying circuit；
The programme control circut is for exporting the fixed gain amplifying circuit according to the control signal at its input control end
Audio analog signals carry out decaying or enhanced processing；
The differential amplifier circuit is used to the differential signal that the programme control circut exports being converted to Single-end output simulation letter
Number；
Analog-digital conversion circuit as described is used to the Single-end output analog signal being converted to digital signal.
As a further improvement of the above technical scheme, the audio analog signals Acquisition Circuit includes：Microphone, two electricity
Resistance, three capacitances；A termination power after the two resistors are connected in series, the other end are answered one end of cylinder, the other end ground connection of microphone；First
A capacitance connection is between the common end and ground of two resistance, and second capacitance connection is in the common end of resistance and microphone and ground
Between, third capacitance connection is between resistance and the common end and the fixed gain amplifying circuit of microphone.
As a further improvement of the above technical scheme, the microphone is Electret condenser microphone.
As a further improvement of the above technical scheme, the fixed gain amplifying circuit selects PJ4808 chips.
As a further improvement of the above technical scheme, the gain ranging of the fixed gain amplifying circuit is 4-8.
As a further improvement of the above technical scheme, the programme control circut selects AD8369 chips.
As a further improvement of the above technical scheme, it is even number that the programme control circut, which selects the number of AD8369 chips,.
As a further improvement of the above technical scheme, the programme control circut selects 2 AD8369 chips to constitute two-stage.
As a further improvement of the above technical scheme, the differential amplifier circuit selects INA118 chips.
As a further improvement of the above technical scheme, analog-digital conversion circuit as described selects ADC122S101 chips.
As a further improvement of the above technical scheme, the analog switching circuit selects SN74LVC1G66.
Using technical solution provided by the utility model, compared with existing known technology, at least have following beneficial to effect
Fruit：The circuit can coordinate FPGA to emulate digital-to-analogue audio-frequency unit function, and circuit is simple, and integrated level is high.
Description of the drawings
It, below will be to required use in embodiment in order to illustrate more clearly of the technical solution of the utility model embodiment
Attached drawing be briefly described, it should be understood that the following drawings illustrates only some embodiments of the utility model, therefore should not be by
Regard the restriction to range as, for those of ordinary skill in the art, without creative efforts, may be used also
To obtain other relevant attached drawings according to these attached drawings.
Fig. 1 is the structural schematic diagram for the analog-to-digital conversion Acquisition Circuit that one embodiment of the utility model proposes.
Fig. 2 is the circuit diagram for the analog-to-digital conversion Acquisition Circuit that one embodiment of the utility model proposes.
Main element symbol description：
10- audio analog signals Acquisition Circuit, 20- fixed gains amplifying circuit, 30- programme control circuts, 40- differential amplification electricity
Road, 50- analog to digital conversion circuits.
Specific implementation mode
Hereinafter, the various embodiments of the disclosure will be described more fully.The disclosure can have various embodiments, and
It can adjust and change wherein.It should be understood, however, that：There is no disclosure protection domain is limited to specific reality disclosed herein
The intention of example is applied, but the disclosure should be interpreted as to all in the spirit and scope for covering the various embodiments for falling into the disclosure
Adjustment, equivalent and/or alternative.
Hereinafter, disclosed in the term " comprising " that can be used in the various embodiments of the disclosure or " may include " instruction
Function, operation or the presence of element, and do not limit the increase of one or more functions, operation or element.In addition, such as existing
Used in the various embodiments of the disclosure, term " comprising ", " having " and its cognate are meant only to indicate special characteristic, number
Word, step, operation, the combination of element, component or aforementioned item, and be understood not to exclude first one or more other
Feature, number, step, operation, the combination of element, component or aforementioned item presence or increase one or more features, number,
Step, the possibility of operation, the combination of element, component or aforementioned item.
In the various embodiments of the disclosure, statement " at least one of A or/and B " includes the word listed file names with
Any combinations or all combinations.For example, statement " A or B " or " at least one of A or/and B " may include A, may include B or can
Including A and B both.
The statement (" first ", " second " etc.) used in the various embodiments of the disclosure can be modified in various implementations
Various constituent element in example, but respective sets can not be limited into element.For example, presented above be not intended to limit the suitable of the element
Sequence and/or importance.The purpose presented above for being only used for differentiating an element and other elements.For example, the first user fills
It sets and indicates different user device with second user device, although the two is all user apparatus.For example, not departing from each of the disclosure
In the case of the range of kind embodiment, first element is referred to alternatively as second element, and similarly, second element is also referred to as first
Element.
It should be noted that：It, can be by the first composition member if a constituent element ' attach ' to another constituent element by description
Part is directly connected to the second constituent element, and " connection " third can be formed between the first constituent element and the second constituent element
Element.On the contrary, when a constituent element " being directly connected to " is arrived another constituent element, it will be appreciated that in the first constituent element
And second third constituent element is not present between constituent element.
The term " user " used in the various embodiments of the disclosure, which may indicate that, to be used the people of electronic device or uses electricity
The device (for example, artificial intelligence electronic device) of sub-device.
The term used in the various embodiments of the disclosure is used only for the purpose of describing specific embodiments and not anticipates
In the various embodiments of the limitation disclosure.Unless otherwise defined, otherwise all terms used herein (including technical term and
Scientific terminology) there is contain identical with the various normally understood meanings of embodiment one skilled in the art of the disclosure
Justice.The term (term such as limited in the dictionary generally used) be to be interpreted as have in the related technical field
The identical meaning of situational meaning and the meaning of Utopian meaning or too formal will be interpreted as having, unless at this
It is clearly defined in disclosed various embodiments.
Embodiment 1
As shown in Figure 1, the utility model provides a kind of analog-to-digital conversion Acquisition Circuit, including：Audio analog signals acquire
Circuit 10, fixed gain amplifying circuit 20, programme control circut 30, differential amplifier circuit 40 and analog to digital conversion circuit 50.
Audio analog signals Acquisition Circuit 10, fixed gain amplifying circuit 20, programme control circut 30,40 and of differential amplifier circuit
Analog to digital conversion circuit 50 is electrically connected successively.
Audio analog signals Acquisition Circuit 10 is for acquiring audio analog signals.
The audio analog signals that fixed gain amplifying circuit 20 exports audio analog signals Acquisition Circuit 10 are fixed
The enhanced processing of gain.
The sound that programme control circut 30 is used to export fixed gain amplifying circuit 20 according to the control signal at its input control end
Frequency analog signal carries out decaying or enhanced processing.
Differential amplifier circuit 40 is used to the differential signal that programme control circut 30 exports being converted to Single-end output analog signal.
Analog to digital conversion circuit 50 is used to the single-ended analog signal that differential amplifier circuit 40 exports being converted to digital signal.
Audio analog signals Acquisition Circuit 10 includes：Microphone, two resistance, three capacitances；One end after the two resistors are connected in series
Connect power supply, the other end is answered one end of cylinder, the other end ground connection of microphone；First capacitance connection the common end of two resistance with
Between ground, second capacitance connection is between resistance and the common end and ground of microphone, and third capacitance connection is in resistance and microphone
Common end and the fixed gain amplifying circuit between.
As shown in Fig. 2, specifically, audio analog signals Acquisition Circuit 10 includes：Microphone MIC, two resistance (R1 and R2),
Three capacitances (C1, C2 and C3)；Resistance R1 and R2 connects latter termination power+5V, and the other end is answered one end of a MIC, microphone
The other end of MIC is grounded；Capacitance C1 is connected between the common end and ground of resistance R1 and R2, and capacitance C2 is connected to resistance R2 and words
Between the common end and ground of cylinder MIC, capacitance C3 is connected to common end and the fixed gain amplifying circuit 20 of resistance R2 and microphone MIC
Between.
The preferred Electret condenser microphones of microphone MIC.
Electret condenser microphone has the characteristics that small, simple in structure, electroacoustic performance is good, low-cost, is widely used in boxlike record
In the circuits such as sound machine, wireless microphone and acoustic control.Belong to most common capacitor microphone.Electret capacitor microphone needs at work
Direct-current working volts.
Fixed gain amplifying circuit 20 selects PJ4808 chips.
Specifically, fixed gain amplifying circuit 20 includes：PJ4808 chips (U1), 7 resistance (R4-R10), 5 capacitances
(C4-C8)。
One end connection audio analog signals Acquisition Circuit 10 of resistance R4, the pin 2 of the other end connection U1 of resistance R4
(INA-).Capacitance C4 connect the pin 1 (OUTA) of pin 2 (INA-) other end connection U1 of U1 with one end after resistance R5 parallel connections.
Resistance R8 latter end ground connection in parallel with capacitance C5, the other end be separately connected the pin 3 (INA+) of U1, U1 pin 5 (INB+) and
One end of resistance R7, another termination power+5V of resistance R7.The pin 4 (GND) of U1 is grounded.Pin 8 (VDD) the connection electricity of U1
Source+5V.Capacitance C6 connect the+5V of power supply with the capacitance C7 latter end ground connection other ends in parallel.The both ends of resistance R6 are separately connected U1
Pin 1 (OUTA) and pin 6 (INB-).Resistance R9, resistance R10 connect the pin 6 of U1 with one end after capacitance C8 parallel connections
(INB-) pin 7 (IOUTB) of other end connection U1.The pin 7 (IOUTB) of U1 is also connected with programme control circut 30.
The gain ranging of fixed gain amplifying circuit 20 is 4-8.In the present embodiment, the resistance value of resistance R4 is 15K Ω, electricity
The resistance value for hindering R5 is 22K Ω, and the resistance value of resistance R6 is 5.6K Ω.The gain of fixed gain amplifying circuit 20 is the first stage gain
Product i.e. 5.76 of 22K/15K and the second stage gain 22K/5.6K.The gain ranging for controlling fixed gain amplifying circuit 20 is 4-8
It can effectively ensure that the voice signal of microphone acquisition smoothly can be handled smoothly by subsequent programme control circut 30.
Programme control circut 30 selects AD8369 chips.
Since AD8369 chips have 4 input control pins (BIT0-BIT3), and a byte inside processor is
8, the output controlling switch of most of fpga chip is 8 or 8 multiple, therefore programme control circut at least selects 2
AD8369 chips constitute the input control end that two-stage forms one 8.
Specifically, programme control circut 30 includes：Two AD8369 chips (U2 and U3), two resistance (R11 and R12), 19
Capacitance (C9-C27).
One end is connected and fixed the output end of gain amplifying circuit 20 after capacitance C9 and capacitance C10 parallel connections, and the other end connects U2
Pin 16 (INHI).One end of capacitance C11 is grounded, the pin 1 (INLO) of the other end connection U2 of capacitance C11；The pin 2 of U2
(COMM), pin 15 (COMM) and pin 12 (SENB) are grounded；Pin 3 (BIT0), pin 4 (BIT1), the pin 5 of U2
(BIT2) control output end of fpga chip is connected as control signal input with pin 6 (BIT3).The pin 10 of U2
(CMDC), pin 11 (FILT), pin 13 (VPOS) and pin 14 (PWUP) are connect by capacitance C15, C14, C13, C12 respectively
Ground.
Capacitance C16 connects one end of pin 9 (OPHI) other end connection resistance R11 of U2 with one end after capacitance C17 parallel connections；
Capacitance C18 connects the other end of pin 8 (OPLO) other end connection resistance R11 of U2 with one end after capacitance C19 parallel connections.Resistance
The both ends of R11 are separately connected the AD8369 chips (U3) of next stage.
The pin 16 (INHI) of one end connection U3 of resistance R11, the pin 1 (INLO) of the other end connection U3 of resistance R11；
Pin 2 (COMM), pin 15 (COMM) and the pin 12 (SENB) of U3 is grounded；The pin 3 (BIT0) of U3, pin 4 (BIT1),
Pin 5 (BIT2) connects the control output end of fpga chip with pin 6 (BIT3) as control signal input.The pin of U3
10 (CMDC), pin 11 (FILT), pin 13 (VPOS) and pin 14 (PWUP) are connect by capacitance C23, C22, C21, C20 respectively
Ground.
Capacitance C24 connects one end of pin 9 (OPHI) other end connection resistance R12 of U3 with one end after capacitance C25 parallel connections；
Capacitance C26 connects the other end of pin 8 (OPLO) other end connection resistance R12 of U3 with one end after capacitance C27 parallel connections.Resistance
The both ends of R12 are also respectively connected with differential amplifier circuit 40.
The controlling switch (BIT0-BIT3) of U2 constitutes low 4, and controlling switch (BIT0-BIT3) composition of U3 is 4 high, always
It totally 8, is connect with 8 control bits (FPGA_MO_BIT0-FPGA_MO_BIT7) of FPGA.
Differential amplifier circuit 40 selects INA118 chips.
INA118 chips have many advantages, such as that precision is high, low in energy consumption, common-mode rejection ratio is high and working band is wide, are suitble to various
Tiny signal is amplified.The unique current feedback structures of INA118 make it that can also keep very high frequency under higher gain
Bandwidth.Differential amplification structure is formed by three operational amplifiers.Built-in input overvoltage protection, and external different size can be passed through
Resistance realize different gains, be of wide application.
INA118 chip major parameters are as follows：Peak excursion voltage is 50 μ V；Maximum input base current is 5nA；It is minimum
Common-mode rejection ratio is 110dB；Input overvoltage protection voltage is ± 40V；Supply voltage is ± 1.35V~± 18V；When unit gain
Bandwidth is 800kHz；Stabilization time is 25 μ s when unit gain；Operating temperature range is -40 DEG C~85 DEG C；Packing forms are 8 feet
DIP is encapsulated.
Specifically, differential amplifier circuit 40 includes：INA118 chips (U4), 3 resistance (R13-R15) and 3 capacitances
(C28-C30)。
The both ends of resistance R13 are separately connected the pin 1 (RG) and pin 8 (RG) of U4；After capacitance C28 and capacitance C29 parallel connections
One end is grounded the pin 7 (V+) of other end connection U4；Resistance R14 connect U4's with the capacitance C30 latter end ground connection other ends in parallel
Pin 5 (REF)；The pin 5 (REF) of the other end connection U4 of the+3.3V of mono- termination powers of resistance R15, resistance R15.
The pin 2 (VIN-) and pin 3 (VIN+) of U4 connects programme control circut 30；The pin 6 (VO) of U4 connects analog-to-digital conversion
Circuit 50.
Analog to digital conversion circuit 50 selects ADC122S101 chips.
ADC122S101 chips are a binary channels, 12 A/D converters that sample frequency is 500ksps to 1ksps.
Specifically, analog to digital conversion circuit 50 includes：ADC122S101 chips (U5), resistance R16 and 4 capacitance (C31-
C34)。
The output end of one end connection programme control circut 40 of resistance R16, the pin 5 of the other end connection U5 of resistance R16
(IN1)；One end of capacitance C31 is grounded, the pin 5 (IN1) of the other end connection U5 of capacitance C31；One end of capacitance C32 is grounded,
The pin 4 (IN2) of the other end connection U5 of capacitance C32；The capacitance C33 latter termination power+3.3V other ends in parallel with capacitance C34
Ground connection；Pin 2 (VA) connection power supply+3.3V of U5；The pin 3 (GND) of U5 is grounded.
When carrying out FPGA emulation, the relevant pins of FPGA pin corresponding with chip U2, U3 and U5 is connected.Pass through control
The relevant pins of FPGA (FPGA_MO_BIT0-FPGA_MO_BIT7) can be achieved programme control circut and decay to audio analog signals
Or enhanced processing, the Acquisition Circuit of program gain control provide the gain-adjusted of wide dynamic range, can adjust -20dB
To the gain ranging of 60dB, stepping 3dB.Circuit is simple, is not interfered between digital-to-analogue.
It will be appreciated by those skilled in the art that the accompanying drawings are only schematic diagrams of a preferred implementation scenario, module in attached drawing or
Flow is not necessarily implemented necessary to the utility model.
It will be appreciated by those skilled in the art that the module in device in implement scene can be described according to implement scene into
Row is distributed in the device of implement scene, can also be carried out respective change and is located at the one or more dresses for being different from this implement scene
In setting.The module of above-mentioned implement scene can be merged into a module, can also be further split into multiple submodule.
Above-mentioned the utility model serial number is for illustration only, does not represent the quality of implement scene.Disclosed above is only this
Several specific implementation scenes of utility model, still, the utility model is not limited to this, any those skilled in the art's energy
Think of variation should all fall into the scope of protection of the utility model.
Claims (10)
1. a kind of analog-to-digital conversion Acquisition Circuit, which is characterized in that including：Audio analog signals Acquisition Circuit, fixed gain amplification
Circuit, programme control circut, differential amplifier circuit and analog to digital conversion circuit；
The audio analog signals Acquisition Circuit, the fixed gain amplifying circuit, the programme control circut, differential amplification electricity
Road and analog-digital conversion circuit as described are electrically connected successively；
The audio analog signals Acquisition Circuit is for acquiring audio analog signals；
The audio analog signals are fixed the enhanced processing of gain in the fixed gain amplifying circuit；
The sound that the programme control circut is used to export the fixed gain amplifying circuit according to the control signal at its input control end
Frequency analog signal carries out decaying or enhanced processing；
The differential amplifier circuit is used to the differential signal that the programme control circut exports being converted to Single-end output analog signal；
Analog-digital conversion circuit as described is used to the Single-end output analog signal being converted to digital signal.
2. analog-to-digital conversion Acquisition Circuit according to claim 1, which is characterized in that the audio analog signals Acquisition Circuit
Including：Microphone, two resistance, three capacitances；A termination power after the two resistors are connected in series, the other end are answered one end of cylinder, microphone
The other end ground connection；First capacitance connection between the common end and ground of two resistance, second capacitance connection in resistance and
Between the common end and ground of microphone, third capacitance connection is in the common end of resistance and microphone and the fixed gain amplifying circuit
Between.
3. analog-to-digital conversion Acquisition Circuit according to claim 2, which is characterized in that the microphone is Electret condenser microphone.
4. analog-to-digital conversion Acquisition Circuit according to claim 1, which is characterized in that the fixed gain amplifying circuit is selected
PJ4808 chips.
5. analog-to-digital conversion Acquisition Circuit according to claim 1, which is characterized in that the increasing of the fixed gain amplifying circuit
Benefit ranging from 4-8.
6. analog-to-digital conversion Acquisition Circuit according to claim 1, which is characterized in that the programme control circut selects AD8369 cores
Piece.
7. analog-to-digital conversion Acquisition Circuit according to claim 6, which is characterized in that the programme control circut selects AD8369 cores
The number of piece is even number.
8. analog-to-digital conversion Acquisition Circuit according to claim 7, which is characterized in that the programme control circut selects 2
AD8369 chips constitute two-stage.
9. analog-to-digital conversion Acquisition Circuit according to claim 1, which is characterized in that the differential amplifier circuit is selected
INA118 chips.
10. analog-to-digital conversion Acquisition Circuit according to claim 1, which is characterized in that analog-digital conversion circuit as described is selected
ADC122S101 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201721604258.8U CN207638859U (en) | 2017-11-23 | 2017-11-23 | Analog-to-digital conversion Acquisition Circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721604258.8U CN207638859U (en) | 2017-11-23 | 2017-11-23 | Analog-to-digital conversion Acquisition Circuit |
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| Publication Number | Publication Date |
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| CN207638859U true CN207638859U (en) | 2018-07-20 |
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ID=62854086
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929803A (en) * | 2021-02-10 | 2021-06-08 | 歌尔科技有限公司 | Microphone gain adjustment method and related device |
-
2017
- 2017-11-23 CN CN201721604258.8U patent/CN207638859U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929803A (en) * | 2021-02-10 | 2021-06-08 | 歌尔科技有限公司 | Microphone gain adjustment method and related device |
| CN112929803B (en) * | 2021-02-10 | 2022-09-23 | 歌尔科技有限公司 | Microphone gain adjustment method and related device |
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Address after: 518000 2102, building a, wisdom Plaza, Qiaoxiang Road, Gaofa community, Shahe street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Zhongke Lanxun Technology Co., Ltd Address before: 518000 Shenzhen, Guangdong Nanshan District Nantou street, Taoyuan West Road, Qianhai garden 10, 403 rooms. Patentee before: Shenzhen Zhongke blue news Technology Co., Ltd. |