CN207611749U - Ic package and package substrate - Google Patents
Ic package and package substrate Download PDFInfo
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- CN207611749U CN207611749U CN201721399278.6U CN201721399278U CN207611749U CN 207611749 U CN207611749 U CN 207611749U CN 201721399278 U CN201721399278 U CN 201721399278U CN 207611749 U CN207611749 U CN 207611749U
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- Prior art keywords
- layer
- encapsulating structure
- package substrate
- conductive material
- package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The utility model is about ic package and package substrate.Package substrate according to one embodiment of the utility model includes by the fixed upper layer encapsulating structure of non-conductive adhesive and lower layer's encapsulating structure.There is the upper layer encapsulating structure cavity for embedding integrated circuit component to be packaged, the interior slugging pad on lower layer's encapsulating structure to be exposed in the cavity.Ic package and package substrate according to the present utility model, the cavity of integrated circuit component to be packaged is stored by being arranged in the encapsulating structure of upper layer, and upper layer encapsulating structure and lower layer's encapsulating structure are fixed using non-conductive adhesive, technique that can be easy provides package substrate and ic package with good electromagnetic environment and mechanical structure.In the case of being buried in weld pad, the thickness of packaging part can be also further decreased.
Description
Technical field
The utility model is related to technical field of semiconductors, more particularly to the integrated antenna package in technical field of semiconductors
Part and package substrate.
Background technology
With the development of electronic technology and semiconductor technology, requirement of the market to electronic product is higher and higher.Electronic product
While function is highly integrated, size will be remained unchanged and even more be minimized.To adapt to this demand, attempting in the industry will collection
It is embedded in package substrate at circuit element, and carries out the electrical connections configurations such as routing processing inside package substrate.This requires encapsulation
Substrate need to consider more factors in design and manufacture, whether such as process complexity, structural stability, high temperature resistant, be manufactured into
This etc..
Thus, how to provide a kind of package substrate makes it meet the configuration buried in integrated circuit component so that encapsulation is whole
Structure thinning and stable structure, with meet the problem of highdensity integrated circuit demand is technical field of semiconductors sustained improvement it
One.
Utility model content
One of the purpose of this utility model is to provide a kind of ic package and package substrate, integrated circuit component
It can be embedded in package substrate, the high structural stability of ic package is realized so as to easy technique and integrate
Degree.
An embodiment according to the present utility model, a package substrate include：Upper layer encapsulating structure；And lower layer's encapsulation knot
Structure is fixed between the upper layer encapsulating structure and lower layer's encapsulating structure by non-conductive adhesive.
Another embodiment according to the present utility model, at the middle and upper levels encapsulating structure include：First layer of non-conductive material；First
Line layer is located on the upper surface of first layer of non-conductive material；Second line layer is located under first layer of non-conductive material
Surface；Second layer of non-conductive material is located on the lower surface of second line layer；It is second non-conductive to be located at this for tertiary circuit layer
On the lower surface of material layer；And cavity, run through upper surface to the lower surface of the cavity of the upper layer encapsulating structure.The lower layer seals
Assembling structure includes：Third layer of non-conductive material which is provided with connecting hole so that the pin of the tertiary circuit layer is exposed to the connection
Hole；4th line layer is located at the top side of the third layer of non-conductive material；The upper surface of the third layer of non-conductive material and the 4th
The upper surface of line layer is adhered to the lower surface of the tertiary circuit layer；And the 4th line layer be equipped with for it is to be packaged integrated
The weld pad that circuit element is electrically connected, the upper surface of the weld pad is exposed in the cavity；And the 5th line layer, it is located at the third
The bottom side of layer of non-conductive material, and be electrically connected in the connecting hole with the pin of the tertiary circuit layer.
The utility model embodiment additionally provides the ic package manufactured using above-mentioned package substrate.
The ic package and package substrate that the utility model embodiment provides, by being set in the encapsulating structure of upper layer
The cavity for storing integrated circuit component to be packaged is set, and is encapsulated with lower layer using non-conductive adhesive to fix upper layer encapsulating structure
Structure, technique that can be easy provide package substrate and integrated antenna package with good electromagnetic environment and mechanical structure
Part.In the case of being buried in weld pad, the thickness of packaging part can be also further decreased.
Description of the drawings
It is the main technique stream in the manufacturing method according to the package substrate of one embodiment of the utility model shown in Fig. 1 a-1j
The structural schematic diagram for the intermediate products that journey is generated
It is the diagrammatic cross-section according to one embodiment ic package of the utility model shown in Fig. 2
Specific implementation mode
To be better understood from the spirit of the utility model, it is made below in conjunction with the part preferred embodiment of the utility model
It further illustrates.
To meet the needs of integrated circuit component is embedded, package substrate is typically multilayer, such as including one for integrated electricity
The upper layer encapsulating structure and the circuit of the upper layer encapsulating structure is directed under the outer circuit of package substrate that circuit component embeds
Layer encapsulating structure.And it is electrically connected configuration and embedded integrated between the circuit of upper layer encapsulating structure and the circuit of lower layer encapsulating structure
The circuit connection configuration of circuit element is unsuitable configuration mode where this class wrapper substrate main problem to be solved
Thickness may be caused to increase, connect the excessively high problems of unstable or cost.
On ic package, package substrate and its manufacturer's rule that the utility model embodiment is provided can avoid
State problem.For example, an embodiment according to the present utility model, an ic package includes a upper layer encapsulating structure, i.e., on
Layer package substrate, lower layer's encapsulating structure descend layer package substrate, and an at least integrated circuit component.The upper layer encapsulating structure
With can be fixed together by non-conductive adhesive between lower layer encapsulating structure, the weld pad of lower layer's encapsulating structure is exposed to the upper layer
In the cavity of encapsulating structure.At least an integrated circuit component can be embedded in the cavity of the upper layer encapsulating structure, and with the lower layer
Weld pad in encapsulating structure is electrically connected.
Had many advantages, such as according to the ic package of the utility model embodiment, for example, simple process, structure are steady
It is fixed, the thickness of packaging part can be also further decreased by way of being buried in line layer.
Below in conjunction with specific embodiment and attached drawing, the ic package that the utility model embodiment is provided,
Package substrate and its manufacturing method are further described.
It is the main work in the manufacturing method according to the package substrate 100 of one embodiment of the utility model shown in Fig. 1 a-1j
The structural schematic diagram for the intermediate products that skill flow is generated, to which demonstration is according to the package substrate of one embodiment of the utility model
100 manufacturing method.That wherein Fig. 1 a-1e are demonstrated is the manufacturer according to the package substrate 100 of one embodiment of the utility model
About upper layer encapsulating structure 200 in method, that is, the technical process of the manufacturing method of upper layer package substrate, and Fig. 1 f-1h demonstrations
Be in the manufacturing method according to the package substrate 100 of one embodiment of the utility model about lower layer's encapsulating structure 300, i.e. lower layer
The technical process of the manufacturing method of the preform constructions of package substrate.In addition, upper layer encapsulating structure 200 and lower layer's encapsulation knot
The preform constructions of structure 300 are independently formed, and are not limited by the demonstration of the present embodiment, and application combination between the two
Do not limit to the present embodiment, it respectively can be with other encapsulating structure combination applications for matching type.For example, in the present embodiment, under
Layer encapsulating structure 300 top side line layer be it is interior bury form, to further decrease the thickness of package substrate 100.And in other realities
It applies in example, as the skilled personnel can understand, the mode buried in non-can be used completely.In addition, institute in the present embodiment
The orientation such as the upper surface, lower surface, upside, the bottom side that use are to understand that reason uses to explain and facilitating, with drilling in attached drawing
It is shown as benchmark, should not be made excessively to explain and cause the unsuitable limitation to the utility model.
As shown in Figure 1a, it includes providing a first substrate 20 to form upper layer encapsulating structure 200, which may include
First layer of non-conductive material 22 and it is located at the upper surface of first layer of non-conductive material 22 and the first layers of copper of lower surface
202.According to the design requirement of the integrated circuit component (for example, bare die) 102 (referring to Fig. 2) of required encapsulation, can be used milling cutter at
The modes such as type, machine drilling or laser drill are formed on the first substrate 20 through upper surface to the lower surface of the first substrate
Cavity 204, the cross section of the cavity 204 can be round or rectangular equal various shapes.According to the present utility model one implements
The longitudinal section of example, the cavity 204 can be in inverted trapezoidal structure, i.e. bottom opening is small compared with top.It so can be during follow-up plastic packaging
Make the air in cavity 204 be easier to be discharged, the reliability of electrical equipment will not be impacted, it is integrated to be more advantageous to
The encapsulation of circuit element 102.
As shown in Figure 1 b, it may be selected to form the second circuit in the first layers of copper 202 on the lower surface of the first substrate 20
Layer 23 is used as subsequent internal wiring layer, specifically may include using technological means commonly used in this field such as copper facing and etchings, this
Place repeats no more.In other embodiments, also second can be formed in the first layers of copper 202 on the upper surface of the first substrate 20
Line layer 23 is used as subsequent internal wiring layer, and there is no particular limitation.It is subsequently formed on the upper surface of the first substrate 20
First line layer 21 and the second line layer 23 between electric connection can pass through the modes such as configuration through-hole in the first substrate 20
It realizes, because the electric connection between first line layer 21 in the present embodiment and the second line layer 23 only relates to upper layer encapsulating structure
200 internal circuit configuration, details are not described herein again.Certainly, in other embodiments, first line layer 21 and the second line layer 23
Between be electrically connected circuit structure configuration may be formed in cavity 204.It, can be to chamber such as during forming the second line layer 23
204 side wall of body covers copper together, on the one hand improves the shield effectiveness of cavity 204, on the other hand can also make the upper table of first substrate 20
Layers of copper 202 on face is electrically connected with the second line layer 23, to realize first line layer 21 and second line layer
Electric connection between 23.
Then the second layer of non-conductive material 24 is laminated on the lower surface of the second line layer 23 of formation, it can also be non-second
The second thin layers of copper 206 is further formed on conductive material layer 24, as illustrated in figure 1 c.Specific embodiment can be used
Resin (PP, polypropylene) and copper sheet are pressed in two line layers 23 successively, or directly press attached resin copper sheet (RCC,
Resin Coated Copper).The difference is that pressing film needs the processing of fiber stripping, and directly presses RCC and do not need then
And it can get thinner substrate thickness.
As shown in Figure 1 d, the conducting structure 208 through 24 to the second line layer 23 of the second layer of non-conductive material is formed.Example
Such as, the mode of laser drill can be used, form the trepanning through the second layer of non-conductive material 24 and second line layer 23 that arrives, and pass through
Such as copper facing process filling trepanning and form the conducting structure 208 that through-hole fills up.Wherein on the second layer of non-conductive material 24
In the case of being laminated with the second layers of copper 206, drilling need to first run through second layers of copper 206, and second layers of copper during copper facing
206 thickness can also increase makees early-stage preparations to be subsequently formed tertiary circuit layer 25.In other embodiments, the conducting structure
208 can also be blind hole, conduction column or sieve pore conducting structure etc..In the present embodiment, the longitudinal section of conducting structure 208 can be in certainly
Lower and upper width gradually narrows trapezoidal.
As shown in fig. le, the first line layer 21 being laminated on the upper surface of the first layer of non-conductive material 20 can be formed, i.e.,
Upside line layer, and form the tertiary circuit layer 25 being laminated on the lower surface of second layer of non-conductive material 24, i.e. bottom side line
Road floor, specific process can be used the common technology of those skilled in the art institute and realize that details are not described herein again.So far, i.e.,
It can get the upper layer encapsulating structure 200 needed for the utility model embodiment.Certainly, if those skilled in the art are on aforementioned base
To understand, in other embodiments, upper layer encapsulating structure 200 can also design more line layers according to need, no longer superfluous herein
It states.
And the generation type of lower layer's encapsulating structure 300 and the formation of upper layer encapsulating structure 200 have many differences.
As shown in Figure 1 f, when forming lower layer's encapsulating structure 300, a support plate 30 can be first provided, which can be glass
Glass, stainless steel, resin cover the materials such as resin of copper.In the present embodiment, which is used in the form that copper is covered on resin two sides, packet
It includes resin core central layer and is superimposed on the layers of copper (not shown) on opposite two surfaces of the core layer.In view of the layers of copper of support plate itself
Thickness, the 4th thin layers of copper 302 can be further formed on it, to improve the quality of the 4th line layer 32 being subsequently formed simultaneously
Reduce process difficulty.To improve production efficiency, the mode of the two-sided operation on support plate 30 can be used, in the upper table of support plate 30
Face and lower surface are respectively formed on the 4th line layer 32.For the sake of clear, it is described below and is served as theme with the lower face side operation of support plate 30
It is described.
As shown in Figure 1 g, on the lower surface of the 4th line layer 32 third layer of non-conductive material is superimposed by the way of pressing
34, the 5th layers of copper 306 can be also further superimposed on the upper surface of the third layer of non-conductive material 34.In this way, the 4th line layer
32 are embedded in third layer of non-conductive material 34, and the upper surface of only four line layers 32 is exposed to the third layer of non-conductive material 34
Upper surface, so as to further decrease the thickness of encapsulation.In the present embodiment, when being superimposed third layer of non-conductive material 34, also
The line construction that the 4th line layer 32 is electrically connected to 34 outside of third layer of non-conductive material can be configured inside it, to ensure
Electric connection between 4th line layer 32 and the 5th line layer 36 being subsequently formed.
As shown in figure 1h, then peelable 4th layers of copper 302 and support plate 30 to obtain being formed on the both sides of support plate 30
Counter structure.Such as the 4th layers of copper 302 can be removed from support plate 30, that is, plate is solved, then leads to overetched mode by the 4th bronze medal
302 ablation of layer.Non-conductive adhesive 308, including exposure are coated on the upper surface of third layer of non-conductive material 34 after stripping
The upper surface of the 4th line layer 32 outside.And in the bottom side line layer of corresponding upper layer encapsulating structure 200, i.e. tertiary circuit layer 25
The position of pin 250 drill to form link slot 310.For the non-conductive adhesive 308 coated on the 4th line layer 32, can swash
The modes such as light or fishing side (route) remove the non-conductive adhesive at the position of the cavity 204 on corresponding upper layer encapsulating structure 200
308.So far, preforming lower layer's encapsulating structure 312 can be formed, why becomes preforming lower layer's encapsulating structure 312 herein
It is because the bottom side line layer of lower layer's encapsulating structure 312 has not yet been formed.
The combination upper layer encapsulating structure 200 that Fig. 1 i-1j are demonstrated and preforming lower layer's encapsulating structure 312, to obtain root
According to the package substrate 100 of one embodiment of the utility model.
Specifically, as shown in figure 1i, upper layer encapsulating structure 200 and preforming lower layer's encapsulating structure 312 are led by non-
Electric bonding agent 308 bonds together, i.e. the bottom side line layer of upper layer encapsulating structure 200, such as the tertiary circuit layer in the present embodiment
25 with the upside line layer of lower layer's encapsulating structure 300, such as 32 be adhesively fixed of the 4th line layer in the present embodiment.Its
In, the pin 250 in the tertiary circuit layer 25 is exposed in the link slot of preforming lower layer's encapsulating structure 312, the 4th line
Weld pad 320 in road floor 32 for integrated circuit component 102 to be packaged is exposed in the cavity 204 of the upper layer encapsulating structure.It can
Further nickel plating or copper protection are made to the weld pad 320 being exposed in cavity 204, to ensure and packaged integrated circuit component
Electric connection reliability between 102.In addition, an embodiment according to the present utility model, can also set in the 4th line layer 32
Ground structure is set, so as to generate screen effect, 204 structure of cavity is avoided to be destroyed by electrostatic charge.
As shown in fig. ij, the bottom side line layer of lower layer's encapsulating structure 312 is formed, that is, the 5th line layer 36, and realize the 5th
Electric connection between line layer 36 and tertiary circuit layer 25.For example, electroless coating can be covered at the top of upper layer encapsulating structure 200
Dry film, then in the bottom side of lower layer's encapsulating structure 300, i.e. the lower surface of the 5th layers of copper 306 carries out the techniques such as electro-coppering and etching
Processing obtains the 5th line layer 36.250 electricity of pin of part of 5th line layer 36 in link slot 310 and tertiary circuit layer 25
Property connection, to which the signal of tertiary circuit layer 25 led to outboard circuit layer.In the present embodiment, the only cell wall of link slot 310 plates
There is copper, and in other embodiments, it may also fill up.Hereafter it removes covered electroless coating dry film and can be obtained this practicality newly
The package substrate 100 of type embodiment.
Specifically, including upper layer encapsulation knot according to the package substrate 100 of one embodiment of the utility model as shown in fig. ij
Structure 200 and the lower layer's encapsulating structure 300 being bonded together with the upper layer encapsulating structure.
The upper layer encapsulating structure 200 includes：First layer of non-conductive material 22, the second layer of non-conductive material 24, first line
The 21, second line layer 23 of layer, tertiary circuit layer 25, and the chamber through the upper surface of the upper layer encapsulating structure 200 to lower surface
Body 204.The first line layer 21 and the second line layer 23 are laminated in the upper surface of first layer of non-conductive material 22 under respectively
Surface, and be electrically connected between the first line layer 21 and the second line layer 23.Second layer of non-conductive material 24 be laminated in this
The lower surface of two line layers 23, and the tertiary circuit layer 25 is then laminated in the lower surface of second layer of non-conductive material 24, i.e., should
Second line layer 23 is located at the upper surface and lower surface of second layer of non-conductive material 24 with the tertiary circuit layer 25.Together
Sample is electrically connected between second line layer 23 and the tertiary circuit layer 25.In one embodiment, first line layer 21 and second
Conducting structure between line layer 23 can cover the inner wall of cavity 204.
Lower layer's encapsulating structure 300 includes：Third layer of non-conductive material 34, the 4th line layer 32 and the 5th line layer 36,
Wherein the 4th line layer 32 and the 5th line layer 36 are located at the top side and bottom side of the third layer of non-conductive material 34, and two
It is electrically connected between person.32 upper surface of third layer of non-conductive material and the upper surface of the 4th line layer 32 are adhered to upper layer encapsulation
The lower surface of the tertiary circuit layer 25 of structure 200.In the present embodiment, it is embedded in the non-conductive material of the third in the 4th line layer 32
The top side of the bed of material 34, therefore the upper surface of third layer of non-conductive material 34 and the 4th line layer 32 is in the same plane.It is wherein corresponding
Pin locations in tertiary circuit layer 25, the third layer of non-conductive material 34 are equipped with the connection through its upper surface to lower surface
Hole 310 by pin to be exposed to the connecting hole 310, so that tertiary circuit layer 25 and the 5th line layer 32 can be in connecting holes
310 positions are electrically connected.In addition the weld pad 320 for integrated circuit component 102 to be packaged on the 4th line layer 32 is sudden and violent
It is exposed to the bottom of cavity 204, is electrically connected so as to be realized with the integrated circuit component 102 in the embedded cavity 204.
Integrated circuit component 102 to be packaged is embedded in the package substrate 100 provided according to the utility model embodiment
In cavity 204, and its weld pad 320 provided with lower layer encapsulating structure 300 is electrically connected by modes such as leads 104, you can
Obtain the ic package 400 that the utility model embodiment is provided.In other embodiments, integrated circuit to be packaged
Element 102 can be also electrically connected by the modes such as surface mount and weld pad 320.The periphery of cavity 204 is set in weld pad 320
In the case of, the usage amount for saving lead can be conducive to, to reduce cost.It is to be implemented according to the utility model one shown in Fig. 2
The diagrammatic cross-section of example ic package 400.As shown in Fig. 2, the ic package 400 includes being sealed shown in Fig. 1 j
Dress substrate 100 and the integrated circuit component 102 being embedded in the package substrate 100.
The technology contents and technical characterstic of the utility model have revealed that as above, however those skilled in the art still may be used
Teaching and announcement that can be based on the utility model and make various replacements and modification without departing substantially from the spirit of the present invention.Therefore, originally
The protection domain of utility model should be not limited to the revealed content of embodiment, and should include various replacing without departing substantially from the utility model
It changes and modifies, and covered by present patent application claims.
Claims (7)
1. a kind of package substrate, it is characterised in that the package substrate includes：
Upper layer encapsulating structure, wherein the upper layer encapsulating structure includes：
First layer of non-conductive material；
First line layer is located on the upper surface of first layer of non-conductive material；
Second line layer is located at the lower surface of first layer of non-conductive material；
Second layer of non-conductive material is located on the lower surface of second line layer；
Tertiary circuit layer is located on the lower surface of second layer of non-conductive material；And
Cavity runs through upper surface to the lower surface of the cavity of the upper layer encapsulating structure；And
Lower layer's encapsulating structure is fixed between the upper layer encapsulating structure and lower layer's encapsulating structure by non-conductive adhesive,
Described in lower layer's encapsulating structure include：
Third layer of non-conductive material which is provided with connecting hole so that the pin of the tertiary circuit layer is exposed to the connecting hole；
4th line layer is located at the top side of the third layer of non-conductive material；The upper surface of the third layer of non-conductive material with
The upper surface of 4th line layer is adhered to the lower surface of the tertiary circuit layer；And the 4th line layer is equipped with and is used for
The weld pad being electrically connected with integrated circuit component to be packaged, the upper surface of the weld pad is exposed in the cavity；And
5th line layer is located at the bottom side of the third layer of non-conductive material, and with the pin of the tertiary circuit layer described
It is electrically connected in connecting hole.
2. package substrate according to claim 1, it is characterised in that the first line layer and second line layer it
Between conducting structure cover the inner wall of the cavity.
3. package substrate according to claim 1, it is characterised in that the longitudinal section of the cavity in width from top to bottom by
It tapers narrow trapezoidal.
4. package substrate according to claim 1, it is characterised in that second line layer and the tertiary circuit layer it
Between the conducting structure through-hole, conduction column or the sieve pore conducting structure that are blind hole, fill up.
5. package substrate according to claim 1, it is characterised in that the 4th line layer has ground structure.
6. package substrate according to claim 1, it is characterised in that be embedded in that the third is non-to be led in the 4th line layer
Material layer.
7. a kind of ic package, it is characterised in that the ic package includes：
Package substrate as described in any one of claim 1-6；And
Integrated circuit component is embedded in the package substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721399278.6U CN207611749U (en) | 2017-10-26 | 2017-10-26 | Ic package and package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721399278.6U CN207611749U (en) | 2017-10-26 | 2017-10-26 | Ic package and package substrate |
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| Publication Number | Publication Date |
|---|---|
| CN207611749U true CN207611749U (en) | 2018-07-13 |
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ID=62793979
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721399278.6U Active CN207611749U (en) | 2017-10-26 | 2017-10-26 | Ic package and package substrate |
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| CN (1) | CN207611749U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731698A (en) * | 2017-10-26 | 2018-02-23 | 日月光半导体(上海)有限公司 | Ic package, package substrate and its manufacture method |
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2017
- 2017-10-26 CN CN201721399278.6U patent/CN207611749U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731698A (en) * | 2017-10-26 | 2018-02-23 | 日月光半导体(上海)有限公司 | Ic package, package substrate and its manufacture method |
| CN107731698B (en) * | 2017-10-26 | 2024-03-26 | 日月光半导体(上海)有限公司 | Integrated circuit package, package substrate and manufacturing method thereof |
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