CN207573381U - A kind of remote message for Modbus buses records system - Google Patents
A kind of remote message for Modbus buses records system Download PDFInfo
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- CN207573381U CN207573381U CN201721546502.XU CN201721546502U CN207573381U CN 207573381 U CN207573381 U CN 207573381U CN 201721546502 U CN201721546502 U CN 201721546502U CN 207573381 U CN207573381 U CN 207573381U
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Abstract
The utility model is related to a kind of remote messages for Modbus buses to record system, in addition to the existing module of existing system, further include local data cache module, specifically include sequentially connected monitoring interface, decoding signals, first processor and fpga chip, multiple built-in network interfaces are provided on fpga chip, each built-in network interface is connect with a RAM；First processor is also connect with data transmission bus interface chip, and data transmission bus interface chip is equipped with multiple first data transmission bus ports, is connect with caching subelement；Local data cache module further includes transmission control circuit and power supply interface, and power supply interface is connect with externally fed circuit, transmission control circuit, first processor and fpga chip, and transmission control circuit is connect with first processor.Compared with prior art, the utility model has many advantages, such as that packet buffer amount is big, packet data transmission is stable and at low cost.
Description
Technical field
The utility model is related to the data monitoring field of Modbus buses, more particularly, to a kind of for Modbus buses
Remote message records system.
Background technology
Modbus agreements are a kind of all-purpose languages being applied on electronic controller.By this agreement, controller mutually it
Between, controller can communicate via network (such as Ethernet) between miscellaneous equipment.It has become a kind of universal industrial mark
It is accurate.There is it, the control device of different vendor's production can be linked to be industrial network, carry out Centralized Monitoring.This protocol define one
A controller can recognize the message structure used, communicate but regardless of them by which kind of network.It describes one
Controller request accesses the process of miscellaneous equipment, how to respond the request from miscellaneous equipment and how to detect mistake and remember
Record.It has formulated the common format of message field layout and content.
As the application of Modbus communication protocols is more extensive, also seem more for the record of message in Modbus buses
It is important, in the prior art, when carrying out remote message record for Modbus buses, often turn simply by by the data in bus
It after turning to the message added with timestamp, is written in RAM by processor, then is carried out the data in RAM by Ethernet
Transmission, writes the data to eventually by another processor in server, and this method has following problem：It is place first
Reason device can only be often attached with single RAM, therefore be for the caching of message it is extremely limited, it is big in message data amount
When, if carrying out network transmission, it is easy to cause the packet loss of data；In addition when writing data into RAM by processor, due to
Processor is powered by external circuit, unstable due to supply voltage, and there is a situation where lose message data.
Utility model content
The purpose of this utility model is to provide a kind of remote message for Modbus buses regarding to the issue above to record system
System.
The purpose of this utility model can be achieved through the following technical solutions：
A kind of remote message for Modbus buses records system, including sequentially connected local data cache module,
Network transmission module and second processor, the local data cache module are connect with Modbus buses, the second processor
It is connect with server, the local data cache module includes sequentially connected monitoring interface, decoding signals, first processor
And fpga chip, multiple built-in network interfaces are provided on the fpga chip, each built-in network interface is connect with a RAM, all
RAM is connect with network transmission module；The first processor is also connect with data transmission bus interface chip, and the data pass
One end of defeated Bus Interface Chip is connect with first processor, and the other end is equipped with multiple first data transmission bus ports, each
First data transmission bus port is connect with a caching subelement, and all caching subelements connect with network transmission module
It connects；The local data cache module further includes transmission control circuit and power supply interface, the input terminal of the power supply interface with it is outer
Portion's power supply circuit connection, output terminal is connect respectively with the input terminal of transmission control circuit, first processor and fpga chip, described
The output terminal of transmission control circuit is connect with first processor.
Preferably, the transmission control circuit includes first comparator, the second comparator, the first diode and the two or two pole
Pipe, the output terminal of the power supply interface connect respectively with the negative input of the electrode input end of first comparator and the second comparator
It connects, the output terminal of the first comparator and the second comparator connects first processor jointly after connecting.
Preferably, first resistor, the power supply interface are additionally provided between the power supply interface and the anode of first comparator
Second resistance is additionally provided between the cathode of the second comparator.
Preferably, the built-in network interface quantity on the fpga chip is no less than 2.
Preferably, the quantity of the first data transmission bus port is no less than 2.
Preferably, the caching subelement includes the second data transmission bus port being connected with each other and bus adapter,
The second data transmission bus port is connect by data transmission bus with first data transmission bus port, and the bus is fitted
Multiple external network ports are equipped with card, each external network port is connect with a RAM, and all RAM connect with network transmission module
It connects.
Preferably, the quantity of the external network port is no less than 2.
Preferably, the network transmission module includes wired transmission assembly or wireless transmission component.
Preferably, the wire transmission component includes ethernet line, the both ends of the ethernet line respectively with all RAM
It is connected with second processor.
Preferably, the wireless transmission component includes radio signal senders and wireless signal receiver, the wireless communication
Number transmitter is connect respectively with all RAM, and the wireless signal receiver is connect with second processor, the wireless signal hair
It send between device and wireless signal receiver by wirelessly communicating.
Compared with prior art, the utility model has the advantages that：
(1) by the way that first processor is connect with the fpga chip with multiple network interfaces, and each net of fpga chip
Mouthful can connect with a RAM, it, can be with simultaneously because FPGA is with multiple network interfaces so as to effectively extend buffer memory capacity
The parallel buffer of message data is realized, so as in the case where respective memory failure can not realize data buffer storage, still protect
The normal cache of message is demonstrate,proved, avoids packet loss；Other than fpga chip, first processor also with data transmission bus interface chip
Connection, data transmission bus interface chip are equipped with multiple first data transmission bus ports, and each port can also be with one
Subelement connection is cached, therefore the capacity of data buffer storage is further extended from outside, coordinates with fpga chip, can realize super
The message data caching of large capacity；Increase transmission control circuit simultaneously, the input terminal of the transmission control circuit and power supply interface
Output terminal connects, so as to realize the monitoring to power supply interface output voltage, when voltage is not in the range of defined threshold, to
First processor exports high level, and first processor is reminded to temporarily cease the data transmission of message at present, avoids due to power supply electricity
It presses the unstable and message transmissions error that occurs or loses message.
(2) transmission control circuit includes two comparators, the electrode input end of first comparator and the second comparator it is negative
Pole input terminal is connect with power supply interface, and the electrode input end of the first stronger negative input and the second comparator then divides
It can not be connect with two endpoint threshold voltages of the threshold voltage in first processor normal range of operation, so as in power supply interface
Output voltage in threshold range when export low level, export high level when in threshold range, pass through two comparisons
The operating voltage of first processor can be monitored in a threshold range, both avoided by the transmission control circuit that device is formed
The brownout of first processor also avoids happening for overtension.
(3) first resistor, power supply interface and the second comparator are additionally provided between power supply interface and the anode of first comparator
Cathode between be additionally provided with second resistance, by the setting of resistance, avoid due to the presence of high current and burn out comparator, from
Caused by transmission control circuit fail.
(4) the built-in network interface quantity on fpga chip and the quantity of first data transmission bus port are no less than 2, can
To ensure the realization of the expanded function of data buffer storage, the waste on hardware will not be caused.
(5) each caching subelement includes the second data transmission bus port being connected with each other and bus adapter, the
Two data transmission bus ports are connect by data transmission bus with first data transmission bus port, it is achieved thereby that message number
According to stablize and transmit, after storage inside data are carried out also close to spilling by FPGA, external caching subelement can be utilized
It further being stored, and bus adapter is equipped with multiple external network ports, each external network port is connect with a RAM,
It can realize that the geometry multiple of RAM increases, while the quantity of external network port is quite a few in 2, equally ensure that will not cause firmly
The waste of part.
(6) network transmission module includes wired transmission assembly or wireless transmission component, in the situation of hypothesis cable of having ready conditions
Under, it can be transmitted by wire transmission component, that is, ethernet line, fast with speed and stable by ethernet line transmission
Advantage, it is ensured that the integrality of packet storage；And be not suitable in region residing for bus in the case of assuming wired network, then it can be with
By being wirelessly transferred component, by the wireless communication between radio signal senders and wireless signal receiver, it can overcome ground
The limitation of manage bar part；Two kinds of transmission modes can be selected according to actual conditions, improve the flexibility of total system.
Description of the drawings
Fig. 1 is the structure diagram of the remote message record system for Modbus buses；
Fig. 2 is the structure diagram for caching subelement；
Wherein, 1 is Modbus buses, and 2 is monitor interface, and 3 be decoding signals, and 4 be first processor, and 5 be FPGA cores
Piece, 6 be built-in network interface, and 7 be RAM, and 8 be power supply interface, and 9 be transmission control circuit, and 10 be externally fed circuit, and 11 pass for network
Defeated module, 12 be second processor, and 13 be server, and 14 be data transmission bus interface chip, and 15 is total for first data transmission
Line end mouth, 16 is cache subelement, and 17 be the second data transmission bus port, and 18 be bus adapter, and 19 be external network port.
Specific embodiment
The utility model is described in detail in the following with reference to the drawings and specific embodiments.The present embodiment is with the utility model
Implemented premised on technical solution, give detailed embodiment and specific operating process, but the guarantor of the utility model
Shield range is not limited to following embodiments.
As shown in Figure 1, present embodiments providing a kind of remote message for Modbus buses records system, including successively
Local data cache module, network transmission module 11 and the second processor 12 of connection, local data cache module and Modbus
Bus 1 connects, and second processor 12 is connect with server 13, local data cache module include it is sequentially connected monitoring interface 2,
Decoding signals 3, first processor 4 and fpga chip 5 are provided with multiple built-in network interfaces 6, each built-in net on fpga chip 5
Mouth 6 is connect with a RAM7, and all RAM7 are connect with network transmission module 11；First processor 4 is also total with data transmission
Line interface chip 14 connects, and one end of data transmission bus interface chip 14 is connect with first processor 4, and the other end is equipped with multiple
First data transmission bus port 15, each first data transmission bus port 15 are connect with a caching subelement 16, institute
There is caching subelement 16 to be connect with network transmission module 11；Local data cache module further includes transmission control circuit 9 and supplies
Electrical interface 8, the input terminal of power supply interface 8 are connect with externally fed circuit 10, the output terminal input with transmission control circuit 9 respectively
End, first processor 4 and fpga chip 5 connect, and the output terminal of transmission control circuit 9 is connect with first processor 4.
Wherein, transmission control circuit 9 includes first comparator, the second comparator, the first diode and the second diode, supplies
Negative input of the output terminal of electrical interface 8 respectively with the electrode input end of first comparator and the second comparator is connect, and first
The output terminal of comparator and the second comparator connects first processor 4 jointly after connecting.Power supply interface 8 and first comparator are just
First resistor is additionally provided between pole, second resistance is additionally provided between the cathode of 8 and second comparator of power supply interface.Fpga chip 5
On 6 quantity of built-in network interface generally no less than 2, be 4 (there are one be not drawn into), first data transmission bus in the present embodiment
The quantity of port 15 is quite a few in 2, is 2 in the present embodiment.
As shown in Fig. 2, caching subelement 16 includes the second data transmission bus port 17 being connected with each other and bus adaption
Card 18, the second data transmission bus port 17 is connect by data transmission bus with first data transmission bus port 15, bus
Adapter 18 is equipped with multiple external network ports 19, and each external network port 19 connect with a RAM7, and all RAM7 are and network
Transmission module 11 connects.The quantity of external network port 19 generally no less than 2 is 3 in the present embodiment.Network transmission module 11 wraps
Include wire transmission component or wireless transmission component.Wire transmission component includes ethernet line, the both ends of ethernet line respectively with institute
Some RAM7 and second processor 12 connect.It is wirelessly transferred component and includes radio signal senders and wireless signal receiver, nothing
Line sender unit is connect respectively with all RAM7, and wireless signal receiver is connect with second processor 12, wireless signal hair
It send between device and wireless signal receiver by wirelessly communicating.
The operation principle of the system is as follows：Interface 2 is first listened to be acquired the message data in Modbus buses 1,
Message data is converted to Transistor-Transistor Logic level signal while acquisition, the Transistor-Transistor Logic level signal entering signal decoder 3 after conversion, letter
Number decoder 3 is then converted to message data after being parsed to it, while adds in timestamp in message data so as to obtain band
The message log files of having time, first processor 4 by the content of the log files by multiple built-in network interfaces 6 of fpga chip 5,
Parallel being written in the RAM7 being connect with each built-in network interface 6 is cached, and the write-in behaviour of message is carried out in first processor 4
When making, the voltage that externally fed circuit 10 provides is respectively transmitted in first processor 4 and fpga chip 5 by power supply interface 8, is
It is powered.Due to the voltage instability that externally fed circuit 10 generally provides, in order to ensure the stability of data write-in, transmission control
Two comparators in circuit 9 carry out the comparison of voltage by being connected with the output terminal of power supply interface 8, it can be seen from the figure that
When the output voltage of power supply interface 8 is between U2 and U1, the first diode and the second diode export low level at first
Device 4 is managed, first processor 4 is normally carried out write-in caching of the data into RAM7 at this time, and the output voltage in power supply interface 8 is low
In U2 or during higher than U1, the first diode and the second diode export high level to first processor 4, at this time first processor 4
Stop carrying out write-in of the data into RAM7, until the low level for receiving the output of transmission control circuit 9.Containing having time
Message log file caches to RAM7 in after, second processor 12 is transmitted to by network transmission module 11, it is total in Modbus
Region residing for line 1 is easy to set up in the case that cable or cost be less than budget, can select ethernet line as network transmission
The realization method of module 11, at this time under the control of second processor 12, message data is transmitted to server with corresponding speed
In 13, second processor 12 avoids writing speed too fast and packet loss occurs primarily to regulation and control data transmission bauds；And
If region residing for Modbus buses 1 is not suitable for assuming cable or assumes that the cost of cable is excessively high more than affordability, can
By the cooperation of radio signal senders and wireless signal receiver, to send data to second processor 12, then pass through
Data are uploaded to server 13 by two processors 12.
If the RAM7 that network interface 6 built in fpga chip 5 is connected does not include enough spatial caches, it can call
The data transmission bus interface chip 14 being connect with first processor 4, the readwrite performance of the chip are slightly below fpga chip 5, because
This is less than fpga chip 5 in the priority of caching, total in data transmission first in the transmission that message is carried out by the chip
Multiple first data transmission bus ports 15 carry out parallel data transmission on line interface chip 14, and each first data transmission is total
Line end mouth 15 is connect with a caching subelement 16, and data are entered by data transmission bus in caching subelement 16
Behind second data transmission bus port 17, via the external network port 19 on bus adapter 18, enter eventually into it is each with it is external
In the RAM7 that network interface 19 connects, realize the further caching of message, be finally uploaded to server 13 via network transmission module 11
In.
By aforesaid operations, network interface 6 built in one side FPGA connects multiple RAM7 and data transmission bus interface chip 14
The setting of multiple RAM7 is also connected by external network port 19 can also can as possible avoid counting when message data amount is excessive
According to spilling, realize the data buffer storage of large capacity；On the other hand pass through transmission control circuit 9, it is ensured that first processor 4
The write-in of data can be just carried out only when supply voltage is in threshold value, is avoided due to carrying out data during supply voltage over range
The situation that message data is lost caused by write-in.
Claims (10)
1. a kind of remote message for Modbus buses records system, including sequentially connected local data cache module, net
Network transmission module and second processor, the local data cache module are connect with Modbus buses, the second processor with
Server connect, which is characterized in that the local data cache module include it is sequentially connected monitoring interface, decoding signals,
First processor and fpga chip are provided with multiple built-in network interfaces, each built-in network interface and a RAM company on the fpga chip
It connects, all RAM are connect with network transmission module；The first processor is also connect with data transmission bus interface chip,
One end of the data transmission bus interface chip is connect with first processor, and the other end is equipped with multiple first data transmission buses
Port, each first data transmission bus port are connect with a caching subelement, and all caching subelements are passed with network
Defeated module connection；The local data cache module further includes transmission control circuit and power supply interface, the power supply interface it is defeated
Enter end to connect with externally fed circuit, output terminal respectively with the input terminal of transmission control circuit, first processor and fpga chip
Connection, the output terminal of the transmission control circuit are connect with first processor.
2. the remote message according to claim 1 for Modbus buses records system, which is characterized in that the transmission
Control circuit includes first comparator, the second comparator, the first diode and the second diode, the output terminal of the power supply interface
The negative input with the electrode input end of first comparator and the second comparator is connect respectively, the first comparator and second
The output terminal of comparator connects first processor jointly after connecting.
3. the remote message according to claim 2 for Modbus buses records system, which is characterized in that the power supply
First resistor is additionally provided between interface and the anode of first comparator, between the power supply interface and the cathode of the second comparator also
Equipped with second resistance.
4. the remote message according to claim 1 for Modbus buses records system, which is characterized in that the FPGA
Built-in network interface quantity on chip is no less than 2.
5. the remote message according to claim 1 for Modbus buses records system, which is characterized in that described first
The quantity of data transmission bus port is no less than 2.
6. the remote message according to claim 1 for Modbus buses records system, which is characterized in that the caching
Subelement includes the second data transmission bus port being connected with each other and bus adapter, the second data transmission bus port
It being connect by data transmission bus with first data transmission bus port, the bus adapter is equipped with multiple external network ports,
Each external network port is connect with a RAM, and all RAM are connect with network transmission module.
7. the remote message according to claim 6 for Modbus buses records system, which is characterized in that described external
The quantity of network interface is no less than 2.
8. the remote message according to claim 1 for Modbus buses records system, which is characterized in that the network
Transmission module includes wired transmission assembly or wireless transmission component.
9. the remote message according to claim 8 for Modbus buses records system, which is characterized in that described wired
Transmission assembly includes ethernet line, and the both ends of the ethernet line are connect respectively with all RAM and second processor.
10. the remote message according to claim 8 for Modbus buses records system, which is characterized in that the nothing
Line transmission assembly include radio signal senders and wireless signal receiver, the radio signal senders respectively with it is all
RAM connections, the wireless signal receiver are connect with second processor, the radio signal senders and wireless signal receiver
Between by wirelessly communicating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721546502.XU CN207573381U (en) | 2017-11-17 | 2017-11-17 | A kind of remote message for Modbus buses records system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721546502.XU CN207573381U (en) | 2017-11-17 | 2017-11-17 | A kind of remote message for Modbus buses records system |
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| Publication Number | Publication Date |
|---|---|
| CN207573381U true CN207573381U (en) | 2018-07-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721546502.XU Expired - Fee Related CN207573381U (en) | 2017-11-17 | 2017-11-17 | A kind of remote message for Modbus buses records system |
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2017
- 2017-11-17 CN CN201721546502.XU patent/CN207573381U/en not_active Expired - Fee Related
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Address after: 200436, No. 1198, Wanrong Road, Shanghai, Jingan District, 5 floor Patentee after: Shanghai Shangshi longchuang Intelligent Technology Co.,Ltd. Address before: 200436, No. 1198, Wanrong Road, Shanghai, Jingan District, 5 floor Patentee before: SHANGHAI SIIC-LONGCHUANG SMARTER ENERGY TECHNOLOGY Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180703 |