CN207557745U - A kind of bus marco board based on PC digital control systems - Google Patents
A kind of bus marco board based on PC digital control systems Download PDFInfo
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- CN207557745U CN207557745U CN201721614046.8U CN201721614046U CN207557745U CN 207557745 U CN207557745 U CN 207557745U CN 201721614046 U CN201721614046 U CN 201721614046U CN 207557745 U CN207557745 U CN 207557745U
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Abstract
The utility model discloses a kind of bus marco boards based on PC digital control systems, relate to field of industrial automation control, including bus marco board, PC digital control systems, number I/O Control cards, motor shaft Control card and expanded function control module；The PC digital control systems are connect by pci bus with the bus marco board realizes data communication control, the number I/O Control cards, the motor shaft Control card are connect respectively by the form of circuit with the bus marco board, and the bus marco board controls its functional circuit after being communicated by parallel bus with the expanded function control module.Bus marco board based on PC digital control systems described in the present embodiment is with high-performance, at low cost, standardization level is high, reliability is high, software and hardware resources enrich and is easy to the advantages such as information integration.
Description
Technical field
The utility model is related to field of industrial automation control more particularly to a kind of bus marcos based on PC digital control systems
Board.
Background technology
At present, bus marco board generally uses special-purpose numerical control system, particularly PCI (Peripheral Component Interconnect marks in the market
Quasi- Peripheral Component Interconnect) bus controller card, the special-purpose numerical control system is by ARM (microprocessors
Advanced RISC Machines), DSP (Digital Signal Processing Digital Signal Processing), the controls such as microcontroller
Device processed and other control circuits composition, its process performance is poor, a small amount of production cost is high, software and hardware resources are not abundant enough, inconvenient
In information integration.
Therefore, bus marco board how to be made to improve process performance, abundant software and hardware resources, facilitate information integration, and drop
Low production cost becomes the technical issues of urgently to be resolved hurrily.
Utility model content
The purpose of this utility model is that for technical problem of the existing technology, provide a kind of based on PC
The bus marco board of (Personal Computer personal computers) digital control system, solves existing bus marco board and adopts
During with special-purpose numerical control system, process performance is poor, production cost is high, software and hardware resources are not abundant enough, information integration is difficult asks
Topic.
Technical solution is used by the utility model solves its technical problem：
The utility model embodiment provides a kind of bus marco board based on PC digital control systems, including bus marco plate
Card, PC digital control systems, number I/O Control cards, motor shaft Control card and expanded function control module；
The PC digital control systems are connect by pci bus with the bus marco board realizes data communication control, described
Digital I/O Control cards, the motor shaft Control card are connect respectively by the form of circuit with the bus marco board, institute
It states after bus marco board is communicated by parallel bus with the expanded function control module and controls its functional circuit；
The PC digital control systems control the number I/O Control cards, the electricity by the bus marco Labcard driver
Arbor Control card and the expanded function control module.
As further improvement of the utility model, the bus marco board includes FPGA programmable logic controller (PLC)s
110th, number I/O card interfaces, motor shaft card interface, expanded function control module interface, pci bus interface and level conversion list
Member；
The PC digital control systems are connected to the FPGA programmable logic controller (PLC)s by the pci bus interface；
The number I/O Control cards are connected to the FPGA Programmable logical controllers by the number I/O card interfaces
On device 110, in the data transmission to the number I/O Control cards of the FPGA programmable logic controller (PLC)s；
The motor shaft Control card is connected to the FPGA programmable logic controller (PLC)s by the motor shaft card interface
On, in the data transmission to the motor shaft Control card of the FPGA programmable logic controller (PLC)s；
The expanded function control module is connected by the level conversion unit and the expanded function control module interface
It is connected on the FPGA programmable logic controller (PLC)s, the data transmission of the FPGA programmable logic controller (PLC)s to the extension work(
On energy control module.
As further improvement of the utility model, the bus marco board further include detection module, power supply instruction and
Output module and memory management module；
The detection module, the power supply instruction and output module, the memory management module pass through the shape of circuit respectively
Formula is connect with the FPGA programmable logic controller (PLC)s.
As further improvement of the utility model, voltage-stabilized power supply circuit is additionally provided on the bus marco board, it is described
Voltage-stabilized power supply circuit includes：The battery being connect with the memory management module, the +/- 12V electricity being connect with the pci bus interface
Source and 5V power supplys；
3.3V power supplys are in series on the 5V power supplys, and a 2.5V power supply of connecting on the 3.3V power supplys.
As further improvement of the utility model, the FPGA programmable logic controller (PLC)s insertion expanded function control mould
ID signals are generated after the communication control logic of block interface, and are controlled by the ID signal generating circuits；
Resistance R106, resistance R107, resistance R108, diode are included according to the circuit that the ID signal generating circuits control
D14, field-effect tube Q1 and+12V power supplys；Wherein, the pin 2 of resistance R106 is imitated after being connected to one end of diode D14 with field
Should the pin 2 of pipe Q1 connect, the other end ground connection of diode D14, the pin 3 of field-effect tube Q1 connects with the pin 1 of resistance R107
It is connect with+12V power supplys after connecing, after the pin 1 of field-effect tube Q1 is connect with the pin 2 of resistance R107, is connected to resistance R108's
On pin 1；The pin 1 of resistance R106 is signal input part, and the pin 2 of resistance R108 is signal output end.
As further improvement of the utility model, the level conversion unit includes single-ended signal voltage being converted to difference
The circuit of sub-signal voltage and the circuit that differential signal voltage is converted to single-ended signal voltage.
As further improvement of the utility model, the electricity that single-ended signal voltage is converted to differential signal voltage
Road includes：
PA0~PA3 ports be connected respectively U32 chips pin 1,7,9,15, PA4~PA7 ports correspond to respectively
It is connected to the pin 1,7,9,15 of U34 chips；+ DIFFA0~+DIFFA3 ports be connected respectively U32 chips pin 2,
6th, 10,14 ,-DIFFA0~-DIFFA3 ports are connected respectively the pin 3,5,11,13 of U32 chips, and+DIFFA4~+
DIFFA7 ports are connected respectively the pin 2,6,10,14 of U34 chips, and-DIFFA4~-DIFFA7 ports are corresponding respectively to be connected
It is connected to the pin 3,5,11,13 of U34 chips；
Wherein, PA0~PA7 ports are signal input port ,+DIFFA0~+DIFFA7 ports and-DIFFA0~-
DIFFA7 ports are signal output port.
As further improvement of the utility model, the circuit that differential signal voltage is converted to single-ended signal voltage
Including：
+ DIFFB0~+DIFFB3 ports are connected respectively the pin 2,6,10,14 of U36 chips, and-DIFFB0~-
DIFFB3 ports are connected respectively the pin 1,7,9,15 of U36 chips, and+DIFFB4~+DIFFB7 ports are corresponding respectively to be connected
Be connected to the pin 2,6,10,14 of U37 chips ,-DIFFB4~-DIFFB7 ports be connected respectively U37 chips pin 1,
7、9、15；In addition, PB0~PB3 ports be connected respectively U36 chips pin 3,5,11,13, PB4~PB7 ports difference
It is correspondingly connected with the pin 3,5,11,13 of U37 chips；Wherein, PB0~PB7 ports be signal input port ,+DIFFB0~+
DIFFB7 ports and-DIFFB0~-DIFFB7 ports are signal output port；
In addition, the resistance R98 that resistance value is 100 is connected between+DIFFB0 ports and-DIFFB0 ports, and so on ,+
The resistance value that connects one to one between DIFFB1~+DIFFB7 ports and-DIFFB1~-DIFFB17 ports is 100 resistance
R100、R101、R99、R102、R104、R105、R103
Compared with prior art, the beneficial effects of the utility model are：
In the embodiment of the utility model, the PC digital control systems are the control axis of entire bus marco board, and
The number I/O Control cards, the motor shaft Control card and the expansion are controlled by the bus marco Labcard driver
Functional control module is opened up, it is achieved thereby that entire numerical control tool shaft movement and related electric control.PC is based on described in the present embodiment
The bus marco board of digital control system is with high-performance, at low cost, standardization level is high, reliability is high, software and hardware resources enrich
And it is easy to the advantages such as information integration.
Description of the drawings
Fig. 1 is the functional block diagram of the bus marco board based on PC digital control systems described in the utility model embodiment；
Fig. 2 is the functional block diagram of bus marco board described in the utility model embodiment；
Fig. 3 is the circuit reference schematic diagram of the utility model embodiment ID signals control；
Fig. 4 is the circuit reference schematic diagram of level conversion unit Port A described in the utility model embodiment；
Fig. 5 is the circuit reference schematic diagram of level conversion unit Port C described in the utility model embodiment；
Fig. 6 is the circuit reference schematic diagram of level conversion unit Port B described in the utility model embodiment；
Fig. 7 is the circuit reference schematic diagram of pci bus interface described in the utility model embodiment.
Main appended drawing reference is described as follows：
| 100 | Bus marco board |
| 110 | FPGA programmable logic controller (PLC)s |
| 120 | Digital I/O card interfaces |
| 130 | Motor shaft card interface |
| 140 | Expanded function control module interface |
| 150 | Pci bus interface |
| 160 | Level conversion unit |
| 170 | Detection module |
| 180 | Power supply instruction and output module |
| 190 | Memory management module |
| 200 | PC digital control systems |
| 300 | Digital I/O Control cards |
| 400 | Motor shaft Control card |
| 500 | Expanded function control module |
Specific embodiment
For the ease of understanding the utility model, the utility model is more fully retouched below with reference to relevant drawings
It states.The preferred embodiment of the utility model is given in attached drawing.But the utility model can in many different forms come in fact
It is existing, however it is not limited to embodiment described herein.On the contrary, the purpose for providing these embodiments is the public affairs made to the utility model
Open the understanding more thorough and comprehensive of content.
Unless otherwise defined, all of technologies and scientific terms used here by the article is led with belonging to the technology of the utility model
The normally understood meaning of technical staff in domain is identical.It is only in the term used in the description of the utility model herein
The purpose of description specific embodiment, it is not intended that in limitation the utility model.
As shown in fig.1, for the bus marco board based on PC digital control systems a kind of described in the utility model embodiment
Functional block diagram, including：Bus marco board 100, PC digital control systems 200, number I/O Control cards 300, motor shaft Control card
400 and expanded function control module 500, the PC digital control systems 200 pass through pci bus and the bus marco board 100
Data communication control is realized in connection, and the number I/O Control cards 300, the motor shaft Control card 400 pass through circuit respectively
Form connect with the bus marco board 100, the bus marco board 100 passes through parallel bus (Parallel bus)
Its functional circuit is controlled after being communicated with the expanded function control module 500；PC digital control systems described in the present embodiment 200
For the control axis of entire bus marco board, for controlling entire numerical control tool shaft movement and the operation of related electric, have
Body is：The PC digital control systems 200 by number I/O Control cards 300 described in 100 drive control of bus marco board,
The motor shaft Control card 400 and the expanded function control module 500, it is achieved thereby that entire numerical control tool shaft movement
It is controlled with related electric.
Wherein, with reference to shown in Fig. 2, the bus marco board 100 includes FPGA (Field Programmable Gate
Array) programmable logic controller (PLC) 110, number I/O card interfaces 120, motor shaft card interface 130, expanded function control module connect
Mouth 140, PCI (Peripheral Component Interconnect) bus interface 150 and level conversion unit 160.
The PC digital control systems 200 are connected to the FPGA programmable logic controller (PLC)s by the pci bus interface 150
On 110, to realize the communication and control of data between the PC digital control systems 200 and the FPGA programmable logic controller (PLC)s 110
System；The number I/O Control cards 300 are connected to the FPGA Programmable logical controllers by the number I/O card interfaces 120
On device 110 in the data transmission of the FPGA programmable logic controller (PLC)s 110 to the number I/O Control cards 300, to realize
The control of basic digital quantity I/O；The motor shaft Control card 400 is connected to described by the motor shaft card interface 130
On FPGA programmable logic controller (PLC)s 110, the data transmission of the FPGA programmable logic controller (PLC)s 110 to the motor shaft control
On making sheet card 400, to realize the control of basic motor shaft；The expanded function control module 500 passes through the level conversion list
Member 160 and the expanded function control module interface 140 are connected on the FPGA programmable logic controller (PLC)s 110, described
In the data transmission of FPGA programmable logic controller (PLC)s 110 to the expanded function control module 500, to realize the extension work(
The control of each expanded function on energy control module 500 controls in the present embodiment the expanded function to include extension motor shaft control
System, expansion variable I/O controls and expanded mode analog quantity I/O controls.
In the embodiment of the utility model, the bus marco board 100 further includes detection module 170, power supply instruction
And output module 180 and memory management module 190, the detection module 170, the power supply instruction and output module 180, institute
Memory management module 190 is stated to connect with the FPGA programmable logic controller (PLC)s 110 by the form of circuit respectively.
The detection module 170 is used for progress such as voltage, temperature and the battery capacities of the bus marco board 100
Detection is monitored the bus marco board 100 with realizing；Specifically：Partial pressure and reference after being sampled by supply voltage
Voltage is compared monitoring, and partial pressure is compared monitoring with reference voltage after being sampled by temperature sensor, passes through cell voltage
Partial pressure is compared monitoring with reference voltage after sampling；The power supply instruction and output module 180 are used for the bus marco
Whether the working condition of itself of board 100 carries out state instruction output extremely, and drives the work of relay switch control forceful electric power；
The memory management module 190 is made of basic CMOS RAM (random access memory) the chips LY62L5128SL of two panels, is used
In the memory headroom for managing the bus marco board 100；In addition, it is additionally provided with regulated power supply on the bus marco board 100
Circuit, the voltage-stabilized power supply circuit include：The battery being connect with the memory management module 190 and the pci bus interface
The +/- 12V power supplys and 5V power supplys of 150 connections；Specifically, 3.3V power supplys are in series on the 5V power supplys, and in 3.3V electricity
One 2.5V power supply of series connection on source, the voltage-stabilized power supply circuit are used to ensure voltage when the bus marco board 100 works
Stability.
The FPGA programmable logic controller (PLC)s 110 are editable device, are loaded and compiled by internally static storage cell
Number of passes is according to realizing some logic functions, the logic function that FPGA programmable logic controller (PLC)s described in the present embodiment 110 is embedded in
It is corresponding with the interface or module set on the bus marco board 100, specifically, including：Pci bus protocol communication is patrolled
It collects, number I/O control logics, motor shaft control logic, extended function module communication control logic, voltage/temperature/battery capacity
Detect logic, power supply instruction and output logic, memory management logic.
In the present embodiment, when the FPGA programmable logic controller (PLC)s 110 insertion expanded function control module interface
ID signals will be generated after communication control logic, and are controlled, then pass through the level conversion list by the ID signal generating circuits
Member 160 carry out after level conversion by the expanded function control module interface 140 and the expanded function control module 500 into
Row Data Transmission Controlling.
Specifically, circuit as shown in Figure 3, which is used to be controlled according to ID signal generating circuits, including resistance R106,
Resistance R107, resistance R108, diode D14, field-effect tube Q1 and+12V power supplys；Wherein, the pin 2 of resistance R106 is connected to
It is connect behind one end of diode D14 with the pin of field-effect tube Q1 2, the other end ground connection of diode D14, field-effect tube Q1's draws
Foot 3 is connect after being connect with the pin 1 of resistance R107 with+12V power supplys, and the pin 1 of field-effect tube Q1 connects with the pin 2 of resistance R107
After connecing, it is connected on the pin 1 of resistance R108；The pin 1 of the present embodiment resistance R106 is signal input part, and resistance R108's draws
Foot 2 is signal output end, specifically, the ID signals are controlled by foregoing circuit by resistance after the pin 1 of resistance R106 inputs
The pin 2 of R108 exports, so as to which generation circuit controls, wherein, field-effect tube Q1 is switched field effect pipe, is risen in foregoing circuit
To opening energy and the effect of shutdown.
In the embodiment of the utility model, the level conversion unit 160 includes single-ended signal voltage being converted to difference
The circuit of sub-signal voltage and the circuit that differential signal voltage is converted to single-ended signal voltage；Single-ended letter in the present embodiment
Number voltage is represented using the voltage on single conductor；And differential signal voltage is utilized in the voltage difference between two conductors.
Identification small-signal is readily able to, to external electromagnetic interference (EMI) hyperimmunization and accurate using differential signal in the present embodiment
Ground handles bipolar signal.
In the present embodiment, to improve the transmission range and stability of single-ended signal voltage, as shown in figure 4, can will be single-ended
Signal voltage is (such as：Transistor-Transistor Logic level) differential signal voltage is converted to (such as by the U32/U34 of integrated chip 26LS31：RS422 electricity
It is flat), implementation method is as follows：
By single-ended signal voltage from PA [7:0] port input, by chip U32/U33 be converted into differential signal voltage and by
+DIFFA[7:0] port and-DIFFA [7:0] port exports；Specifically, PA0~PA3 ports are connected respectively U32 cores
The pin 1 of piece, 7,9,15, PA4~PA7 ports are connected respectively the pins 1,7,9,15 of U34 chips；In addition,+DIFFA0
~+DIFFA3 ports are connected respectively the pin 2,6,10,14 of U32 chips, and-DIFFA0~-DIFFA3 ports are right respectively
The pin 3,5,11,13 of U32 chips should be connected to ,+DIFFA4~+DIFFA7 ports are connected respectively drawing for U34 chips
Foot 2,6,10,14 ,-DIFFA4~-DIFFA7 ports are connected respectively the pin 3,5,11,13 of U34 chips.Wherein, PA0
~PA7 ports are signal input port, and+DIFFA0~+DIFFA7 ports and-DIFFA0~-DIFFA7 ports are signal
Output port.
It in some embodiments, can also be by single-ended signal voltage from PC [7 with reference to shown in Fig. 5:0] port inputs, and passes through core
Piece U33/U35 is converted into differential signal voltage and by+DIFFC [7:0] port and-DIFFC [7:0] port exports, realization side
Method with it is above-mentioned by single-ended signal voltage from PA [7:0] port inputs, and the side of differential signal voltage is converted by chip U32/U34
Method is similar, repeats no more in the present embodiment.
In the present embodiment, since the FPGA programmable logic controller (PLC)s 110 can only identify single-ended signal voltage, it is
This, as shown in fig. 6, can be by differential signal voltage (such as：RS422 level) it is converted to by the U36/U37 of integrated chip 26LS31
Single-ended signal voltage is (such as：Transistor-Transistor Logic level), implementation method is as follows：
By differential signal voltage from+DIFFB [7：0] port and-DIFFB [7：0] port inputs, and passes through chip U36/
U37 is converted into single-ended signal voltage and by PB [7:0] port exports；Specifically ,+DIFFB0~+DIFFB3 ports correspond to respectively
The pin 2,6,10,14 of U36 chips is connected to ,-DIFFB0~-DIFFB3 ports are connected respectively the pin of U36 chips
1st, 7,9,15 ,+DIFFB4~+DIFFB7 ports are connected respectively the pin 2,6,10,14 of U37 chips, and-DIFFB4~-
DIFFB7 ports are connected respectively the pin 1,7,9,15 of U37 chips；In addition, PB0~PB3 ports are connected respectively
The pin 3 of U36 chips, 5,11,13, PB4~PB7 ports are connected respectively the pins 3,5,11,13 of U37 chips.Wherein,
PB0~PB7 ports are signal input port, and+DIFFB0~+DIFFB7 ports and-DIFFB0~-DIFFB7 ports are letter
Number output port；In addition, the resistance R98 that resistance value is 100, successively class are connected between+DIFFB0 ports and-DIFFB0 ports
Push away, connect one to one between+DIFFB1~+DIFFB7 ports and-DIFFB1~-DIFFB7 ports have resistance R100,
R101, R99, R102, R104, R105, R103, and the resistance value of resistance R100, R101, R99, R102, R104, R105, R103 with
The resistance value of resistance R98 is 100.
As the preferred embodiment of the present embodiment, the chip U32/U33/U34/U35/ of the use of level conversion unit 160
U36/U37 is the chip of same model, and Pin locations and function are also identical.
In the embodiment of the utility model, the pci bus interface 150 is total for a kind of time-multiplexed two-way response
Line, the data communication control being mainly used between transmission side and recipient, transmission initiator is the PC numbers in the present embodiment
200 recipient of control system is the bus marco board 100：With reference to shown in Fig. 7, concrete implementation method is as follows：
First, the PC digital control systems 200 are used as instruction, the bus marco board 100 using FRAME signals in diagram
DEVSEL lines in diagram are dragged down to ask to represent that response is transmitted；Wherein, it is illustrated that middle IRDY and TRDY represents the PC numerical controls respectively
System 200 and the bus marco board 100 are ready for.
Secondly, the data transmission of the pci bus interface 150 is as unit of frame, and transmission is by an address cycle every time
(Address Phase) and multiple data periods (Data Phase) form, specifically, AD0~AD31 is provided first in diagram
The first address of this transmission, followed by one or more 32 (4 bytes) wide data, the address of multiple data is passed automatically
Increase.
In address cycle, it is illustrated that the various combination of this four lines of middle CBE0~CBE3 is indicated will on the ADO~AD31
What type of operation is carried out, such as：CBE0~CBE3=0110 represents that memory is read, and CBE0~CBE3=0011 represents I/
O read-writes etc..In addition, in the data period, upper four bytes of CBE0~CBE3 corresponding As D0~AD31 enable.
In transmission process, only IRDY and TRDY effective, the PC digital control systems 200 and the bus marco plate simultaneously
Data transmission between card 100 could continue；Otherwise latent period is inserted into, for coordinating work between the equipment of friction speed
Make.
In some embodiments, traditional data transmission interface card can generally use I/O ports, storage space, interruption
And computer resources, the interface card such as DMA (Direct Memory Access, direct memory access) are kept away by changing wire jumper
Exempt from the resource contention between polylith card, and the pci bus interface that the present embodiment uses then has abandoned hardware jumper, is planned as a whole by software
Distribute resource, i.e. referred to as plug and play.And the function that the present embodiment is realization plug and play, the PCI defined by pci bus interface
Agreement also defines read-write to configuration space (such as other than can be to input/output space, storage space read-write：CBE0~CBE3
=1010,1011).So-called configuration space refers to the special function register of 256 bytes being mapped on every piece of interface card, and right
Resource needed for them carries out pool distribution, then allocation result is write back corresponding configuration space address, completes to automatically configure.
In the embodiment of the utility model, the PC digital control systems 200 are the control axis of entire bus marco board,
And pass through number I/O Control cards 300, the motor shaft Control card 400 described in 100 drive control of bus marco board
And the expanded function control module 500, it is achieved thereby that entire numerical control tool shaft movement and related electric control.This implementation
The example bus marco board based on PC digital control systems is with high-performance, at low cost, standardization level is high, reliability is high, soft
Rich hardware resource and it is easy to the advantages such as information integration.
Above-described embodiment is the preferable embodiment of the utility model, but the embodiment of the utility model is not by above-mentioned
The limitation of embodiment, the change made under other any Spirit Essences and principle without departing from the utility model are modified, are replaced
In generation, simplifies combination, should be equivalent substitute mode, is included within the scope of protection of the utility model.
Claims (8)
1. a kind of bus marco board based on PC digital control systems, which is characterized in that including：Bus marco board, PC numerical controls system
System, number I/O Control cards, motor shaft Control card and expanded function control module；
The PC digital control systems are connect by pci bus with the bus marco board realizes data communication control, the number
I/O Control cards, the motor shaft Control card are connect respectively by the form of circuit with the bus marco board, described total
Line traffic control board controls its functional circuit after being communicated by parallel bus with the expanded function control module；
The PC digital control systems control the number I/O Control cards, the motor shaft by the bus marco Labcard driver
Control card and the expanded function control module.
2. the bus marco board according to claim 1 based on PC digital control systems, it is characterised in that：The bus marco
Board includes FPGA programmable logic controller (PLC)s 110, number I/O card interfaces, motor shaft card interface, expanded function control module and connects
Mouth, pci bus interface and level conversion unit；
The PC digital control systems are connected to the FPGA programmable logic controller (PLC)s by the pci bus interface；
The number I/O Control cards are connected to the FPGA programmable logic controller (PLC)s 110 by the number I/O card interfaces
On, in the data transmission to the number I/O Control cards of the FPGA programmable logic controller (PLC)s；
The motor shaft Control card is connected to by the motor shaft card interface on the FPGA programmable logic controller (PLC)s, institute
It states in the data transmission to the motor shaft Control card of FPGA programmable logic controller (PLC)s；
The expanded function control module is connected to by the level conversion unit and the expanded function control module interface
On the FPGA programmable logic controller (PLC)s, the data transmission of the FPGA programmable logic controller (PLC)s to the expanded function control
On molding block.
3. the bus marco board according to claim 2 based on PC digital control systems, it is characterised in that：The bus marco
Board further includes detection module, power supply instruction and output module and memory management module；
The detection module, the power supply instruction and output module, the memory management module respectively by the form of circuit with
The FPGA programmable logic controller (PLC)s connection.
4. the bus marco board according to claim 3 based on PC digital control systems, which is characterized in that the bus marco
Voltage-stabilized power supply circuit is additionally provided on board, the voltage-stabilized power supply circuit includes：The battery that is connect with the memory management module, with
The +/- 12V power supplys and 5V power supplys of the pci bus interface connection；
3.3V power supplys are in series on the 5V power supplys, and a 2.5V power supply of connecting on the 3.3V power supplys.
5. the bus marco board according to claim 2 based on PC digital control systems, it is characterised in that：The FPGA can be compiled
ID signals are generated, and by the ID signals after the communication control logic of journey logic controller insertion expanded function control module interface
Generation circuit controls；
According to the ID signal generating circuits control circuit include resistance R106, resistance R107, resistance R108, diode D14,
Field-effect tube Q1 and+12V power supplys；Wherein, the pin 2 of resistance R106 is connected to behind one end of diode D14 and field-effect tube
The pin 2 of Q1 connects, the other end of diode D14 ground connection, after the pin 3 of field-effect tube Q1 is connect with the pin 1 of resistance R107
It is connect with+12V power supplys, after the pin 1 of field-effect tube Q1 is connect with the pin 2 of resistance R107, is connected to the pin 1 of resistance R108
On；The pin 1 of resistance R106 is signal input part, and the pin 2 of resistance R108 is signal output end.
6. the bus marco board according to claim 2 based on PC digital control systems, it is characterised in that：The level conversion
Unit includes single-ended signal voltage is converted to the circuit of differential signal voltage and differential signal voltage is converted to single-ended letter
The circuit of number voltage.
7. the bus marco board according to claim 6 based on PC digital control systems, which is characterized in that described by single-ended letter
The circuit that number voltage is converted to differential signal voltage includes：
PA0~PA3 ports be connected respectively U32 chips pin 1,7,9,15, PA4~PA7 ports are connected respectively
To the pin 1,7,9,15 of U34 chips；+ DIFFA0~+DIFFA3 ports be connected respectively U32 chips pin 2,6,
10th, 14 ,-DIFFA0~-DIFFA3 ports are connected respectively the pin 3,5,11,13 of U32 chips, and+DIFFA4~+
DIFFA7 ports are connected respectively the pin 2,6,10,14 of U34 chips, and-DIFFA4~-DIFFA7 ports are corresponding respectively to be connected
It is connected to the pin 3,5,11,13 of U34 chips；
Wherein, PA0~PA7 ports are signal input port ,+DIFFA0~+DIFFA7 ports and-DIFFAO~-DIFFA7
Port is signal output port.
8. the bus marco board according to claim 6 based on PC digital control systems, which is characterized in that described to believe difference
The circuit that number voltage is converted to single-ended signal voltage includes：
+ DIFFB0~+DIFFB3 ports are connected respectively the pin 2,6,10,14 of U36 chips ,-DIFFB0~-DIFFB3
Port is connected respectively the pin 1,7,9,15 of U36 chips, and+DIFFB4~+DIFFB7 ports are connected respectively U37
The pin 2,6,10,14 of chip ,-DIFFB4~-DIFFB7 ports are connected respectively the pin 1,7,9,15 of U37 chips；
In addition, PB0~PB3 ports be connected respectively U36 chips pin 3,5,11,13, PB4~PB7 ports are corresponding respectively connects
It is connected to the pin 3,5,11,13 of U37 chips；Wherein, PB0~PB7 ports be signal input port ,+DIFFB0~+DIFFB7 ends
Mouth and-DIFFB0~-DIFFB7 ports are signal output port；
In addition, the resistance R98 that resistance value is 100 is connected between+DIFFB0 ports and-DIFFB0 ports, and so on ,+
The resistance value that connects one to one between DIFFB1~+DIFFB7 ports and-DIFFB1~-DIFFB17 ports is 100 resistance
R100、R101、R99、R102、R104、R105、R103。
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108762128A (en) * | 2018-04-13 | 2018-11-06 | 大族激光科技产业集团股份有限公司 | Electrical control integrated system and device |
| CN111367238A (en) * | 2018-12-26 | 2020-07-03 | 大族激光科技产业集团股份有限公司 | Control system of numerical control laser cutting machine |
| CN116909201A (en) * | 2023-09-13 | 2023-10-20 | 南京德克威尔自动化有限公司 | Bus type IO acquisition and control expansion method, system and computer storage medium |
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2017
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108762128A (en) * | 2018-04-13 | 2018-11-06 | 大族激光科技产业集团股份有限公司 | Electrical control integrated system and device |
| CN111367238A (en) * | 2018-12-26 | 2020-07-03 | 大族激光科技产业集团股份有限公司 | Control system of numerical control laser cutting machine |
| CN116909201A (en) * | 2023-09-13 | 2023-10-20 | 南京德克威尔自动化有限公司 | Bus type IO acquisition and control expansion method, system and computer storage medium |
| CN116909201B (en) * | 2023-09-13 | 2023-11-24 | 南京德克威尔自动化有限公司 | Bus type IO acquisition and control expansion method, system and computer storage medium |
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