CN207489874U - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
- Publication number
- CN207489874U CN207489874U CN201721721026.0U CN201721721026U CN207489874U CN 207489874 U CN207489874 U CN 207489874U CN 201721721026 U CN201721721026 U CN 201721721026U CN 207489874 U CN207489874 U CN 207489874U
- Authority
- CN
- China
- Prior art keywords
- bit line
- contact
- active area
- area
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The utility model provides a kind of semiconductor devices, including active area, groove isolation construction, wordline and the bit line formed in Semiconductor substrate；Contact hole is equipped between bit line, source contact and spaced walls are equipped in contact hole；Expansion area is equipped between source contact and spaced walls so that the face area that source contact appears is more than the area that spaced walls surround, and forms storage node contacts.The utility model appears the contact area of end face by increasing source contact, maximizes storage node contacts and the bonding layer contact area of source contact, improves the electric conductivity of semiconductor devices.
Description
Technical field
The utility model is related to field of semiconductor manufacture, and in particular to a kind of semiconductor devices.
Background technology
Memory generally includes storage and is connected to the memory transistor of the memory element, the storage electricity
Container is used for storing the charge for representing storage information.Active area, drain region and gate structure are formed in the memory transistor.It is described
Gate structure is connected to wordline, for controlling the electric current flowing between the source region and drain region.The source region is used to form bit line
Contact zone, to be connected to bit line, the drain region is for forming storage node contacts area, to be connected to storage.Wherein,
When the storage node contacts area is connected to the storage, need to usually be formed in the storage node contacts area
Storage node contacts, to realize the electricity between storage node contacts area and the storage by the storage node contacts
Property connection.
As semiconductor contact manufacturing process becomes finer, and storage node contacts are formed on a semiconductor substrate,
So that the interval that design rule is compared before reducing between node becomes narrower, storage node contacts and storage node contacts area
Between can not come into full contact with, then cause contact interface metallic bond layer grow it is unstable, so as to generate larger contact resistance,
The performance of memory is had adverse effect on, when influencing serious, device cisco unity malfunction.
Utility model content
The utility model embodiment provides a kind of semiconductor devices at least to solve Yi Shang technical problem of the prior art.
In order to achieve the above objectives, the utility model embodiment provides a kind of semiconductor devices, including：
Semiconductor substrate, formed in the Semiconductor substrate active area, each active area of isolation groove isolation construction,
Multiple bit lines are formed in a plurality of wordline and the Semiconductor substrate；
Bit line isolation structure is formed in the Semiconductor substrate and covers the bit line；Wherein, shape on the active area
It into contact hole, is formed between the bit line isolation structure, and the contact hole bottom appears the source area of the active area；
Source contact is set to the active area on the source area except adjacent two wordline and positioned at the contact
Window bottom；
Spaced walls are formed in the bit line isolation structure on the side wall in the contact hole, in the spaced walls lower end
Extension gap is formed between face and the source contact, is formed as access opening between the adjacent spaced walls, between the extension
The access opening between gap and the spaced walls connects；
Storage node contacts are formed on the source contact, and the storage node contacts are formed according to being highly divided into
Filling perforation portion in the access opening and the extension bottom for being filled in the extension gap so that the extension bottom with it is described
The bonding area of source contact is not less than the sectional area that the filling perforation portion intercepts in the horizontal direction.
In an embodiment, the active area includes being formed in the semiconductor substrate a plurality of rodlike active
Area, the groove isolation construction is between the rodlike active area, the rodlike active area and the groove isolation construction edge
First direction is alternately arranged on the semiconductor substrate, and the wordline is buried in a second direction in the Semiconductor substrate,
And the first direction and the second direction intersect, and the bit line is arranged on the Semiconductor substrate table along third direction
Face, and the third direction is vertical with the second direction.
In an embodiment, further include：
Bit line contact is set to the active area in the drain area between adjacent two wordline and positioned at the bit line
In the overlapping areas of the active area.
In an embodiment, the height in the extension gap is not more than 15nm.
In an embodiment, the bit line isolation structure includes：
First separation layer is formed on the bit line；And
Second separation layer is formed in the bit line side wall, the first separation layer side wall and top；
Second separation layer includes：
Inner insulation layer is set to the bit line and the first separation layer side；
Oxide layer is set on the inner insulation layer side；And
Outer insulation is set to the oxide layer side.
In an embodiment, the storage node contacts include：
Metallic bond layer is arranged on the end face that the source contact appears；
First conductive layer is arranged in the metallic bond layer, and is integrally formed at the spaced walls, the extension gap
And on the bit line isolation structure；And
Second conductive layer is arranged on first conductive layer, to fill the contact hole, and second conductive layer
The top of the bit line isolation structure is covered in wrap up first conductive layer.
In an embodiment, the storage node contacts also have higher than the bit line isolation structure and one extension
Capacitance contact portion, the side in the capacitance contact portion extended partially on the bit line isolation structure, the capacitance contact portion
Opposite side defined by notch, bit line isolation structure described in the ablation of the notch part, so that the upper table in the capacitance contact portion
The composition surface central point of bottom is extended described in the central point relative depature of face.
The utility model embodiment due to using the technology described above, has the following advantages：The utility model by
It is formed before metallic bond layer on source contact, removing part source contact by isotropic etching method forms between extension
Gap, so that the face area of source contact is more than the access opening horizontal section area that spaced walls surround, so that being formed in source
Metallic bond layer on the end face of pole contact is stablized to be formed, and to form storage node contacts, makes storage node contacts and source contact
Between resistance will not increase suddenly, improve performance of semiconductor device.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one
Aspect, embodiment and the feature of step will be what is be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent the same or similar through the identical reference numeral of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to this practicality
Some novel disclosed embodiments, and should not be taken as the limitation to the scope of the utility model.
Fig. 1 is the memory that the method for manufacture storage node contacts in semiconductor devices in the utility model embodiment is formed
Overall structure diagrammatic cross-sectional view.
Fig. 2 is the flow chart for manufacturing storage node contacts method in the utility model embodiment in semiconductor devices.
Fig. 3 is that manufacture storage node contacts method forms bit line and first in semiconductor devices in the utility model embodiment
The diagrammatic cross-sectional view of separation layer.
Fig. 4 is that manufacture storage node contacts method forms the second separation layer in semiconductor devices in the utility model embodiment
Diagrammatic cross-sectional view.
Fig. 5 is that manufacture storage node contacts method forms source contact in semiconductor devices in the utility model embodiment
Diagrammatic cross-sectional view.
Fig. 6 is that manufacture storage node contacts method forms spaced walls section view in semiconductor devices in the utility model embodiment
Schematic diagram.
Fig. 7 is after manufacturing storage node contacts method formation extension gap in the utility model embodiment in semiconductor devices
Diagrammatic cross-sectional view.
Fig. 8 is that manufacture storage node contacts method forms capacitance contact portion in semiconductor devices in the utility model embodiment
Diagrammatic cross-sectional view.
Fig. 9 is the overall structure sectional view of semiconductor devices in the utility model embodiment.
Drawing reference numeral explanation：
100 Semiconductor substrates,
101 active areas,
102 groove isolation constructions,
110 wordline,
111 bit line contacts,
120 bit lines,
130 first separation layers,
140 second separation layers,
141 inner insulation layers,
142 oxide layers,
143 outer insulations,
150 contact holes,
160 source contacts,
170 spaced walls,
180 access openings,
190 extension gaps；
200 storage node contacts,
201 filling perforation portions,
202 extension bottoms,
203 capacitance contact portions,
210 metallic bond layers,
220 first conductive layers,
230 second conductive layers,
240 notches.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present utility model, described reality can be changed by various different modes
Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be appreciated that term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", " on ", " under ", "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ",
The orientation or position relationship of the instructions such as " clockwise ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " are based on shown in the drawings
Orientation or position relationship are for only for ease of description the utility model and simplify description rather than instruction or imply signified dress
It puts or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that the utility model
Limitation.
In addition, term " first ", " second " are only used for description purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature." multiple " are meant that two or two in the description of the present invention,
More than, unless otherwise specifically defined.
In the utility model unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " Gu
It is fixed " etc. terms should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected or integral；Can be
Mechanical connection or electrical connection, can also be communication；It can be directly connected, the indirect phase of intermediary can also be passed through
Even, can be the interaction relationship of connection inside two elements or two elements.For those of ordinary skill in the art
For, concrete meaning of the above-mentioned term in the utility model can be understood as the case may be.
In the utility model unless specifically defined or limited otherwise, fisrt feature second feature it " on " or it
" under " can be in direct contact including the first and second features, it is not to be in direct contact but lead to that can also include the first and second features
Cross the other characterisation contact between them.Moreover, fisrt feature second feature " on ", " side " and " above " including first
Feature is right over second feature and oblique upper or is merely representative of fisrt feature level height higher than second feature.Fisrt feature
Second feature " under ", " lower section " and " below " including fisrt feature right over second feature and oblique upper or only table
Show that fisrt feature level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the utility model.
In order to simplify the disclosure of the utility model, hereinafter the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.In addition, various specific techniques and the example of material that the utility model provides, but this
Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.
Embodiment 1
As shown in Figures 1 to 8, the method that storage node contacts are manufactured in a kind of semiconductor devices of the present embodiment is formed such as
The method of semiconductor devices shown in FIG. 1 specifically includes step as shown in Figure 2 and includes：
Step S01：As shown in figure 3, providing semi-conductive substrate 100, active area is formed in the Semiconductor substrate 100
101st, the groove isolation construction 102 of each active area 101, a plurality of wordline 110 and shape on the semiconductor substrate is isolated
Into multiple bit lines 120；As shown in figure 4, formed bit line isolation structure in the Semiconductor substrate 100 to cover the bit line
120。
Step S02：As shown in figure 5, the active area 101 between the bit line isolation structure is etched to having described in exposing
The source area of source region 101, to form contact hole 150；Source contact 160 is formed in the active area 101 in the adjacent wordline
On source area except 110, and the source contact 160 is formed in 150 bottom of contact hole.
Step S03：As shown in fig. 6, formed spaced walls 170 in the bit line isolation structure in the contact hole 150
On side wall, as shown in fig. 7, forming extension gap 190, phase between 170 lower face of spaced walls and the source contact 160
Access opening 180 is formed between the adjacent spaced walls 170, the extension gap 190 is connected with the access opening 180.
Step S04：As shown in figure 8, storage node contacts 200 are formed on the source contact 160, the memory node
Contact 200 includes filling the extension gap 190 extension bottom 202 formed and the filling perforation being formed in the access opening 180
Portion 201 is to form semiconductor devices as shown in Figure 1；Wherein, the extension bottom 202 and the engagement of the source contact 160
Area is not less than the sectional area that the filling perforation portion 201 intercepts in the horizontal direction.
Based on embodiment 1, in one embodiment, a plurality of rodlike active area is formed in the Semiconductor substrate 100,
The groove isolation construction 102 is formed between the rodlike active area, the rodlike active area and the groove isolation construction
102 are arranged alternately in along the first direction in the Semiconductor substrate 100, and the wordline 110 is buried in described half in a second direction
In conductor substrate 100, and the first direction and the second direction intersect, and the bit line 120 is formed in along third direction
100 surface of Semiconductor substrate, and the third direction is vertical with the second direction.
Based on embodiment 1, in one embodiment, further include：
Bit line contact 111 is formed in the active area 101 on drain region between the adjacent wordline 110, and institute
Bit line contact 111 is located in the overlapping areas of the bit line 120 and the active area 101.
Based on embodiment 1, in one embodiment, form the extension gap 190 and include：
By isotropic etching mode, source contact 160 described in etched portions, to form the extension gap 190；
Wherein, the isotropic etching includes isotropism wet etching and isotropism dry etching.
Based on embodiment 1, in one embodiment, form the extension gap 190 and include：
By isotropic etching mode, source contact 160 described in etched portions, to form the extension gap 190；
Wherein, the isotropic etching includes isotropism wet etching.
Based on embodiment 1, in one embodiment, form the extension gap 190 and include：
By isotropic etching mode, source contact 160 described in etched portions, to form the extension gap 190；
Wherein, the isotropic etching includes isotropism dry etching.
Based on embodiment 1, in one embodiment, the etch amount of the isotropic etching is not more than 15nm.
Based on embodiment 1, in one embodiment, form bit line isolation structure and include：
The first separation layer 130 is formed on the bit line 120；And
The second separation layer 140 is formed in 120 side of bit line, 130 side of the first separation layer and top.
Based on embodiment 1, in one embodiment, the formation of second separation layer 140 includes：
Inner insulation layer 141 is formed, the inner insulation layer 141 is covered in first separation layer 130 and the bit line
120 side；
Oxide layer 142 is formed, the oxide layer 142 is covered in the side of the inner insulation layer 141；And
Form outer insulation 143, the outer insulation 143 is covered in the surface of the oxide layer 142 and described
The top of first separation layer 130.
Based on embodiment 1, in one embodiment, further included before forming the storage node contacts 200：
The part bit line isolation structure is removed, to manifest at the top of the bit line isolation structure.
The step of forming storage node contacts 200 includes：
It is formed on the end face that metallic bond layer 210 is manifested in the source contact 160；
The first conductive layer 220 is formed, first conductive layer 220 is formed in the metal by chemical vapor deposition manner
On bonding layer 210, and it is in that integral type is covered in the extension gap 190, the spaced walls 170, the bit line isolation structure
On surface；And
The second conductive layer 230 is formed, second conductive layer 230 is deposited on first conductive layer 220 to fill
Contact hole 150 is stated, and second conductive layer 230 covers at the top of the bit line isolation structure to wrap up first conductive layer
220。
Based on embodiment 1, in one embodiment, the storage node contacts 200 further include higher than the bit line every
From structure and along the capacitance contact portion that 230 upper end of the second conductive layer integrally extends downwards, the side in the capacitance contact portion
It extends partially on the bit line isolation structure, the opposite side in the capacitance contact portion is defined by notch 240, the notch 240
Bit line isolation structure described in local ablation, so as to extend bottom described in the upper surface central point relative depature in the capacitance contact portion
202 composition surface central point.
The present embodiment passes through storage node contacts 200 in the manufacture of a semiconductor device and 160 contact interface of source contact
When, by the way that 150 inside points source contact 160 of contact hole is removed, with increase source contact 160 and storage node contacts 200 it
Between contact interfacial area, make metallic bond layer 210 on source contact 160 stablize formed, due to increase contact area reduce source
Resistance between pole contact 160 and storage node contacts 200, makes the resistance of storage node contacts 200 will not increase suddenly, Jin Erti
The high performance of semiconductor devices.
Embodiment 2
The method that storage node contacts are manufactured in a kind of semiconductor devices of the present embodiment, including：
As shown in figure 3, providing semi-conductive substrate 100, a plurality of rodlike active area is formed in the Semiconductor substrate 100
101st, the groove isolation construction 102 of each rodlike active area 101, a plurality of wordline 110 is isolated and in the Semiconductor substrate 100
Upper formation multiple bit lines 120；The groove isolation construction 102 is formed between rodlike active area 101, rodlike active area 101 with
The groove isolation construction 102 is arranged alternately in along the first direction in the Semiconductor substrate 100, the wordline 110 along second
Direction is buried in the Semiconductor substrate 100, and the first direction and the second direction intersect, the bit line 120
100 surface of Semiconductor substrate is formed in, and the third direction is vertical with the second direction along third direction；
Bit line contact 111 is formed in active area 101 on drain region between the adjacent wordline 110, and institute's rheme
Line contact 111 is located in the overlapping areas of the bit line 120 and active area 101；And
Bit line isolation structure is formed on the bit line 120.
Bit line isolation structure includes the first separation layer 130 being formed on bit line 120；And
As shown in figure 4, the second isolation formed at 120 side of bit line, 130 side of the first separation layer and top
Layer 140；
The formation of second separation layer 140 includes：
Inner insulation layer 141 is formed, the inner insulation layer 141 is covered in first separation layer 130 and the bit line
120 side；
Oxide layer 142 is formed, the oxide layer 142 is covered in the side of the inner insulation layer 141；And
Form outer insulation 143, the outer insulation 143 is covered in the surface of the oxide layer 142 and described
The top of first separation layer 130, and the outer insulation 142 is partially covered on active area 101；
As shown in figure 5, active area 101 between the bit line isolation structure is etched to the source area for exposing active area 101,
To form contact hole 150；And
Source contact 160 is formed in active area 101 on the source area except the adjacent wordline 110, and the source
Pole contact 160 is formed in 150 bottom of contact hole；
As shown in fig. 6, spaced walls 170 are formed on the side wall of the bit line isolation structure in the contact hole 150, such as
Shown in Fig. 7, pass through isotropic etching mode, etching portion between 170 lower face of spaced walls and the source contact 160
Divide the source contact 160, to form the extension gap 190；
Wherein, the isotropic etching includes isotropism wet etching and/or isotropism dry etching, described respectively to same
Property etching etch amount be not more than 15nm.
Access opening 180 is formed between the adjacent spaced walls 170, the extension gap 190 connects with the access opening 180
It is logical；
Part second separation layer 140 is removed, to manifest the top of first separation layer 130；
As shown in figure 8, it is formed on the end face that metallic bond layer 210 is manifested in the source contact 160；First is formed to lead
Electric layer 220, first conductive layer 220 are formed in by chemical vapor deposition manner in the metallic bond layer 210, and in one
Body formula be covered in it is described extension gap 190, the spaced walls 170, first separation layer, 130 and second separation layer 140 table
On face；And the second conductive layer 230 is formed, second conductive layer 230 is deposited on first conductive layer 220 with described in filling
Contact hole 150, and second conductive layer 230 covers 130 top of the first separation layer to wrap up first conductive layer
220, to form storage node contacts 200, the storage node contacts 200 include filling the expansion that the extension gap 190 is formed
Exhibition bottom 202 and the filling perforation portion 201 being formed in the access opening 180, the storage node contacts 200 are further included higher than described
First separation layer 130 and the capacitance contact portion integrally extended downwards along 230 upper end of the second conductive layer, the capacitance contact portion
Side extend partially on first separation layer, the opposite side in the capacitance contact portion is defined by notch 240, the notch
First separation layer 130 and second separation layer 140 described in 240 local ablations, so that in the upper surface in the capacitance contact portion
The composition surface central point of bottom 202 is extended described in heart point relative depature, to form semiconductor devices as shown in Figure 1；Wherein, institute
It states extension bottom 202 and the bonding area of the source contact 160 is cut not less than what the filling perforation portion 201 intercepted in the horizontal direction
Area.
The present embodiment passes through storage node contacts 200 in the manufacture of a semiconductor device and contact circle of source contact 160
During face, by the way that 150 inside points source contact 160 of contact hole is removed, to increase source contact 160 and storage node contacts 200
Between contact interface area, make metallic bond layer 210 on source contact 160 stablize formed, due to increase contact area reduce
Resistance between source contact 160 and storage node contacts 200, makes the resistance of storage node contacts 200 will not increase suddenly, and then
Improve the performance of semiconductor devices.
Embodiment 3
A kind of semiconductor devices of the present embodiment, including：
Semiconductor substrate 100 forms active area 101, isolation each active area 101 in the Semiconductor substrate 100
Multiple bit lines 120 are formed in groove isolation construction 102, a plurality of wordline 110 and the Semiconductor substrate 100；
Bit line isolation structure is formed in the Semiconductor substrate 100 and covers the bit line 120；Wherein, it is described active
Contact hole 150 is formed in area 101, is formed between the bit line isolation structure, and 150 bottom of the contact hole appears described
The source area of active area 101；
Source contact 160 is set to the active area 101 on the source area except adjacent two wordline 110 and position
In 150 bottom of contact hole；
Spaced walls 170 are formed in the bit line isolation structure on the side wall in the contact hole 150, at the interval
Extension gap 190 is formed between 170 lower face of wall and the source contact 160, is formed as between the adjacent spaced walls 170
Access opening 180, the extension gap 190 are connected with the access opening 180 between the spaced walls 170；
Storage node contacts 200 are formed on the source contact 160, and the storage node contacts 200 are according to height point
For the filling perforation portion 201 being formed in the access opening 180 and it is filled in the extension bottom 202 for extending gap 190 so that
The extension bottom 202 intercepts in the horizontal direction in the bonding area with the source contact 160 not less than the filling perforation portion 201
Sectional area.
The extension gap 190 is used to expand the end face appeared of the source contact 160, so that the memory node
It is maximized when contact 200 is formed with the contact area of the source contact 160, ensures the storage node contacts 200 and source electrode
Resistance between contact 160 will not increase suddenly.
Based on embodiment 3, in one embodiment, the active area 101 includes being formed in the semiconductor substrate
A plurality of rodlike active area, the groove isolation construction 102 is between the rodlike active area, the rodlike active area and institute
It states groove isolation construction 102 to be arranged alternately in along the first direction in the Semiconductor substrate 100, the wordline 110 is along second party
To being buried in the Semiconductor substrate 100, and the first direction and the second direction intersect, 120 edge of bit line
Third direction is arranged on 120 surface of Semiconductor substrate, and the third direction is vertical with the second direction.
Based on embodiment 3, in one embodiment, further include：
Bit line contact 111 is set to the active area 101 in the drain area between adjacent two wordline 110 and position
In the overlapping areas of the bit line 120 and the active area 101.
Based on embodiment 3, in one embodiment, the height in the extension gap 190 is not more than 15nm.
Based on embodiment 3, in one embodiment, the bit line isolation structure includes：
First separation layer 130 is formed on the bit line 120；And
Second separation layer 140 is formed in 120 side wall of bit line, 130 side wall of the first separation layer and top；
Second separation layer 140 includes：
Inner insulation layer 141 is set to the bit line 120 and 130 side of the first separation layer；
Oxide layer 142 is set on 141 side of inner insulation layer；And
Outer insulation 143 is set to 142 side of oxide layer.
Based on embodiment 3, in one embodiment, the storage node contacts 200 include：
Metallic bond layer 210 is arranged on the end face that the source contact 160 appears；
First conductive layer 220 is arranged in the metallic bond layer 210, and is integrally formed at the spaced walls 170, institute
It states on extension gap 190 and the bit line isolation structure；And
Second conductive layer 230 is arranged on first conductive layer 220, to fill the contact hole 150, and it is described
Second conductive layer 230 is covered in the top of the bit line isolation structure to wrap up first conductive layer 220.
Based on embodiment 3, in one embodiment, the storage node contacts 200 also have higher than the bit line every
The capacitance contact portion extended from structure and integrally, the side in the capacitance contact portion extend partially into the bit line isolation structure
On, the opposite side in the capacitance contact portion is defined by notch 240, bit line isolation structure described in the local ablation of notch 240, with
Make the composition surface central point of extension bottom 202 described in the upper surface central point relative depature in the capacitance contact portion.
Based on embodiment 3, in one embodiment, the bit line isolation structure includes but does not limit to silicon nitride, described
Bit line contact 111 and the source contact 160 include but do not limit to polysilicon doping, and the metallic bond layer 210 is included through cobalt
Annealing forms cobalt SiClx, and first conductive layer 220 includes but do not limit to titanium nitride, and second conductive layer 230 is included but not
Limit to tungsten.
In the present embodiment in contact of semiconductor device window 150 in source contact 160 and contact hole 150 between spaced walls 170
Equipped with interval, so as to the face area increase for appearing the source contact 160, storage node contacts 200 are touched with the source electrode
Composition surface area increase between point 160 makes metal faying face 210 form stabilization, reduces storage node contacts 200 and the source
Resistance between pole contact 160, makes the resistance of storage node contacts 200 will not increase suddenly, ensure that the steady of semiconductor devices
It is fixed, improve the performance of semiconductor devices.
The above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to
In this, in the technical scope that any one skilled in the art discloses in the utility model, it is each that it can be readily occurred in
Kind change or replacement, these should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model
It should be based on the protection scope of the described claims.
Claims (7)
1. a kind of semiconductor devices, which is characterized in that including：
Semiconductor substrate forms the groove isolation construction, a plurality of of active area, each active area of isolation in the Semiconductor substrate
Multiple bit lines are formed in wordline and the Semiconductor substrate；
Bit line isolation structure is formed in the Semiconductor substrate and covers the bit line；Wherein, it is formed and connect on the active area
Window is touched, is formed between the bit line isolation structure, and the contact hole bottom appears the source area of the active area；
Source contact is set to the active area on the source area except adjacent two wordline and positioned at the contact hole bottom
Portion；
Spaced walls are formed in the bit line isolation structure on the side wall in the contact hole, the spaced walls lower face with
Extension gap is formed between the source contact, is formed as access opening between the adjacent spaced walls, the extension gap with
Access opening connection between the spaced walls；
Storage node contacts are formed on the source contact, the storage node contacts according to be highly divided into be formed in it is described
Filling perforation portion in access opening and the extension bottom for being filled in the extension gap so that the extension bottom with the source electrode
The bonding area of contact is not less than the sectional area that the filling perforation portion intercepts in the horizontal direction.
2. semiconductor devices as described in claim 1, which is characterized in that the active area is included in the semiconductor substrate
Formed a plurality of rodlike active area, the groove isolation construction positioned at the rodlike active area between, the rodlike active area and
The groove isolation construction is alternately arranged on the semiconductor substrate along the first direction, and the wordline is buried in a second direction
In the Semiconductor substrate, and the first direction and the second direction intersect, and the bit line is arranged on along third direction
The semiconductor substrate surface, and the third direction is vertical with the second direction.
3. semiconductor devices as described in claim 1, which is characterized in that further include：
Bit line contact is set to the active area in the drain area between adjacent two wordline and positioned at the bit line and institute
In the overlapping areas for stating active area.
4. semiconductor devices as described in claim 1, which is characterized in that the height in the extension gap is not more than 15nm.
5. semiconductor devices as described in claim 1, which is characterized in that the bit line isolation structure includes：
First separation layer is formed on the bit line；And
Second separation layer is formed in the bit line side wall, the first separation layer side wall and top；
Second separation layer includes：
Inner insulation layer is set to the bit line and the first separation layer side；
Oxide layer is set on the inner insulation layer side；And
Outer insulation is set to the oxide layer side.
6. semiconductor devices as described in claim 1, which is characterized in that the storage node contacts include：
Metallic bond layer is arranged on the end face that the source contact appears；
First conductive layer is arranged in the metallic bond layer, and be integrally formed at the spaced walls, it is described extension gap and
On the bit line isolation structure；And
Second conductive layer is arranged on first conductive layer, and to fill the contact hole, and second conductive layer covers
At the top of the bit line isolation structure to wrap up first conductive layer.
7. semiconductor devices as described in claim 1, which is characterized in that the storage node contacts also have higher than institute's rheme
Line isolation structure and the capacitance contact portion integrally extended, the side in the capacitance contact portion extend partially into the bit line isolation junction
On structure, the opposite side in the capacitance contact portion is defined by notch, bit line isolation structure described in the ablation of the notch part, so that institute
State the composition surface central point that bottom is extended described in the upper surface central point relative depature in capacitance contact portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721721026.0U CN207489874U (en) | 2017-12-12 | 2017-12-12 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721721026.0U CN207489874U (en) | 2017-12-12 | 2017-12-12 | Semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207489874U true CN207489874U (en) | 2018-06-12 |
Family
ID=62458110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721721026.0U Active CN207489874U (en) | 2017-12-12 | 2017-12-12 | Semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207489874U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020151389A1 (en) * | 2019-07-22 | 2020-07-30 | 福建省晋华集成电路有限公司 | Memory |
-
2017
- 2017-12-12 CN CN201721721026.0U patent/CN207489874U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020151389A1 (en) * | 2019-07-22 | 2020-07-30 | 福建省晋华集成电路有限公司 | Memory |
| US11074965B2 (en) | 2019-07-22 | 2021-07-27 | Fujian Jinhua Integrated Circuit Co., Ltd. | Memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107910328A (en) | The method and semiconductor devices of storage node contacts are manufactured in semiconductor devices | |
| US10008579B2 (en) | MOSFET with integrated schottky diode | |
| CN106992156B (en) | Memory array and its manufacturing method | |
| TWI358821B (en) | Transistor, memory cell array and method of manufa | |
| CN108155152B (en) | Conductor structure, array of capacitors structure and preparation method | |
| CN107910327A (en) | Array of capacitors structure and its manufacture method | |
| CN108206208A (en) | Semiconductor devices and its manufacturing method | |
| CN109075164A (en) | 3 dimension capacitor arrangements | |
| CN103227210B (en) | Decoupling FINFET capacitor | |
| CN110506333A (en) | Integrated circuitry construction and the method that vertically extending conductor is transversely formed between a pair of of structure | |
| CN109478552A (en) | Semiconductor device and its manufacturing method | |
| CN107611133A (en) | Memory and forming method thereof, semiconductor devices | |
| CN108231738A (en) | Semiconductor device structure and its manufacturing method | |
| CN107482012B (en) | Three-dimensional storage and preparation method thereof | |
| CN110491878A (en) | Semiconductor storage | |
| CN207489874U (en) | Semiconductor devices | |
| CN107665859A (en) | Semiconductor devices and its manufacture method including being electrically isolated pattern | |
| JP2015146399A (en) | Semiconductor device and semiconductor device manufacturing method | |
| CN208225880U (en) | The word line structure and memory transistor of memory transistor | |
| CN114078773A (en) | Capacitor structure, manufacturing method thereof and memory | |
| CN208738216U (en) | A kind of semiconductor structure | |
| CN207398140U (en) | Array of capacitors structure | |
| CN208111443U (en) | Semiconductor memory | |
| CN208142178U (en) | Semiconductor memory cell | |
| KR20140141299A (en) | Vertical channel semiconductor device and method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180927 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |