CN207424861U - The circuit that a kind of receiving end signal duty cycle adaptively adjusts - Google Patents

Abstract

The utility model is related to the circuits that a kind of receiving end signal duty cycle adaptively adjusts.In one embodiment, which includes：Analog level comparison circuit, pretreatment circuit, the first channel selector, alternate path switch, decoding circuit, parameter extraction estimating circuit, error generation circuit, filtering feedback circuit and D/A converting circuit.Analog level comparison circuit receives useful signal, generates duty cycle signals according to datum.Pretreatment circuit pre-processes duty cycle signals；When first channel selector turns on, parameter extraction estimating circuit obtains duty cycle information from duty cycle signals, generates duty cycle deviations；Error generation circuit handles duty cycle deviations, generates error signal；Filtering feedback circuit and D/A converting circuit are converted into analog voltage signal after error signal is filtered, and are connected to analog level comparison circuit, as its datum；During alternate path switch conduction, decoding circuit is decoded duty cycle signals.

Description

The circuit that a kind of receiving end signal duty cycle adaptively adjusts

Technical field

The circuit that the utility model is related to adaptively adjust adaptively is adjusted more particularly, to a kind of receiving end signal duty cycle Whole circuit.

Background technology

General-purpose serial bus USB interface design initial stage, be with data transmission and exchange as the main purpose, subsidiary confession Electric energy power is extremely limited.However as electronic technology development, the role of USB is also varied widely, and provides electric energy interface Using having had increased to the status of equal importance with data transmission.Such as handheld device, intelligent wearable device are portable to set Standby, tablet computer etc. is all to obtain electric energy by USB interface mostly.

USB has become a standard interface of various electronic equipments at present, and the power supply capacity of interface is also from 1.0 versions 5V@500mA promote 5V@1.5A to 2.0 versions, the power reguirements of many electronic products can be met.But still there are many compared with Powerful electronic equipment, such as laptop, television set, display screen etc., output power often require that tens watts or More than, the enough electric energy for maintaining its work can not be obtained by current USB interface.

The USB PD of newest issue --- Power Delivery power transmission protocols are to be based on 3.1 versions of USB, i.e., The power transmission new concept that USB type-C ports propose promotes the power supply capacity of USB interface to a new height. Beneficial to the high power characteristics of Type-C interfaces, USB can realize the up to quick charge of 100W and be supervised for laptop, large screen The electrical equipment of the biggers such as visual organ, panel TV set provides electric energy.In addition USB Type-C interfaces are popularized to substitute in electronic equipment Power supply interface, may be such that the integrated level higher of electronic product, cost is lower, while also has shared various supplying adapters and defeated Electric wire cable reduces the wasting of resources.Multiple voltage electric current configuration is supported in USB PD agreements at present, most I 50mV or 10mA make For a step units, maximum can support the power output of 100W (20V/5A).

In USB Type-C interfaces, USB PD communications are defined using a CC passage by USB PD power supplies specification.It is adopted With half-duplex operation mechanism, two-phase label coding Bi-phase Mark Coding are used --- BMC is transferred through 4B/5B codings Binary data, the method has been used as standard to issue, simple and flexible can simplify the design of receiver, at present just progressively To being widely applied and promote.

BMC can be considered as a kind of Manchester Manchester codings.Manchester's code is by clock and data packet Containing in a stream, while transmission code information, clock sync signal is also transferred to other side together, in every coding extremely A rare saltus step, there is no DC component, therefore with self-synchronization and good interference free performance.Recipient utilizes bag Specific coding containing synchronizing signal extracts synchronizing signal to lock the clock pulse frequency of oneself from signal itself, reaches synchronous Purpose.But each symbol is modulated into two level, so message transmission rate only has the 1/2 of modulation rate.

In practical applications, since transmitting terminal quality is various, transmission medium is very different, and channel is different in size, signal by External interference is serious and bad environments, receiving terminal there may be problems such as larger direct current biasing and intersymbol interferences, these The BMC signals received can be affected greatly, cause wave distortion serious.Herein, be mainly summarized as follows it is several because Element：

1st, there are larger frequency departures for transmitting terminal and receiving terminal.Because two-part clock source is different, this is often objective Existing for sight, because transmitting terminal and receiving terminal be not often in same system.Frequency departure can cause to send and receive for The discrimination standard appearance of benchmark UI is inconsistent, so as to cause error code.

2nd, there are larger local DC deviations when receiving terminal is converted from analog quantity to digital quantity.BMC codings are not deposited in itself In DC component, if but the direct current biasing of receiving terminal be added on the BMC waveforms received, these possible direct current biasings often compare The noise of front end receiver circuit will also greatly, on the one hand so that signal-to-noise ratio is deteriorated, on the other hand so that the BMC signals conversion received Waveform duty cycle serious distortion after into digital quantity, causes BMC codes that can not decode.

3rd, level conversion rate is inconsistent, i.e., signal switches from low level to high level, with being cut from high level to low level The rate changed is inconsistent or does not match that, this can also cause BMC waveform duty cycles that distortion occurs indirectly.Modern operational amplifier has The Push-pull-output stage of some modes, many is asymmetric, and the conversion rate of a direction has having than other directions The tendency of bigger；

The non-ideal factors such as the 4th, clock jitter, the additive noise of channel, intersymbol interference will also result in BMC waveform duty cycles hair Raw distortion.

In engineering practice, in order to solve interchannel noise or interference problem, generally use FIR filter is carried out outside useful signal Garbage signal filtering, this to clock jitter, channel additive noise, intersymbol interference etc. have stochastic behaviour non-ideal factor make Into wave distortion it is largely effective, but for the intrinsic direct current biasing of such as analog level comparator, system, which sends and receives, deposits The wave distortion caused by frequency departure etc. is helpless.

Therefore, receiving circuit needs a BMC coding to differentiate the circuit with waveform adjust automatically, and adjustment is because above-mentioned possibility Intrinsic factor caused by BMC coding duty cycle wave distortion so that the BMC signal dutyfactors received are in certain decodable code In the range of, it can be achieved that receive appropriate judgement of the signal from analog quantity to digital quantity, complete BMC and be correctly decoded.Usual receiving circuit Property relationship when analog quantity to digital quantity is converted is encoded to the overall performance and communication bit error rates of receiver using BMC Physics layer decoder and waveform duty cycle characteristic are closely related.Therefore the premise that dutyfactor adjustment circuit is met the requirements in basic function Under, it is necessary to good performance could be obtained by the debugging of actual circuit.If this process cannot be adopted a correct attitude towards, design The receptivity of circuit can very poor or environmental suitability it is poor.

Utility model content

To achieve the above object, the utility model provides the circuit that a kind of receiving end signal duty cycle adaptively adjusts, Including：Analog level comparison circuit, the first channel selector SW-M, alternate path switch SW-N, decoding circuit, parameter extraction estimation Circuit, error generation circuit, filtering feedback circuit and D/A converting circuit.Analog level comparison circuit is used to receive signal, and By it compared with datum, duty cycle signals are generated.First channel selector SW-M and alternate path switch SW-N is all duty It is switched than signal transmission pathway；When duty cycle signals are lead code, the first channel selector SW-M is turned on, duty cycle signals and ginseng Number extraction estimating circuit is connected；Otherwise alternate path switch SW-N conductings, duty cycle signals are connected with decoding circuit.Decoding Circuit is used to be decoded duty cycle signals.Parameter extraction estimating circuit is believed for obtaining duty cycle from duty cycle signals Breath generates duty cycle deviations.Error generation circuit generates error signal for duty cycle deviations to be handled.Filtering feedback Circuit is used to error signal being converted to control errors amount, and control errors amount is output to D/A converting circuit.Digital-to-analogue conversion Circuit is used to, by control errors amount, be converted to analog signal from digital signal, the reference being output in analog level comparison circuit Level terminal.

Preferably, further include：Circuit is pre-processed, for being pre-processed to duty cycle signals.

Preferably, filtering feedback circuit includes：Feedback filter.Feedback filter is used to error signal filtering out high frequency division Amount forms control errors amount by linearly calculating.

Preferably, further include：Sequential control circuit.Sequential control circuit is adaptive for controlling and receiving end signal duty cycle The overall workflow of adjustment circuit.

Preferably, further include：Receive activity indicating circuit.Activity indicating circuit is received to be used for input signal It is detected, if detect the input signal of validity feature, notifies sequential control circuit, reception system enables, and receives Circuit is started to work.

Preferably, the duty cycle of the duty cycle signals of SW-N is switched by alternate path as 35% to 65%, permission it is inclined Difference is +/- 5%.

Preferably, pretreatment circuit pre-processes duty cycle signals, differentiates whether duty cycle signals are in centainly Spectral range simultaneously eliminates burr.

Preferably, duty cycle signals are the ratio of signal waveform high level width and entire bit period, value range For 0% to 100%.

Preferably, parameter extraction estimating circuit is the electricity that high level bit duty cycle information is obtained from duty cycle signals Road.

The utility model embodiment carries out in the targeting sequencing stage of USB PD message packages, by the waveform of serious distortion Duty cycle has carried out good adjustment and recovery, is mainly reflected in when analog level comparison circuit has larger direct current biasing or transmitting terminal When voltage conversioning rate is inconsistent, which can be very good to eliminate its influence, hence it is evident that improves waveform and loses Very, reliable sources of waveforms is outputed for subsequent decoding circuit.Simultaneously without additional prover time, without self-defined in advance Calibration form, it can be achieved that with USB PD agreement seamless connections.And according to specific receiving circuit characteristic, number is being received each time It is adaptively adjusted during according to bag, there is extensive adaptability.

Description of the drawings

The BMC oscillograms that Fig. 1 is the definition of BMC codings and receiving terminal recovers in the prior art；

Fig. 2 is the circuit structure that a kind of receiving end signal duty cycle that the utility model embodiment provides adaptively adjusts Figure；

Fig. 3 is the communication information bag schematic diagram provided according to the utility model one embodiment；

Fig. 4 a are a kind of waveform diagram of the extraction duty cycle error provided according to the utility model one embodiment；

Fig. 4 b are the utility model parameter extraction estimating circuit schematic diagram；

Fig. 5 is a kind of filtering feedback electrical block diagram；

Fig. 6 is a kind of method stream for adaptive adjustment circuit of receiving end signal duty cycle that the utility model embodiment provides Cheng Tu.

Specific embodiment

Below by drawings and examples, the technical solution of the utility model is described in further detail.

Exemplified by the utility model is with two-phase label coding (Bi-phase Mark Coding, BMC), but it is not limited to this reality With new protection domain.

As shown in Figure 1, the BMC oscillograms defined and receiving terminal recovers in the prior art for BMC codings.

In BMC coding definition, Bit-1 is defined as in each UI --- the starting of Unit Interval, once level Switching, and in the centre position of each UI, there is second of level switching, high level and low level form 50% duty cycle. Bit-0 is defined as only in the starting of each UI, once level switching.

When receiving terminal is when analog quantity to digital quantity is converted, since level conversion rate is inconsistent, and analog level compares Device results in reception and transformed BMC digital waveforms Severe distortion there are larger forward dc deviation.Such as Fig. 1 lower parts ripple Shape is clearly present two problems：The duty cycle distortion of Bit-1 is apparent, and A width is significantly less than B width；B sections of the low level of Bit-1 It is almost approached with C sections of width of high level of subsequent Bit-0.

The waveform of this distortion, which directly inputs, gives BMC decoding circuits, decoding circuit from the width of A and B relatively in, will be unable to Judge Bit-1, while also cannot be distinguished B sections is the low level of Bit-1 or the low level of Bit-0 on earth, BMC decodings fail, Communication can not be carried out effectively.

Fig. 2 is the circuit structure that a kind of receiving end signal duty cycle that the utility model embodiment provides adaptively adjusts Figure.

As shown in Fig. 2, circuit includes：Analog level comparison circuit, pretreatment circuit, the first channel selector SW-M, second Channel selector SW-N, decoding circuit, parameter extraction estimating circuit, error generation circuit, filtering feedback circuit and digital-to-analogue conversion electricity Road.

Analog level comparison circuit is for receiving useful signal and datum, by the signal of input and feedback reference level It compares, completes conversion of the BMC waveforms from analog quantity to digital quantity, recover the BMC signals of modulation, generate duty cycle signals.

Pretreatment circuit is the number that the BMC signals to the output of analog level comparison circuit are completed using internal reception clock Word samples, and for being pre-processed to duty cycle signals, i.e., the BMC waveforms recovered is sampled and pre-processed, judgement is No is effective BMC signals, and eliminates the influence of burr.

First channel selector SW-M and alternate path switch SW-N is all duty cycle signals transmission channel switch；It is accounted for when described When sky than signal is lead code, the first channel selector SW-M conductings, duty cycle signals are connected with parameter extraction estimating circuit；It is no Then, alternate path switch SW-N conductings, duty cycle signals are connected with decoding circuit.

Decoding circuit is used to be decoded duty cycle signals.

For parameter extraction estimating circuit for extracting effective duty cycle information from duty cycle signals, generation duty cycle is inclined Difference.

Error generation circuit compares duty cycle information with desired duty cycle parameter for handling duty cycle deviations Compared with generation error signal, that is, duty cycle error component.

Filtering feedback circuit includes feedback filter.Feedback filter is used to duty cycle error component carrying out digital filter Ripple is converted into control errors amount.

Control errors amount is converted into analog voltage signal by D/A converting circuit, is connected to analog level comparison circuit.

The circuit for detecting that activity indicating circuit is input signal is received, which is used to examine input signal It surveys.Its moment detects CC passages, if detect the input signal of validity feature, notifies the sequential control circuit, gives Go out the instruction for receiving effective input signal, subsequent receiving circuit enables, and starts to work normally.

Sequential control circuit controls and completes adaptive adjustment circuit and enables, and extraction estimation, the margin of error generates, the work(such as feedback The sequential of energy module, is completed to switching SW-M, the specific control of SW-N；I.e. for controlling the course of work of whole system, complete Adaptive duty cycle adjustment and the enabled and stopping for normally receiving function.The adaptive duty cycle adjustment of the utility model embodiment Circuit is carried out in the preamble sequence time windows of USB PD message packages, i.e., during adaptive duty cycle adjusts, SW-M Conducting, SW-N are disconnected.After the completion of adaptive dutyfactor adjustment circuit, switch SW-M is disconnected and SW-N is turned on.Receiving signal When movable indicating circuit is indicated without effective input signal, SW-M disconnections can be set and SW-N is also disconnected, to save overall power.

Above-mentioned each circuit module combination shown in Fig. 2 together constitutes the negative feedback loop of a BMC duty cycle adjust automatically Road, because parameter extraction estimating circuit is usually nonlinear, therefore the feedback control loop is typically all nonlinear feedback System.

Detecting of the activity indicating circuit to receiving terminal input signal is received, its moment detects the change of signal on CC passages Change.If detecting the characteristic signal in the range of certain frequency, the instruction for receiving effective input signal is provided, with being followed by Receipts system enables, and receiving circuit is started to work.Because adaptive algorithm is very quick for the mistake and abnormal conditions of input signal Sense, even has abnormal input waveform to enter reponse system, can cause adaptive algorithm severe exacerbation and nothing under certain conditions Method is recovered.Therefore one embodiment of the utility model is set, only when reception activity indicating circuit has monitored effective spy During the input signal of sign, adaptive duty cycle adjustment algorithm just enables work, and otherwise, entire adaptive feedback control loop is in not work Make state, be maintained at low-power consumption mode.

Fig. 3 is the partial information example of USB PD message packages, and wherein lead code Preamble is to access channel in physical layer When the targeting sequencing that sends, the effect of targeting sequencing is to make destination host receiver clock and the clock of source host transmitter same Step.In USB PD agreements, lead code is defined as " 0-1-0-1 " alternate code, and 0 is starting, and 1 is end.When targeting sequencing is sent After, followed by effective information part, start character " 00011 " of demarcating shown in figure for frame, " 00011 " is used to indicate The beginning of effective information.

When reception activity indicating circuit monitors the input signal of validity feature, adaptive duty cycle adjustment is calculated Method enables work.Analog level comparison circuit is using the analog waveform received as input terminal, by the output of D/A converting circuit Datum end as comparison circuit.If incoming signal level is more than datum, high level 1 is exported, is otherwise exported low Level 0.Analog level comparison circuit completes the conversion from BMC fluted moulds analog quantity to digital quantity, can recover the BMC letters of modulation Number.

Fig. 4 a are a kind of waveform diagram of the extraction duty cycle error provided according to the utility model one embodiment.

Parameter extraction estimating circuit extracts effective duty cycle parameter, and estimates from the BMC signals of pretreatment circuit output Go out to adjust proportional quantities, usually it is to be understood that different parameters method of estimation is to the impact factor of input signal duty cycle.The utility model One embodiment in, automatic duty cycle parameters be mainly track Bit-0 signals high level width and Bit-0 signals low electricity The slowly varying trend of flat width, i.e. low frequency component.Preamble sequence code in USB PD communications is handed over for " 0-1-0-1 " For code, the time window that we adjust time period as adaptive BMC waveform duty cycles, i.e., in this time window, SW-M switch conductions in circuit are set, backfeed loop is made to work, and SW-N switches disconnect, data do not enter BMC decoding circuits.

In fig.4, according to the level change of input waveform each time, the waveform received can be divided into six stages, A-B-C-D-E-F is labeled as successively.Cyclophysis is presented in targeting sequencing stage BMC waveforms, this six stages form once anti- Present the update cycle.The initial position for please noting that this six phased markers is random, i.e., any one stage in six stages is all It may mark and be, this is related with the time point of actual circuit beginning label, but has no effect on the result of algorithm.

The high level section of Bit-0 must be contained in this six stages, must also contain the low level section of Bit-0.

Fig. 4 b are parameter extraction estimating circuit schematic diagram.

Specific extraction estimate and obtain duty cycle adjusting parameter algorithm description it is as follows：

Sequential control circuit determines current level as lead code, the current generation is the adjusting stage according to the switching of level. In one example, two counters are set.Wherein high level width counter is used for counting longest high electricity in six stages Flat width sets count value as TH.Low level width counter is used for counting its longest low level width, sets count value For TL.

Then duty cycle deviations are calculated, subtract the result of TL using TH to represent the BMC of Bit-1 coding duty cycle deviations, A linear relationship is defined between the two, and note scale factor is λ, is had：

Terr=λ (TH-TL)

The value and D/A converting circuit range of λ, the conversion rate of analog level conversion circuit, low and high level width count Resolution ratio it is related.Its counter counts and the realization of calculation, can select to be carried with logic gates and realize, can also lead to Cross CPU programme-control realization.

In error generation circuit, the duty cycle deviations Terr that will be calculated, and it is expected that the deviation of duty cycle does subtraction, Obtain duty cycle error component, i.e. error signal.

As shown in figure 5, it is a kind of filtering feedback electrical block diagram.

Filtering feedback circuit includes a feedback filter.Wherein in order to preferably be filtered, therefore the utility model is real It applies example and selects first-order linear feedback filter.It is worth noting that, the utility model is not limited solely to first-order linear feedback filter Ripple device.First-order linear feedback filter filters out the high fdrequency component of error component, i.e., instantaneously divides according to above-mentioned duty cycle error component Amount.Its proportional path and integration access by linear combination, are formed control errors amount by filtering feedback circuit.

The model structure of first-order linear feedback filter as shown in figure 5, in the driving circuit by adder, multiplier and The effect of d type flip flop constitutes a single order infinite impulse response filter, can filter out the radio-frequency component of input signal.Wherein, P is gain control module, is the monotonically increasing function of g (n).The signal of output passes through linear group by proportional path and integration access It closes and forms.The x (n) wherein inputted is multiplied by a coefficient as proportional path, and the g (n) of input is integration access.As g (n)>When 0, y =P (g) * x, D are Estimation of Parameters module, are generally realized by accumulator or low-pass filter.In real work, which has one Rank IIR low-pass filter properties.

Wherein in single order infinite impulse response filter, the signal of input is multiplied by α by multiplier first, using tired Add device add up before d type flip flop store signal value, by d type flip flop store and export add up after signal value, the letter of output Number value be g (n).

After proportional path and integration access are by linear combination, missed by the accumulator deviation OffSet that adds up Poor controlled quentity controlled variable y (n).

With P (g)=g, D (y)=| y | exemplified by, backfeed loop is analyzed, can obtain linear renewal equation is：

G (n+1)=g (n) [1- α | x (n) |]

It is constant to make x (n)=cu (n), c, and range value, u (n) is jump function, and solution obtains steady-state response and is：

G (n)=[1- (1- α c)ⁿ]u(n)

The condition of convergence of the system is | 1- α c |<1, i.e., 0<αc<2.So：

As α c<When 1, system is in overdamping state；

As α c>When 1, system is in underdamping state；

As α c=1, system is in Critical damping state.

After the system model is applied to entire feedback control loop, when the error signal of input is larger, the tuned slope is big, convergence Comparatively fast.And after input error signal reduces, then the longer time is needed, system could restrain.

Fig. 6 is a kind of method stream for adaptive adjustment circuit of receiving end signal duty cycle that the utility model embodiment provides Cheng Tu.

Step 602, the first channel selector SW-M is disconnected, and alternate path switch SW-N is disconnected.

Step 603, receive activity indicating circuit and detect whether effective input signal input；If being returned without if Step 602.

Step 604, the first channel selector SW-M is turned on, and alternate path switch SW-N is disconnected, at the beginning of setting counting how many times Nstep Beginning turns to 1.

Step 605, extract and estimate duty cycle parameters, obtain duty cycle deviations, by error calculation, show that error is believed Number.

Step 606, error signal is input to filtering feedback unit, filters and adjusts digital analog converter output voltage, into For reference voltage；Analog level comparison circuit exports subsequent waveform under new reference voltage；Counting how many times Nstep simultaneously Increase by 1.

Step 607, judge counting how many times Nstep whether be equal to 8 or waveform duty cycle whether close to desired value, that is, export Duty cycle error signal very little, less than one preset threshold value；When above-mentioned condition is all unsatisfactory for, then return to step 605。

Step 608, the first channel selector SW-M is disconnected, alternate path switch SW-N conductings.

Step 609, the signal after adjustment enters decoding circuit, starts to receive and handles subsequent valid data；Above-mentioned mistake After the completion of journey, return to step 603.

After 608 first channel selector SW-M of above-mentioned steps is disconnected, circuit still works, simply the input letter of negative feedback path Number be 0.Because the record of last time adjustment is remain in filtering feedback circuit, even if the first channel selector SW-M breaks After opening, it can be still the good datum of analog level comparison circuit output adjustment, BMC waveforms are adjusted.

After above-mentioned steps 609 adjust, signal enters decoding circuit, starts to receive and handles subsequent valid data.It is preferred that , signal dutyfactor is 35% to 65%, it is believed that decoding circuit can be correctly decoded.For different circuits, allow correct Decoded signal dutyfactor scope bound amplitude variation is +/- 5%.

In the utility model, " connection ", it is connected, the word that " company ", the expressions such as " connecing " are electrical connected, such as nothing is especially said It is bright, then it represents that direct or indirect electric connection." row " or " row " in the utility model are all sensu lato meanings, both may be used To refer to a row horizontal in array, a vertical row can also be referred to.

The utility model embodiment receives the circuit structure of BMC code self-adaptings duty cycle adjustment, particularly with regard to USB PD communication control processors are applicable in but are not limited only to USB PD communication systems.

Above-described specific embodiment, the purpose of this utility model, technical solution and advantageous effect have been carried out into One step is described in detail, it should be understood that the foregoing is merely specific embodiment of the present utility model, is not used to limit Determine the scope of protection of the utility model, within the spirit and principle of the utility model, any modification for being made equally is replaced It changes, improve, should be included within the scope of protection of this utility model.

Claims (6)

1. a kind of circuit that receiving end signal duty cycle adaptively adjusts, which is characterized in that including：Analog level comparison circuit, First channel selector SW-M, alternate path switch SW-N, decoding circuit, parameter extraction estimating circuit, error generation circuit, filtering Feedback circuit and D/A converting circuit；

The analog level comparison circuit is for receiving input signal, based on received signal and datum generation duty cycle letter Number；

The first channel selector SW-M and alternate path switch SW-N is all the duty cycle signals transmission channel switch； When it is lead code to receive signal, the first channel selector SW-M conductings, the duty cycle signals and the parameter extraction are estimated Meter circuit is connected；Otherwise the alternate path switch SW-N conductings, the duty cycle signals are connected with the decoding circuit；

The decoding circuit is used to be decoded the duty cycle signals；

The parameter extraction estimating circuit generates duty cycle deviations for obtaining duty cycle information from the duty cycle signals；

The error generation circuit generates error signal for the duty cycle deviations to be handled；

The filtering feedback circuit is used to the error signal being converted to control errors amount；

The D/A converting circuit is used to the control errors amount being converted to analog signal from digital signal, and this is converted Analog signal afterwards is as the datum end being output to reference to level in the analog level comparison circuit.

2. circuit according to claim 1, which is characterized in that further include：Circuit is pre-processed, for believing the duty cycle It number is pre-processed, differentiates whether the duty cycle signals in certain spectral range and eliminate burr.

3. circuit according to claim 1, which is characterized in that the filtering feedback circuit includes：Feedback filter；It is described Feedback filter is used to the error signal filtering out high fdrequency component, and the control errors amount is formed by linearly calculating.

4. circuit according to claim 1, which is characterized in that further include：Sequential control circuit；

The sequential control circuit is used to control the overall workflow of the adaptive adjustment circuit of receiving end signal duty cycle； It is carried out in the preamble sequence time window of USB PD message packages, i.e., during adaptive duty cycle adjusts, SW-M conductings, SW-N It disconnects；After adaptive dutyfactor adjustment circuit is completed to adjust, switch SW-M is disconnected and SW-N is turned on.

5. circuit according to claim 1, which is characterized in that further include：Receive activity indicating circuit；

The reception activity indicating circuit is for being detected input signal, if detecting the input letter of validity feature Number when, then enable sequential control circuit and reception system, receiving circuit is started to work.

6. circuit according to claim 1, which is characterized in that the duty cycle of SW-N is switched by the alternate path The duty cycle of signal is 35% to 65%, and the deviation of permission is +/- 5%.