CN207367976U - A kind of thin film transistor (TFT), array base palte, display device - Google Patents
A kind of thin film transistor (TFT), array base palte, display device Download PDFInfo
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- CN207367976U CN207367976U CN201721532908.2U CN201721532908U CN207367976U CN 207367976 U CN207367976 U CN 207367976U CN 201721532908 U CN201721532908 U CN 201721532908U CN 207367976 U CN207367976 U CN 207367976U
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Abstract
The utility model provides a kind of thin film transistor (TFT), array base palte, display device, belongs to display technology field, it can solve the problems, such as that polysilicon is easily spent quarter in existing LTPS.The thin film transistor (TFT) of the utility model includes multilayer dielectric layer, wherein, the insulating layer that at least one layer is arranged on above low-temperature polycrystalline silicon layer is formed using resin material, it is follow-up when via is formed in the resin material, without dry carving technology, using the method for exposure imaging, it is possible to prevente effectively from the low-temperature polycrystalline silicon layer below the insulating layer is crossed and carved.The thin film transistor (TFT) of the utility model can also increase the contact area and homogeneity of drain electrode and low-temperature polysilicon silicon material layer, improve electrical conductivity；The exposure imaging technique of second via of the second insulating layer and the first via of the first insulating layer can be completed with a step, and the production cycle of product is greatly decreased, and improve equipment capacity.
Description
Technical field
The utility model belongs to display technology field, and in particular to a kind of thin film transistor (TFT), array base palte, display device.
Background technology
With the raising of people's quality of the life, user has the display brightness, angles of display and low energy consumption of display screen
The requirement of higher, such as：In the more sufficient open air of light or place, it is necessary to which display screen has clearer display effect, just
Display screen is needed to have the brightness of higher；Need to clearly indicate under different gestures different angle state in Working Life
Effect, it is necessary to which display screen has wider array of visual angle；For the purposes of more long usage time, it is also desirable to which display screen has lower energy
Consumption.
Low-temperature polysilicon silicon technology (Low Temperature Poly Silicon, LTPS) can reduce the energy consumption of display screen,
Make display screen more frivolous, LTPS is to form polysilicon (p-Si) by " low temperature " crystallization process by non-crystalline silicon (a-Si) film
Technology.
Inventor has found that at least there are the following problems in the prior art：Since a-Si is being changed into P-Si processes, only table
The a-Si on the face 50 Izod right side becomes for P-Si, P-Si very thin thickness, during subsequent technique dry etching, due to the limit of dry etching technology
System, often occurred quarter, caused P-Si to be carved or unkind, caused SD to diminish with the contact area of P-Si or contact inequality
It is even.
Utility model content
The utility model is directed to the problem of P-Si is easily spent quarter in existing LTPS, there is provided a kind of thin film transistor (TFT), battle array
Row substrate, display device.
Technical solution is used by solving the utility model technical problem：
A kind of thin film transistor (TFT), including substrate, and low-temperature polycrystalline silicon layer on the substrate, multilayer dielectric layer,
Grid；
Wherein, at least one layer of insulating layer is made of resin material, and is arranged on one of the low-temperature polycrystalline silicon layer away from substrate
The insulating layer of side is equipped with via.
Preferably, the insulating layer includes the first insulating layer, and the via of first insulating layer is the first via；Its
In, first insulating layer is arranged between the low-temperature polycrystalline silicon layer and the grid, and it is exhausted that the grid is arranged on described first
Side of the edge layer away from substrate.
Preferably, the insulating layer further includes the second insulating layer, and second insulating layer is arranged on the grid away from lining
The side at bottom, and second insulating layer is equipped with the second via.
Preferably, the thin film transistor (TFT) further includes：
Source electrode and drain electrode, the source electrode and drain electrode are arranged on the side of second insulating layer away from substrate, and the source electrode
Contacted with drain electrode by the first via, the second via with low-temperature polycrystalline silicon layer.
Preferably, in first via at least part orthographic projection on substrate and the second via to substrate at least
Part orthographic projection overlaps.
Preferably, the thin film transistor (TFT) further includes：Flatness layer and public electrode, the flatness layer are arranged on source electrode and leakage
Between pole and the public electrode, the flatness layer is arranged on the source electrode and drains from the side of substrate, and where the drain electrode
The 3rd via is equipped with flatness layer at position, the public electrode is connected by the 3rd via and the drain electrode.
Preferably, the resin material includes polymethyl methacrylate (PMMA), polyethylene terephthalate
(PET), any one or a few in makrolon (PC), polyurethane (PU), polyimides (PI).
Preferably, on the direction of the substrate, the size of the insulating layer is 1.5 μm~3.0 μm.
Preferably, cushion is equipped between the substrate and the low-temperature polycrystalline silicon layer.
The utility model also provides a kind of array base palte, including the multiple above-mentioned thin film transistor (TFT)s being distributed in array-like.
The utility model also provides a kind of display device, including above-mentioned array base palte.
The utility model also provides a kind of preparation method of thin film transistor (TFT), comprises the following steps：
Low-temperature polysilicon silicon material layer is formed on substrate；
Resin bed is formed in side of the low-temperature polycrystalline silicon layer away from substrate, and sets via to obtain absolutely in the resin bed
Edge layer；
The first metal layer is formed, and patterned first metal layer obtains the grid of thin film transistor (TFT).
Preferably, the formation resin bed, and set via to obtain insulating layer, including following step in the resin bed
Suddenly：
Coated with resins material forms organic film；
First time curing is carried out to organic film；
Development is exposed to the organic film for completing above-mentioned steps and forms via；
Second of curing is carried out to the organic film for completing above-mentioned steps and obtains insulating layer.
Preferably, first time cure be in vacuum be 20Pa~100Pa, heating-up temperature is 80 DEG C~130 DEG C
Under conditions of carry out 90s-140s；Described second, which cures, is carried out under conditions of normal heating temperature is 200 DEG C~250 DEG C
40min~120min.
The thin film transistor (TFT) of the utility model includes multilayer dielectric layer, wherein, at least one layer is arranged on low-temperature polycrystalline silicon layer
The insulating layer of top is formed using resin material, and follow-up during formation via, without dry carving technology, uses in the resin material
The method of exposure imaging, so it is possible to prevente effectively from the low-temperature polycrystalline silicon layer below the insulating layer is crossed and carved.
The preparation method of the thin film transistor (TFT) of the utility model is it is possible to prevente effectively from low-temperature polycrystalline silicon layer below insulating layer
Carved by crossing, while the contact area and homogeneity of drain electrode and low-temperature polysilicon silicon material layer can be increased, improve electrical conductivity；Second is exhausted
The exposure imaging technique of second via of edge layer and the first via of the first insulating layer can be completed with a step, and product can be greatly decreased
Production cycle, improve equipment capacity.
Brief description of the drawings
Fig. 1 is the structure diagram of the thin film transistor (TFT) of the embodiment 1 of the utility model；
Fig. 2-3 is the structure diagram of the thin film transistor (TFT) of the embodiment 2 of the utility model；
Fig. 4 is the preparation flow schematic diagram of the thin film transistor (TFT) of the embodiment 3 of the utility model；
Wherein, reference numeral is：1st, substrate；2nd, low-temperature polycrystalline silicon layer；21st, doped region；3rd, insulating layer；31st, the first insulation
Layer；32nd, the second insulating layer；4th, grid；5th, via；51st, the first via；52nd, the second via；53rd, the 3rd via；61st, source electrode；
62nd, drain；7th, flatness layer；81st, public electrode；82nd, pixel electrode；91st, cushion；92nd, passivation layer.
Embodiment
It is below in conjunction with the accompanying drawings and specific real to make those skilled in the art more fully understand the technical solution of the utility model
Mode is applied to be described in further detail the utility model.
Embodiment 1：
The present embodiment provides a kind of thin film transistor (TFT), as shown in Figure 1, including substrate 1,
Low-temperature polycrystalline silicon layer 2, multilayer dielectric layer 3, grid 4 on the substrate 1；Wherein, at least one layer of insulating layer
It is made of resin material, and the insulating layer arranged on the side of the low-temperature polycrystalline silicon layer 2 away from substrate is equipped with via 5.
The thin film transistor (TFT) of the present embodiment includes multilayer dielectric layer 3, wherein, at least one layer is arranged on the low temperature polycrystalline silicon
The insulating layer 3 of the top of layer 2 is formed using resin material,
It is follow-up when via 5 is formed in the resin material, without dry carving technology, using the method for exposure imaging,
So it is possible to prevente effectively from the low-temperature polycrystalline silicon layer 2 below the insulating layer is crossed and carved.
Embodiment 2：
The present embodiment provides a kind of thin film transistor (TFT), as Figure 2-3, including substrate 1, and on the substrate 1
The low-temperature polycrystalline silicon layer 2 of side, the first insulating layer 31, the grid 4 being made of resin material；Specifically, the first insulating layer 31 is arranged on
The side of the low-temperature polycrystalline silicon layer 2 away from substrate, the grid 4 are arranged on the side of the first insulating layer 31 away from substrate；
Wherein, the first insulating layer 31 is equipped with the first via 51.
Substrate 1 in the present embodiment can use the transparent materials such as glass to be made, specifically, the corresponding attached drawing of the present embodiment
The low-temperature polycrystalline silicon layer 2 shown in 2 is used as active layer, doped with phosphorus or boron at which part position, forms doped region 21, to increase
Its strong characteristic electron.Grid 4 therein is formed using at least one of molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper.Its
In, the first insulating layer 31 of side of the present embodiment low-temperature polycrystalline silicon layer 2 away from substrate is alternatively referred to as interlayer insulating film, it is used
Resin material is formed, and when via is formed so in the resin material, dry carving technology is not used, using the method for exposure imaging
The first via 51 can be formed, effectively avoids the low-temperature polycrystalline silicon layer 2 of the lower section of the first insulating layer 31 from being crossed and carves.
As a kind of preferred embodiment in the present embodiment, the resin material includes transparent poly-methyl methacrylate
Appointing in ester (PMMA), polyethylene terephthalate (PET), makrolon (PC), polyurethane (PU), polyimides (PI)
Meaning is one or more of.
Specifically, the transparent resin material in the present embodiment is selected from transparent polymeric material, due to the material transparent, because
This does not influence the transmitance of product.In addition, above-mentioned material when forming via, selects corresponding mask plate to use exposure imaging work
Skill, reduces by a step dry etching, saves process costs.
As a kind of preferred embodiment in the present embodiment, on the direction of the substrate 1, the insulating layer
Size be 1.5 μm~3.0 μm.
That is, referring to Fig. 2, the thickness H1 of the first insulating layer 31 is in 1.5 μm~3.0 μ ms.That is resin material
Thickness H1 be so that more than 1.5 μm of effect between the grid 4 above resin material and 2 structure of low-temperature polycrystalline silicon layer of lower section
Reach certain insulation performance；Meanwhile the thickness H1 of resin material is no more than 3.0 μm, so not meaningless increase product itself
Thickness, is more suitable for ultra-thin display.
In one embodiment, cushion 91 is equipped between the substrate 1 and the low-temperature polycrystalline silicon layer 2.
Referring to the corresponding attached drawing 2 of the present embodiment, cushion 91, cushion are added between substrate 1 and low-temperature polycrystalline silicon layer 2
91 can be the laminated construction of single layer structure or multiple sublayers, and cushion 91 is formed using Si oxide or silicon nitride.
In one embodiment, the insulating layer further includes the second insulating layer 32, and second insulating layer 32 is arranged on described
Side of the grid 4 away from substrate, and second insulating layer 32 is equipped with the second via 52.
In one embodiment, the thin film transistor (TFT) further includes source electrode 61 and drain electrode 62, the source electrode 61 and drain electrode 62
Above second insulating layer 32, and the source electrode 61 and drain electrode 62 pass through the first via 51, the second via 52 and low temperature
Polysilicon layer 2 contacts.
Referring to the corresponding attached drawing 3 of the present embodiment, the second insulating layer 32 is equipped with grid 4, alternatively referred to as grid 4 insulate
Layer, the second insulating layer 32 are also formed using transparent resin material, equally, the second via can be formed using the method for exposure imaging
52, effectively avoid low-temperature polycrystalline silicon layer 2 from being crossed and carve.Further, since the second via 52 of the second insulating layer 32 and the first insulating layer
31 the first via 51 is corresponding, and the second insulating layer 32 is also by the present embodiment using the advantages of transparent resin material formation：The
One via 51 is formed with the second via 52 using a step exposure technology, saves product cost.
It is understood that the second insulating layer 32 can not also use transparent resin material to be formed but use nitridation silica
Silicon nitride material, i.e., formed using transparent resin material adjacent only to the first insulating layer 31 of low-temperature polycrystalline silicon layer 2, so can also
Avoid low-temperature polycrystalline silicon layer 2 by cross carved, but so the shortcomings that be：First insulating layer 31 uses different works from the second insulating layer 32
Skill, the first via 51 cannot synchronously expose to be formed with the second via 52, and the mode compared to step exposure adds the work of product
Skill cost.
As a kind of preferred solution of the present embodiment, first via at least part orthographic projection and second on substrate
At least part orthographic projection on via to substrate overlaps.
That is, on the direction perpendicular to substrate, the second via 52 and the first insulating layer 31 of the second insulating layer 32
The first via 51 it is corresponding, so when using exposure imaging technique formed via when, the second via 52 and the first via 51 can
Completed with a step, save Product Process cost.
In one embodiment, the thin film transistor (TFT) further includes：Flatness layer 7 and public electrode 81, flatness layer 7 are arranged on institute
62 sides away from substrate of source electrode 61 and drain electrode are stated, and the flatness layer 7 of the drain electrode position is equipped with the 3rd via 53, institute
State public electrode 81 to be arranged on the flatness layer 7, and be connected by the 3rd via 53 with the drain electrode 62.
In the corresponding attached drawing 3 of the present embodiment, it is shown that be formed at the flat of 62 sides away from substrate of source electrode 61 and drain electrode
Smooth layer 7, the 3rd via 53 of flatness layer 7 correspond to the position of drain electrode 62, and the public electrode 81 on flatness layer 7 passes through the 3rd via 53
It is connected with drain electrode 62.In addition, in attached drawing 3, it also show passivation layer 92 and be equipped with pixel electrode 82, and pixel electrode 82 is by blunt
The via for changing layer 92 is connected with public electrode 81.It is only in the size of each structure, thickness etc. shown in the attached drawing that the present embodiment is shown
Signal.In technique realization, the projected area of each structure sheaf on substrate 1 may be the same or different, and can pass through etching
Technique realizes required each structure sheaf projected area；Meanwhile structure shown in attached drawing does not limit the geometry of each structure sheaf, example yet
As can be rectangle shown in the drawings, trapezoidal or formed other etchings shape, equally can pass through to etch and realize.
Embodiment 3：
The present embodiment provides a kind of preparation method of thin film transistor (TFT), comprise the following steps：
S01a, using Si oxide or silicon nitride form cushion 91 on substrate 1, specifically, substrate 1 uses glass
It is made Deng transparent material and passes through pre-wash.Cushion 91 can be single layer structure or the laminated construction of multiple sublayers.
S01b, form low-temperature polysilicon silicon material layer on the substrate 1 for completing above-mentioned steps；Specifically, first sink on substrate 1
Product non-crystalline silicon a-Si, then carries out crystallization to non-crystalline silicon using " low temperature " crystallization process and forms polysilicon P-Si, wherein, surface
The a-Si at least 50 Izods right side becomes for P-Si.Excimer-Laser Crystallization mode, metal-induced crystallization mode are more for two kinds of low temperature
The method of crystal silicon is more common the method that amorphous silicon is polysilicon.However, the utility model is by amorphous silicon
For the method for polysilicon, the method using low temperature polycrystalline silicon is not restricted to, as long as can be institute by active layer amorphous silicon
The polysilicon membrane needed can.
S02, form transparent resin material on the substrate 1 for completing above-mentioned steps, and is set in the transparent resin material
Put the first via 51 and obtain the first insulating layer 31.
Specifically, S02 comprises the following steps：
S02a, coating transparent resin form the first organic film that thickness range is generally 1.5um~3.0um；It is described
Ming tree fat includes polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), makrolon (PC), poly- ammonia
Any one or a few in ester (PU), polyimides (PI).It should be noted that the transparent resin of coating can be multilayer,
It can also be individual layer, can be the performed polymer of the above-mentioned several polymer enumerated or the list of polymer raw material polymer
The mixed solution of body.The detailed description of subsequent process steps, other transparent trees are carried out in the present embodiment by taking PMMA performed polymers as an example
The concrete condition of fat is similar with PMMA.
S02b, in vacuum be 20~100Pa, and heating-up temperature under conditions of being 80~130 DEG C have the first PMMA
Machine film layer carries out 90s-140s curings；
S02c, be exposed the first PMMA organic films for completing above-mentioned steps development the first via 51 of formation；The step
Light exposure in rapid is 150~300mj.
S02d, obtain the first insulating layer 31 to second of the curing of the first organic film progress for completing above-mentioned steps.Specifically
, it is to carry out 40min~120min under conditions of normal heating temperature is 200 DEG C~250 DEG C that second, which cures,.
S03, form the first metal layer, and patterned first metal layer obtains the grid 4 of thin film transistor (TFT).Wherein, grid
Material include but are not limited to the metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi, the one or more in material.
The thickness of the grid is 1500~6000 angstroms.
S04, form transparent resin material again on the substrate 1 for completing above-mentioned steps, and in the transparent resin material
The second via 52 of middle setting obtains the second insulating layer 32.
Specifically, S04 comprises the following steps：
S04a, coating transparent resin form the 2nd PMMA organic films that thickness range is generally 1.5um~3.0um；Its
In, the transparent resin of coating can be multilayer or individual layer, can be the performed polymer or polymer of polymer
The mixed solution of the monomer of raw polymer.S04b, in vacuum be 20~100Pa, and heating-up temperature is 80~130 ° of condition
Under carry out to the 2nd PMMA organic films carry out first time curing；
S04c, be exposed the 2nd PMMA organic films for completing above-mentioned steps development the second via 52 of formation；The step
Light exposure in rapid is 150~300mj.
S04d, obtain the second insulating layer 32 to second of the curing of the second organic film progress for completing above-mentioned steps.Specifically
, it is to carry out 40min~120min under conditions of normal heating temperature is 200 DEG C~250 DEG C that second, which cures,.
It should be noted that the second via 52 of the second insulating layer 32 is opposite with the first via 51 of the first insulating layer 31
Should, the exposure imaging technique of S02c and S04c can be completed with a step, save Product Process cost.
S05, form source electrode 61 and drain electrode 62 on the second insulating layer 32, specifically, source electrode 61, drain electrode 62 are using molybdenum, molybdenum
The formation of at least one of niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper.More specifically, sputtering mode, thermal evaporation side can be used
Formula, plasma enhanced chemical vapor deposition (Plasma Enhanced Vapor Deposition：Abbreviation PECVD) mode,
Low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition：Abbreviation LPCVD) mode, atmospheric pressure
Chemical vapor deposition (Atmospheric Pressure Chemical Vapor Deposition：Abbreviation APCVD) mode or
Electron cyclotron resonance chemical vapor deposition (Electron Cyclotron Resonance Chemical Vapor
Deposition:Abbreviation ECR-CVD) mode forms source and drain metal electrode film.Then, by using half-tone mask (Half
Tone Mask, abbreviation HTM) or gray mask (Gray Tone Mask, abbreviation GTM), by patterning processes, (film forming, expose
Light, development, wet etching or dry etching), while form the figure for including source electrode 61 and drain electrode 62.
S06, form flatness layer 7 on source electrode 61 and drain electrode 62, and the 3rd via 53 is formed in the correspondence drain electrode 62, public
Electrode 81 is electrically connected by the 3rd via 53 with drain electrode 62.Then public electrode 81 is formed on flatness layer 7.Wherein, formed flat
The effect of smooth layer 7 is：So that the upper surface planarization of product, so as to depositing electrode layer on a flat surface.
S07, form passivation layer 92 on public electrode 81, and forms the 3rd via 53 in passivation layer 92.Wherein, passivation layer
92 be single layer structure or the laminated construction of multiple sublayers, using Si oxide, silicon nitride, hafnium oxide or aluminum oxide shape
Into.
S08, form pixel electrode 82, the via and public electrode that pixel electrode 82 passes through passivation layer 92 on passivation layer 92
81 connections.
Be described in detail in the present embodiment using PMMA transparent resins as insulation layers, other transparent resins it is specific
Situation is similar with PMMA, no longer enumerates.
Insulating layer is formed using transparent resin material in the preparation method of the present embodiment, and the via of insulating layer is without dry etching work
Skill, but the method for using exposure imaging, so it is possible to prevente effectively from the low-temperature polycrystalline silicon layer below insulating layer is crossed and carved,
The contact area and homogeneity of drain electrode and low-temperature polysilicon silicon material layer can be increased at the same time, improve electrical conductivity；Second insulating layer
The exposure imaging technique of first via of the second via and the first insulating layer can be completed with a step, and the production of product can be greatly decreased
In the cycle, improve equipment capacity.
Embodiment 4：
The present embodiment provides a kind of array base palte, including the multiple above-mentioned thin film transistor (TFT)s being distributed in array-like.
Embodiment 5：
A kind of display device is present embodiments provided, it includes any one above-mentioned array base palte.The display device can
Think：Liquid crystal display panel, Electronic Paper, mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigation
Any product or component with display function such as instrument.
Obviously, also many modifications may be made to for the embodiment of the various embodiments described above；Such as：Each processing step it is specific
Parameter can be adjusted as needed, and the specific steps of different product can be changed according to actual conditions.
It is understood that embodiment of above is merely to illustrate that the principle of the utility model and uses exemplary
Embodiment, but the utility model is not limited thereto.For those skilled in the art, this is not being departed from
In the case of the spirit and essence of utility model, various changes and modifications can be made therein, these variations and modifications are also considered as this reality
With new protection domain.
Claims (10)
- A kind of 1. thin film transistor (TFT), it is characterised in that including substrate, and it is low-temperature polycrystalline silicon layer on the substrate, more Layer insulating, grid；Wherein, at least one layer of insulating layer is made of resin material, and arranged on side of the low-temperature polycrystalline silicon layer away from substrate Insulating layer is equipped with via.
- 2. thin film transistor (TFT) according to claim 1, it is characterised in that the insulating layer includes the first insulating layer, described The via of first insulating layer is the first via；Wherein, first insulating layer is arranged at the low-temperature polycrystalline silicon layer and the grid Between pole, the grid is arranged on the side of first insulating layer away from substrate.
- 3. thin film transistor (TFT) according to claim 2, it is characterised in that the insulating layer further includes the second insulating layer, institute State the second insulating layer and be arranged on side of the grid away from substrate, and second insulating layer is equipped with the second via.
- 4. thin film transistor (TFT) according to claim 3, it is characterised in that the thin film transistor (TFT) further includes：Source electrode and drain electrode, the source electrode and drain electrode are arranged on the side of second insulating layer away from substrate, and the source electrode and leakage Pole is contacted by the first via, the second via with low-temperature polycrystalline silicon layer.
- 5. thin film transistor (TFT) according to claim 4, it is characterised in that first via at least part on substrate Orthographic projection is overlapped with least part orthographic projection on the second via to substrate.
- 6. thin film transistor (TFT) according to claim 4, it is characterised in that the thin film transistor (TFT) further includes：Flatness layer and Public electrode, the flatness layer be arranged between source electrode and drain electrode and the public electrode, the flatness layer be arranged on the source electrode and Side of the drain electrode away from substrate, and the 3rd via is equipped with the flatness layer of the drain electrode position, the public electrode leads to The 3rd via is crossed to connect with the drain electrode.
- 7. thin film transistor (TFT) according to claim 1, it is characterised in that the resin material includes poly-methyl methacrylate Any one or a few in ester, polyethylene terephthalate, makrolon, polyurethane, polyimides.
- 8. thin film transistor (TFT) according to claim 1, it is characterised in that described on the direction of the substrate The size of insulating layer is 1.5 μm~3.0 μm.
- 9. a kind of array base palte, it is characterised in that including the multiple thin film transistor (TFT)s being distributed in array-like, the thin film transistor (TFT) Including claim 1-8 any one of them thin film transistor (TFT)s.
- 10. a kind of display device, it is characterised in that including the array base palte described in claim 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019095857A1 (en) * | 2017-11-16 | 2019-05-23 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method therefor, array substrate, and display device |
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2017
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019095857A1 (en) * | 2017-11-16 | 2019-05-23 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method therefor, array substrate, and display device |
| CN109801923A (en) * | 2017-11-16 | 2019-05-24 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array substrate, display device |
| US11588055B2 (en) | 2017-11-16 | 2023-02-21 | Ordos Yuangsheng Optoelectronics Co., Ltd. | Thin-film transistor and method for manufacturing the same, array substrates, display devices |
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