CN207330353U - The package carrier three-dimensionally integrated for SIP - Google Patents
The package carrier three-dimensionally integrated for SIP Download PDFInfo
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- CN207330353U CN207330353U CN201720849124.6U CN201720849124U CN207330353U CN 207330353 U CN207330353 U CN 207330353U CN 201720849124 U CN201720849124 U CN 201720849124U CN 207330353 U CN207330353 U CN 207330353U
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- substrate
- shell
- metal
- bottom plate
- dimensionally integrated
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Abstract
A kind of package carrier three-dimensionally integrated for SIP of the utility model, including shell, substrate, metal cover board, the substrate is arranged on the shell, and the cavity for being used for accommodating chip is formed between the substrate and the shell, the shell, substrate use non-conducting material, and the electric signal between the shell and substrate is interconnected, the metal cover board is positioned on the shell and the metal cover board is located on the outside of the substrate, is sealed against each other between the metal cover board and the shell.The utility model, which is used for the three-dimensionally integrated package carriers of SIP, realizes the 3D encapsulation with cavity, and substrate and shell can respectively be assembled, separately tested, and be combined into a system entirety after separately test calibration is good, improved the yield rate of system, reduce cost.
Description
Technical field
A kind of package carrier is the utility model is related to, more particularly to a kind of package carrier of chip.
Background technology
SIP (System In a Package) encapsulation be by multiple and different devices, such as MEMS (MEMS,
Micro-Electro-Mechanical System), the element such as optics (Optics) be integrated into a packaging body, form one
A system or subsystem.The directions such as High Density Integration, high power density, high reliability drive under, packing forms from 2D into
The 3D epoch are entered.At present, three-dimensional integration technology is mostly based on Silicon Wafer, wherein containing TSV (Through Silicon Via)
Three-dimensional stacked technology be typically to represent.The three-dimensional integration technology of package carrier is used as either using silicon, ceramics or plastics
Have focused largely in stacking and its interconnection of multiple chips, encapsulation schematic diagram as shown in Figure 1 is its Typical Representative, encapsulates base
Plate 1 can be made of silicon, ceramics and plastics, and silicon hole pinboard 2 is stacked with multiple chips, and upper and lower two chips pass through silicon hole
(TSV) 4 interconnected relationship is formed.
Utility model content
The primary and foremost purpose of the utility model is to provide a kind of package carrier three-dimensionally integrated for SIP, above-mentioned existing to solve
The problem of with the presence of technology, it can form the space cavity ensured needed for systemic-function, allow the chip unit of system to realize 3D
It is integrated.
To achieve the above object, the utility model provides following scheme：The utility model is a kind of three-dimensionally integrated for SIP
Package carrier, including shell, substrate, metal cover board, the substrate be arranged on the shell, and in the substrate and institute
State the cavity for being formed between shell and being used for accommodating chip, the shell, substrate use non-conducting material, and the shell with
Electric signal between substrate is interconnected, and the metal cover board is positioned on the shell and the metal cover board is positioned at described
On the outside of substrate, sealed against each other between the metal cover board and the shell.
The utility model is used for the three-dimensionally integrated package carriers of SIP, wherein, the shell and substrate are made of plastics,
The shell includes bottom plate and side wall, and the plate upper surface sets bottom plate lead frame made of metal, set in the side wall
Metal ferrule, the metal ferrule bottom are connected with the bottom plate lead frame, and the base lower surface sets base made of metal
Plate lead frame, the metal ferrule upper end and substrate lead frame conducting.
The utility model is used for the three-dimensionally integrated package carriers of SIP, wherein, connection is provided with the lower surface of the substrate
Groove, the metal ferrule top is placed in the link slot, and the metal ferrule and the substrate of link slot periphery draw
Wire frame is welded to each other by solder(ing) paste.
The utility model is used for the three-dimensionally integrated package carriers of SIP, wherein, the substrate lead frame, bottom plate lead frame are equal
It is made of copper alloy.
The utility model is used for the three-dimensionally integrated package carriers of SIP, wherein, the shell and substrate are using ceramic material
Matter, the shell include bottom plate and side wall, and the plate upper surface sets sole plate metal figure, and the top side wall sets side wall
Sheet metal, the base lower surface set substrate metal piece, and the side-wall metallic piece and the substrate metal piece are welded to each other.
The utility model is used for the three-dimensionally integrated package carriers of SIP, wherein, the sole plate metal figure, side-wall metallic piece,
Substrate metal piece is made of gold, and is electroplated respectively on the bottom plate, side wall and substrate.
The utility model is used for the three-dimensionally integrated package carriers of SIP, wherein, the shell and the metal cover board pass through flat
Row soldering and sealing or soldering are welded to each other.
The utility model is used for the three-dimensionally integrated package carriers of SIP, wherein, leave electric signal interface on the bottom plate of shell.
The utility model achieves following technique effect relative to the prior art：Since the utility model is used for SIP three-dimensionals
Integrated package carrier includes substrate and shell, and substrate is arranged on shell, and cavity is formed between substrate and shell, real
The 3D encapsulation with cavity is showed, and substrate and shell can respectively be assembled, separately tested, and be combined into after separately test calibration is good
One system entirety, improves the yield rate of system, reduces cost.
Further, since shell and substrate are made of plastics, process, be molded comparatively fast, cost is low, the cycle is short, can be quick
Realize the encapsulation verification to system, suitable for the fast verification of development phase, metal ferrule is set, shaping is compared in the side wall
Flexibly, it can be that shell shaping or first shell shaping, reserved contact pin groove are first interconnected again with lead frame, finally assemble
Contact pin.
In addition, when shell and substrate use ceramic material, it is possible to achieve the level Hermetic Package of high reliability, suitable for formal
The encapsulation of product.Electric signal interface is left on the bottom plate of shell, is easy to integrated with the assembling of other systems.
Brief description of the drawings
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Needed in attached drawing be briefly described, it should be apparent that, drawings in the following description are only the utility model
Some embodiments, for those of ordinary skill in the art, without having to pay creative labor, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is existing SIP encapsulating structures figure；
Fig. 2 is the structure diagram that the utility model is used for substrate in the three-dimensionally integrated package carrier embodiments one of SIP；
Fig. 3 is the structure diagram that the utility model is used for shell in the three-dimensionally integrated package carrier embodiments one of SIP；
Fig. 4 is when being used for the construction packages chip of the three-dimensionally integrated package carrier embodiments one of SIP using the utility model
Schematic diagram；
Fig. 5 is when being used for the construction packages chip of the three-dimensionally integrated package carrier embodiments two of SIP using the utility model
Schematic diagram.
Embodiment
The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without making creative work
All other embodiments obtained, shall fall within the protection scope of the present invention.
To enable the above-mentioned purpose of the utility model, feature and advantage more obvious understandable, below in conjunction with the accompanying drawings and have
Body embodiment is described in further detail the utility model.
Embodiment one
As shown in figure 4, the utility model is used for the three-dimensionally integrated package carriers of SIP, including shell 11, substrate 21, metal
Cover board 50, shell 11 use plastic material, as shown in figure 3, shell 11 includes bottom plate and side wall, side wall has certain altitude, bottom
Plate upper surface sets bottom plate lead frame 10 made of metal, and metal ferrule 12,12 bottom of metal ferrule and bottom plate are set in side wall
Lead frame 10 connects, and substrate 21 is made of plastics, as shown in Fig. 2, 21 lower surface of substrate sets substrate lead frame 20, metal ferrule
12 upper ends and substrate lead frame 20 turn on, and the quantity and distributing position of metal ferrule 12 can be according to actual chip layouts and reality
Signal wire quantity is adjusted flexibly, and the shape of bottom plate lead frame 10 and the shape of substrate lead frame 20 can be set on demand, bottom plate
Lead frame 10, substrate lead frame 20 are made by copper alloy, and substrate 21 is arranged on shell 11, and in substrate 21 and shell 11
Between formed and be used to accommodate the cavity of chip, metal cover board 50 is positioned on shell 11 and metal cover board 50 is located at outside substrate 21
Side, seals against each other between metal cover board 50 and shell 11, and electric signal I/O interface is left on the bottom plate of shell 11.
As shown in Figure 2,3, 4, for ease of shell 11 and the assembling of substrate 21 positioning and electricity interlinkage, on the lower surface of substrate 21
Link slot 22 is provided with, the top side wall that shell 11 is stretched out at the top of metal ferrule 12 is placed in link slot 22, and metal ferrule 12
It is welded to each other with the substrate lead frame 20 of the periphery of link slot 22 by solder(ing) paste.
When shell 11 is molded, first metal ferrule 12 and bottom plate lead frame 10 are connected with each other, are then molded, after injection molding
Bottom plate lead frame 10, metal ferrule 12 and polymer plastic form the shell 11.It is used for alternatively, being reserved with injection moulding process
The groove of metal ferrule 12 is assembled, after 11 injection molding of shell, reassembles metal ferrule 12.
As shown in figure 4, optical detection chip 42 is mounted on substrate lead frame 20, optical detection chip 42 and substrate lead
Frame 20 is interconnected by bonding wire to realize, inside shell 11, driving MEMS chip 41 is fixed on pipe by bonded adhesives 30
11 bottom of shell, sensor chip 43 are stacked in driving MEMS chip 41, are fixed by middle bonding gemel connection, sensor chip
Electric signal is realized by bonding wire respectively between 43 and driving MEMS chip 41, between driving MEMS chip 41 and shell 11
Connection.After substrate 21 and shell 11 assemble, metal cover board 50 is capped, ultimately forms a closed complete package body.
Embodiment two
As shown in figure 5, the utility model, which is used for the three-dimensionally integrated package carriers of SIP, includes shell 11 ", substrate 21 ", metal
Cover board 50 ", shell 11 " and substrate 21 " use ceramic material, and shell 11 " includes bottom plate and side wall, and side wall has certain high
Degree, plate upper surface are provided with the sole plate metal figure 102 made of sheet metal, and top side wall sets side-wall metallic piece 103,
The lower surface of substrate 21 " sets substrate metal piece 202, and substrate 21 " is arranged on shell 11 ", and in substrate 21 " and shell 11 "
Between formed and be used to accommodate the cavity of chip, side-wall metallic piece 103 and substrate metal piece 202 are welded to each other, and when welding is accurately right
Position, makes the electric signal between shell 11 " and substrate 21 " be interconnected, metal cover board 50 " is positioned on shell 11 " and metal
Cover board 50 " is located at the outside of substrate 21 ", is sealed against each other between metal cover board 50 " and shell 11 ", and IO electricity is left on the bottom plate of shell 11 "
Signaling interface.
Sole plate metal figure 102, side-wall metallic piece 103, substrate metal piece 202 are made of gold, and electroplate respectively
On bottom plate, side wall and substrate, shell 11 " and metal cover board 50 " are welded to each other by parallel soldering and sealing or soldering, allow whole system shape
Into the encapsulation of an air-tightness.
Optical detection chip 403 is mounted on substrate 21 ", and the signal interconnection of optical detection chip 403 and substrate 21 " passes through
Wire bonding realizes that MEMS driving chips 401 are welded on the bottom of shell 11 " by way of flip chip bonding (flip chip), senses
Device chip 402 is assembled to form interconnected relationship again by the form of flip chip bonding (flip chip) with MEMS driving chips 401.
Apply specific case in the utility model to be set forth the principle and embodiment of the utility model, the above
The explanation of embodiment is only intended to help the method and its core concept for understanding the utility model；Meanwhile for the one of this area
As technical staff, according to the thought of the utility model, in specific embodiments and applications there will be changes.To sum up
Described, this specification content should not be construed as the limitation to the utility model.
Claims (8)
- A kind of 1. package carrier three-dimensionally integrated for SIP, it is characterised in that：Including shell (11,11 "), substrate (21,21 "), Metal cover board (50,50 "), the substrate (21,21 ") are arranged on the shell (11,11 "), and the substrate (21, 21 ") formed between the shell (11,11 ") and be used to accommodating the cavity of chip, the shell (11,11 "), substrate (21, 21 ") non-conducting material is used, and the electric signal between the shell (11,11 ") and substrate (21,21 ") is interconnected, The metal cover board (50,50 ") is positioned on the shell (11,11 ") and the metal cover board (50,50 ") is positioned at described On the outside of substrate (21,21 "), sealed against each other between the metal cover board (50,50 ") and the shell (11,11 ").
- 2. the package carrier three-dimensionally integrated for SIP according to claim 1, it is characterised in that：The shell (11) and Substrate (21) uses plastic material, and the shell (11) includes bottom plate and side wall, and the plate upper surface sets metal to be made Bottom plate lead frame (10), metal ferrule (12) is set in the side wall, and metal ferrule (12) bottom and the bottom plate draw Wire frame (10) connects, and substrate (21) lower surface sets substrate lead frame (20) made of metal, the metal ferrule (12) Upper end and the substrate lead frame (20) conducting.
- 3. the package carrier three-dimensionally integrated for SIP according to claim 2, it is characterised in that：The substrate (21) Link slot (22) is provided with lower surface, is placed at the top of the metal ferrule (12) in the link slot (22), and the metal Contact pin (12) and the substrate lead frame (20) of the link slot (22) periphery are welded to each other by solder(ing) paste.
- 4. the package carrier three-dimensionally integrated for SIP according to claim 3, it is characterised in that：The substrate lead frame (20), bottom plate lead frame (10) is made by copper alloy.
- 5. the package carrier three-dimensionally integrated for SIP according to claim 1, it is characterised in that：The shell (11 ") and Substrate (21 ") uses ceramic material, and the shell (11 ") includes bottom plate and side wall, and the plate upper surface sets bottom plate gold Belong to figure (102), the top side wall sets side-wall metallic piece (103), and substrate (the 21 ") lower surface sets substrate metal piece (202), the side-wall metallic piece (103) and the substrate metal piece (202) are welded to each other.
- 6. the package carrier three-dimensionally integrated for SIP according to claim 5, it is characterised in that：The sole plate metal figure Shape (102), side-wall metallic piece (103), substrate metal piece (202) are made of gold, and electroplate respectively in the bottom plate, side wall And on substrate.
- 7. the package carrier three-dimensionally integrated for SIP according to claim 6, it is characterised in that：The shell (11 ") and The metal cover board (50 ") is welded to each other by parallel soldering and sealing or soldering.
- 8. the package carrier three-dimensionally integrated for SIP according to claim 1, it is characterised in that：The shell (11, 11 ") electric signal interface is left on bottom plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720849124.6U CN207330353U (en) | 2017-07-13 | 2017-07-13 | The package carrier three-dimensionally integrated for SIP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720849124.6U CN207330353U (en) | 2017-07-13 | 2017-07-13 | The package carrier three-dimensionally integrated for SIP |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207330353U true CN207330353U (en) | 2018-05-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720849124.6U Expired - Fee Related CN207330353U (en) | 2017-07-13 | 2017-07-13 | The package carrier three-dimensionally integrated for SIP |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207330353U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107324274A (en) * | 2017-07-13 | 2017-11-07 | 中国工程物理研究院电子工程研究所 | The package carrier three-dimensionally integrated for SIP |
-
2017
- 2017-07-13 CN CN201720849124.6U patent/CN207330353U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107324274A (en) * | 2017-07-13 | 2017-11-07 | 中国工程物理研究院电子工程研究所 | The package carrier three-dimensionally integrated for SIP |
| CN107324274B (en) * | 2017-07-13 | 2024-04-05 | 中国工程物理研究院电子工程研究所 | Encapsulation carrier for SIP three-dimensional integration |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180508 Termination date: 20210713 |