CN207303112U

CN207303112U - Thin film transistor (TFT), array base palte and display device

Info

Publication number: CN207303112U
Application number: CN201721391865.0U
Authority: CN
Inventors: 李磊; 樊君; 李付强; 刘泰洋
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2017-10-26
Filing date: 2017-10-26
Publication date: 2018-05-01
Anticipated expiration: 2027-10-26

Abstract

The utility model discloses a kind of thin film transistor (TFT), array base palte and display device, belong to display technology field.Thin film transistor (TFT) includes：Gate patterns, active layer pattern and the gate insulation layer between gate patterns and active layer pattern；Thin film transistor (TFT) further includes：First conductive pattern, the second conductive pattern and the first intermediate insulating layer between the first conductive pattern and the second conductive pattern；Wherein, the first conductive pattern and the second conductive pattern are respectively source electrode figure and drain patterns；The first via is provided with first intermediate insulating layer, the second conductive pattern is connected by the first via with active layer pattern.By setting the first intermediate insulating layer between source electrode figure and drain patterns, it effectively prevent source electrode and the phenomenon of short circuit occur with drain electrode.The utility model is used in display device.

Description

Thin film transistor (TFT), array base palte and display device

Technical field

Display technology field is the utility model is related to, more particularly to a kind of thin film transistor (TFT), array base palte and display device.

Background technology

With the development of display technology field, the various products with display function occur in daily life, such as hand Machine, tablet computer, television set, laptop, Digital Frame, navigator, virtual reality (English：Virtual Reality； Referred to as：VR) etc., these products all without exception need assemble display panel.

At present, most of display panel can include array base palte, color membrane substrates and positioned at array base palte and color film base Liquid crystal layer between plate, array base palte includes underlay substrate and the multiple films for the array arrangement being formed on underlay substrate are brilliant Body pipe (English：Thin Film Transistor；Abbreviation TFT).For VR products, in order not to influence the 3D of VR (English： Three-Dimensional) display effect is, it is necessary to improve the number of pixels (English of the per inch in array base palte：Pixels Per Inch；Referred to as：PPI), can be by reducing the distance between source electrode and drain electrode in TFT, and then reduce the size of pixel, So as to improve the PPI of array base palte.

But if the distance between source electrode in TFT and drain electrode are too small, when forming the source electrode with drain electrode, source electrode with Drain easy short circuit, causes corresponding TFT short circuit, therefore product easily occur bad by the TFT generated.

Utility model content

This application provides a kind of thin film transistor (TFT), array base palte and display device, the TFT of existing generation can be solved Easily there is the bad problem of product.The technical solution is as follows：

First aspect, there is provided a kind of thin film transistor (TFT), including：

Gate patterns, active layer pattern and the gate insulation layer between the gate patterns and the active layer pattern；

The thin film transistor (TFT) further includes：First conductive pattern, the second conductive pattern and positioned at first conductive pattern The first intermediate insulating layer between second conductive pattern；

Wherein, first conductive pattern and second conductive pattern are respectively source electrode figure and drain patterns；

Be provided with the first via on first intermediate insulating layer, second conductive pattern by first via with The active layer pattern connection.

Optionally, the thin film transistor (TFT) further includes：Second intermediate insulating layer；

The active layer pattern, the gate insulation layer, the gate patterns, second intermediate insulating layer, described first Conductive pattern, first intermediate insulating layer and second conductive pattern are sequentially overlapped setting；

The second via and the 3rd via are provided with second intermediate insulating layer, first conductive pattern passes through described Second via is connected with the active layer pattern, and second conductive pattern passes sequentially through first via and the 3rd mistake Hole is connected with the active layer pattern.

Optionally, the 4th via and the 5th via are provided with the gate insulation layer,

First conductive pattern passes sequentially through second via and the 4th via and connects with the active layer pattern Connect, second conductive pattern pass sequentially through first via, the 3rd via and the 5th via with it is described active Layer pattern connects.

Optionally, the gate patterns, gate insulation layer, the active layer pattern, first conductive pattern, described First intermediate insulating layer and second conductive pattern are sequentially overlapped setting.

Second aspect, there is provided a kind of manufacture method of thin film transistor (TFT), the described method includes：

Gate patterns, active layer pattern, gate insulation layer, the first conductive pattern, the second conductive pattern are formed on underlay substrate Shape and the first intermediate insulating layer；

Wherein, the gate insulation layer is between the gate patterns and the active layer pattern, among described first absolutely Edge layer is between first conductive pattern and second conductive pattern；

First conductive pattern and second conductive pattern are respectively source electrode figure and drain patterns；

Optionally, it is described on underlay substrate formed gate patterns, active layer pattern, gate insulation layer, the first conductive pattern, Second conductive pattern and the first intermediate insulating layer, including：

The active layer pattern, the gate insulation layer, the gate patterns, second are sequentially formed on the underlay substrate Intermediate insulating layer, first conductive pattern, first intermediate insulating layer and second conductive pattern；

Wherein, the second via and the 3rd via are provided with second intermediate insulating layer, first conductive pattern leads to Cross second via to be connected with the active layer pattern, second conductive pattern passes sequentially through first via and described 3rd via is connected with the active layer pattern；

Alternatively, the gate patterns, the gate insulation layer, the active layer figure are sequentially formed on the underlay substrate Shape, first conductive pattern, first intermediate insulating layer and second conductive pattern.

The third aspect, there is provided a kind of array base palte, including：

Underlay substrate；

Thin film transistor (TFT) and pixel electrode figure are disposed with the underlay substrate, the thin film transistor (TFT) is first Thin film transistor (TFT) described in aspect；

The pixel electrode figure is electrically connected with one of first conductive pattern and second conductive pattern.

Optionally, the array base palte further includes：The flatness layer set on the thin film transistor (TFT)；

The 6th via is provided with the flatness layer, the pixel electrode figure passes through the 6th via and described first One of conductive pattern and second conductive pattern are electrically connected.

Optionally, the array base palte further includes：Shading layer pattern, which eases up, rushes layer；

The shading layer pattern, the cushion and the thin film transistor (TFT) are sequentially overlapped setting；

Wherein, the thin film transistor (TFT) further includes：Second intermediate insulating layer, the active layer pattern, the gate insulation layer, The gate patterns, second intermediate insulating layer, first conductive pattern, first intermediate insulating layer and described second Conductive pattern is sequentially overlapped setting.

Optionally, the source electrode figure includes source electrode, and the drain patterns includes drain electrode,

Orthographic projection of the source electrode on the underlay substrate and the orthographic projection of the drain electrode on the underlay substrate it Between gap be 0, and orthographic projection of the source electrode on the underlay substrate with it is described drain electrode on the underlay substrate just Overlapping region is not present in projection.

Optionally, the array base palte further includes：The passivation layer and public electrode set on the pixel electrode figure Figure.

Fourth aspect, there is provided a kind of manufacture method of array base palte, the described method includes：

Thin film transistor (TFT) is formed on underlay substrate；

Pixel electrode figure is formed on the thin film transistor (TFT)；

Wherein, the thin film transistor (TFT) includes：

Be provided with the first via on first intermediate insulating layer, second conductive pattern by first via with The active layer pattern connection；

Optionally, the thin film transistor (TFT) further includes：Second intermediate insulating layer, the active layer pattern, the gate insulation Layer, the gate patterns, second intermediate insulating layer, first conductive pattern, first intermediate insulating layer and described Second conductive pattern is sequentially overlapped setting,

Formed on underlay substrate before thin film transistor (TFT), the method further includes：

Shading layer pattern is sequentially formed on the underlay substrate ease up and rush layer.

Optionally, the formation pixel electrode figure on the thin film transistor (TFT), including：

Flatness layer is formed on the thin film transistor (TFT)；

Pixel electrode figure is formed on the flatness layer；

Wherein, the 6th via is provided with the flatness layer, the pixel electrode figure passes through the 6th via and institute State the electrical connection of one of the first conductive pattern and second conductive pattern.

5th aspect, there is provided a kind of display device, including：Array base palte described in the third aspect.

The beneficial effect brought of technical solution that the utility model embodiment provides is：

Thin film transistor (TFT), array base palte and the display device that the utility model embodiment provides, due in the first conductive pattern First intermediate insulating layer is set between shape and the second conductive pattern, and first conductive pattern and the second conductive pattern are respectively source electrode Figure and drain patterns, therefore the source electrode figure and drain patterns are formed by patterning processes twice, and then avoid existing When some forms source electrode with drain electrode by a patterning processes, since source electrode and the distance between drain electrode are too small, cause the source electrode There is the phenomenon of short circuit with drain electrode, and then effectively raise the product yield of TFT.And source electrode and drain electrode appearance are short avoiding It on the premise of connecing phenomenon, can effectively reduce the distance between source electrode and drain electrode, and then the PPI of array base palte can be improved, Effectively avoiding the display device being subsequently formed there is the phenomenon of dim spot at the same time.

Brief description of the drawings

It is required in being described below to embodiment in order to illustrate more clearly of the technical scheme in the embodiment of the utility model Attached drawing to be used is briefly described, it should be apparent that, drawings in the following description are only some realities of the utility model Example is applied, for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings Obtain other attached drawings.

Fig. 1 is a kind of structure diagram for array base palte that the prior art provides；

Fig. 2-1 is a kind of top view for TFT that the utility model embodiment provides；

Fig. 2-2 is sectional views of the Fig. 2-1 at B-B ' places；

Fig. 3-1 is the top view for another TFT that the utility model embodiment provides；

Fig. 3-2 is sectional views of the Fig. 3-1 at C-C ' places；

Fig. 4-1 is the top view for another TFT that the utility model embodiment provides；

Fig. 4-2 is sectional views of the 4-1 at B-B ' places；

Fig. 5 is a kind of manufacture method flow chart for TFT that the utility model embodiment provides；

Fig. 6 is the manufacture method flow chart for another TFT that the utility model embodiment provides；

Fig. 7-1 is a kind of top view for array base palte that the utility model embodiment provides；

Fig. 7-2 is the sectional view at D-D ' places in Fig. 7-1；

Fig. 8-1 is the top view for another array base palte that the utility model embodiment provides；

Fig. 8-2 is the sectional view at D-D ' places in Fig. 8-1；

Fig. 8-3 is the sectional view at E-E ' places in Fig. 8-1；

Fig. 9-1 is a kind of top view for array base palte that the prior art provides；

Fig. 9-2 is the sectional view at F-F ' places in Fig. 9-1；

Fig. 9-3 is the top view for another array base palte that the prior art provides；

Fig. 9-4 is the sectional view at F-F ' places in Fig. 9-3；

Fig. 9-5 is the design sketch that the phenomenon that via does not penetrate occurs in via in the prior art；

Figure 10 is the structure diagram that the utility model embodiment provides another array base palte；

Figure 11 is a kind of flow chart of the manufacture method for array base palte that the utility model embodiment provides；

Figure 12 is the flow chart of the manufacture method for another array base palte that the utility model embodiment provides.

Embodiment

It is new to this practicality below in conjunction with attached drawing to make the purpose of this utility model, technical solution and advantage clearer Type embodiment is described in further detail.

Please refer to Fig.1, Fig. 1 is a kind of structure diagram for array base palte that the prior art provides, which can With including：Glass substrate 01, the shading layer pattern 02 set gradually on glass substrate 01, cushion 03, active layer pattern 04, Gate insulation layer 05, gate patterns 06, intermediate insulating layer 07, source-drain electrode figure 08, flatness layer 09, pixel electrode figure 010, passivation Layer 011 and common pattern of electrodes 012.When needing to improve the PPI of the array base palte 00, can reduce in source-drain electrode figure 08 The distance between source electrode 08a and drain electrode 08b d0.

Under normal conditions, source electrode 08a and drain electrode 08b is by carrying out one to the source and drain very thin films on intermediate insulating layer 07 What secondary patterning processes processing was formed, which can include photoresist coating, exposure, development, etching and photoresist Peel off.Due to being influenced be subject to existing process, if the distance between source electrode 08a and drain electrode 08b d0 are too small, due to source electrode 08a and drain electrode 08b is made of using metal material, in the source electrode for carrying out being formed after the processing of patterning processes to source and drain very thin films 08a and drain electrode 08b between may there are metal residual, therefore source electrode 08a with drain electrode the easy short circuits of 08b, cause corresponding TFT short circuits, it is bad that product easily occurs in the TFT of generation.

The utility model provides a kind of TFT, can improve the product yield of TFT, please refers to Fig.2-1 and Fig. 2-2, and Fig. 2- 1 is a kind of top view for TFT that the utility model embodiment provides, and Fig. 2-2 is sectional views of the Fig. 2-1 at B-B ' places.

The TFT 10 can include：Gate patterns 11, active layer pattern 12 and positioned at the gate patterns 11 and active layer figure Gate insulation layer 13 between shape 12.

The TFT 10 can also include：First conductive pattern 14, the second conductive pattern 15 and positioned at the first conductive pattern 14 And second the first intermediate insulating layer 16 between conductive pattern 15.

Wherein, which is respectively source electrode figure and drain patterns.It that is to say, First conductive pattern 14 is source electrode figure, and the second conductive pattern 15 is drain patterns；Alternatively, the first conductive pattern 14 is schemed for drain electrode Shape, the second conductive pattern 15 are source electrode figure.The first via 161, the second conductive pattern are provided with first intermediate insulating layer 16 Shape 15 is connected by the first via 161 with active layer pattern 12.

In conclusion the TFT that the utility model embodiment provides, due to the first conductive pattern and the second conductive pattern it Between the first intermediate insulating layer is set, first conductive pattern and the second conductive pattern are respectively source electrode figure and drain patterns, because This source electrode figure and drain patterns are formed by patterning processes twice, and then are avoided existing by a composition work When skill forms source electrode with drain electrode, since source electrode and the distance between drain electrode are too small, the source electrode is caused showing for short circuit occur with drain electrode As so as to effectively raise the product yield of TFT.

In practical application, since the TFT can be top gate type TFT, or bottom gate type TFT, therefore the utility model Embodiment by it is following two it is achievable in a manner of exemplified by schematically illustrated：

In the first can realize mode, when the TFT is top gate type TFT ,-1 and Fig. 3-2 are please referred to Fig.3, Fig. 3-1 is The top view for another TFT that the utility model embodiment provides, Fig. 3-2 is sectional views of the Fig. 3-1 at C-C ' places.The TFT 10 It can also include：Second intermediate insulating layer 17, active layer pattern 12, gate insulation layer 13, gate patterns 11 in the TFT 10, Two intermediate insulating layers 17, the first conductive pattern 14, the first intermediate insulating layer 16 and the second conductive pattern 15 are sequentially overlapped setting.Should The second via 171 and the 3rd via 172 are provided with second intermediate insulating layer 17, at this time, the first conductive pattern 14 passes through second Via 171 is connected with active layer pattern 12, and the second conductive pattern 15 passes sequentially through the first via 161 and the 3rd via 172 with having Active layer figure 12 connects.

Optionally, when gate insulation layer 13 can be flood structure, as shown in Fig. 3-1 and Fig. 3-2, on the gate insulation layer 13 The 4th via 131 and the 5th via 132 can be provided with, at this time, the first conductive pattern 14 passes sequentially through the second via 171 and Four vias 131 are connected with active layer pattern 12, and the second conductive pattern 15 passes sequentially through the first via 161, the 3rd via 172 and Five vias 132 are connected with active layer pattern.Optionally, as shown in figure 3-1, the first via 161, the 3rd via 172 and the 5th mistake The orthographic projection of hole 132 vertically is overlapping, and the orthographic projection of 171 and the 4th via 131 of the second via vertically is overlapping, The vertical direction is the stacked direction of each Rotating fields of the TFT, such as the direction in Fig. 3-1 perpendicular to paper.

In second can be achieved mode, when the TFT is bottom gate type TFT ,-1 and Fig. 4-2 are please referred to Fig.4, Fig. 4-1 is The top view for another TFT that the utility model embodiment provides, Fig. 4-2 is sectional views of the 4-1 at B-B ' places.In the TFT 10 Gate patterns 11, gate insulation layer 13, active layer pattern 12, the first conductive pattern 14, the first intermediate insulating layer 16 and second lead Electrograph shape 15 is sequentially overlapped setting.

In conclusion the TFT that the utility model embodiment provides, due to the first conductive pattern and the second conductive pattern it Between the first intermediate insulating layer is set, first conductive pattern and the second conductive pattern are respectively source electrode figure and drain patterns, because This source electrode figure and drain patterns are formed by patterning processes twice, and then are avoided existing by a composition work When skill forms source electrode with drain electrode, since source electrode and the distance between drain electrode are too small, the source electrode is caused showing for short circuit occur with drain electrode As, and then effectively raise the product yield of TFT.

The utility model embodiment additionally provides a kind of manufacture method of TFT, and this method can include：

Gate patterns, active layer pattern, gate insulation layer, the first conductive pattern, the second conductive pattern are formed on underlay substrate Shape and the first intermediate insulating layer.

Wherein, for gate insulation layer between gate patterns and active layer pattern, the first intermediate insulating layer is conductive positioned at first Between figure and the second conductive pattern；First conductive pattern and the second conductive pattern are respectively source electrode figure and drain patterns；The The first via is provided with one intermediate insulating layer, the second conductive pattern is connected by the first via with active layer pattern.

In conclusion the manufacture method for the TFT that the utility model embodiment provides, due in the first conductive pattern and second First intermediate insulating layer is set between conductive pattern, and first conductive pattern and the second conductive pattern are respectively source electrode figure and leakage Pole figure shape, therefore the source electrode figure and drain patterns are formed by patterning processes twice, and then avoid existing pass through When patterning processes form source electrode with drain electrode, since source electrode and the distance between drain electrode are too small, cause the source electrode with draining out The phenomenon of existing short circuit, and then effectively raise the product yield of TFT.

In practical application, since the TFT can be top gate type TFT, or bottom gate type TFT, therefore the utility model Embodiment provide TFT manufacture method it is also different, the utility model embodiment by it is following two it is achievable in a manner of exemplified by carry out Schematically illustrate：

In the first can realize mode, when the TFT is top gate type TFT, the manufacture method of the TFT can include： Active layer figure, gate insulation layer, gate patterns, the second intermediate insulating layer, the first conductive pattern, are sequentially formed on underlay substrate One intermediate insulating layer and the second conductive pattern.Wherein, in order to allow the first conductive pattern to be connected with active layer pattern, Yi Ji Two conductive patterns can be connected with active layer pattern, and the first via, the second intermediate insulation are provided with first intermediate insulating layer The second via and the 3rd via are provided with layer, when gate insulation layer is flood structure, the can be provided with the gate insulation layer Four vias and the 5th via so that first conductive pattern can pass sequentially through the second via and the 4th via and active layer pattern Connection, the second conductive pattern can pass sequentially through the first via, the 3rd via and the 5th via and be connected with active layer pattern.At this In the manufacturing process of TFT, by taking the second conductive pattern is connected with active layer pattern as an example, can while gate insulation layer is formed shape Into the 5th via, the 4th via is then formed while the second intermediate insulating layer is formed, is finally forming the first intermediate insulation The first via is formed while layer, that is to say, the insulating layer in TFT is simultaneously formed with corresponding via；Can also first according to Secondary formation gate insulation layer, the second intermediate insulating layer and the first intermediate insulating layer, then sequentially form the first via, the 3rd via and 5th via, that is to say, all insulating layers being initially formed in TFT, then form corresponding via on each insulating layer respectively.With Lower embodiment is to be initially formed all insulating layers in TFT, then is formed exemplified by corresponding via and is shown on the insulating layer respectively What meaning property illustrated.

It is exemplary, Fig. 5 is refer to, Fig. 5 is a kind of manufacture method flow chart for TFT that the utility model embodiment provides, The structure of the TFT manufactured by this method may be referred to Fig. 3-2, and this method can include：

Step 501, form active layer pattern on underlay substrate.

Optionally, the material of the active layer pattern can be non-crystalline silicon or polysilicon etc..

It is exemplary, can on underlay substrate by deposit, apply, sputter etc. any of various ways formed it is active Layer film, then performs a patterning processes to the active layer film and forms active layer pattern, which can wrap Include：Photoresist coating, exposure, development, etching and photoresist lift off.

Step 502, form gate insulation layer in active layer pattern.

Optionally, the material of the gate insulation layer can be the mixed of silica, silicon nitride or silica and silicon nitride Condensation material.

It is exemplary, can be on the underlay substrate formed with active layer pattern by depositing, applying, the various ways such as sputtering Any of formed gate insulation layer.

Step 503, form gate patterns on gate insulation layer.

Optionally, which can be formed using metal material, for example, gate patterns are using metal molybdenum (abbreviation： Mo), metallic copper (abbreviation：Cu), metallic aluminium (abbreviation：Al) or alloy material is fabricated.

It is exemplary, can be on the underlay substrate formed with gate insulation layer by depositing, applying, sputtering etc. in various ways Any formation grid film, patterning processes then are performed to the grid film and form gate patterns, a composition Technique can include：Photoresist coating, exposure, development, etching and photoresist lift off.

Step 504, form the second intermediate insulating layer on gate patterns.

Optionally, the material of second intermediate insulating layer can be silica, silicon nitride or silica and nitridation The mixing material of silicon.

It is exemplary, can be on the underlay substrate formed with gate patterns by depositing, applying, sputtering etc. in various ways The second intermediate insulating layer of any formation.

Step 505, form the first conductive pattern on the second intermediate insulating layer.

Optionally, which can be source electrode figure, which can use metal material shape Into for example, gate patterns are fabricated using metal Mo, Ni metal, metal Al or alloy material.

It is exemplary, can on the underlay substrate formed with the second intermediate insulating layer by deposit, apply, sputter etc. it is a variety of Any of mode forms the first conductive film, and a patterning processes formation first is then performed to first conductive film and is led Electrograph shape, a patterning processes can include：Photoresist coating, exposure, development, etching and photoresist lift off.

In the utility model embodiment, in order to make the first conductive pattern be connected with active layer pattern, step 505 it Before, a patterning processes can be performed to the second intermediate insulating layer, and then the second mistake can be formed on the second intermediate insulating layer Hole so that first conductive pattern can be connected by the second via with active layer pattern.If gate insulation layer is flood structure, For example, when needing to be formed the TFT shown in Fig. 3-2, before step 505, a structure can be performed to the second intermediate insulating layer Figure technique, and increase the etch period in this patterning processes, and then the second via can be formed on the second intermediate insulating layer Afterwards, the 4th via is formed on gate insulation layer, at this time, which can pass sequentially through the second via and the 4th via It is connected with active layer pattern.

Step 506, form the first intermediate insulating layer on the first conductive pattern.

Optionally, the material of first intermediate insulating layer can be silica, silicon nitride or silica and nitridation The mixing material of silicon.

It is exemplary, can be on the underlay substrate formed with the first conductive pattern by depositing, applying, a variety of sides such as sputtering Any of formula forms the first intermediate insulating layer.

Step 507, form the second conductive pattern on the first intermediate insulating layer.

Optionally, which can be drain patterns, which can use metal material shape Into for example, gate patterns are fabricated using metal Mo, Ni metal, metal Al or alloy material.

It is exemplary, can on the underlay substrate formed with the first intermediate insulating layer by deposit, apply, sputter etc. it is a variety of Any of mode forms the second conductive film, and a patterning processes formation second is then performed to second conductive film and is led Electrograph shape, a patterning processes can include：Photoresist coating, exposure, development, etching and photoresist lift off.

In the utility model embodiment, in order to make the second conductive pattern be connected with active layer pattern, step 507 it Before, a patterning processes can be performed to the first intermediate insulating layer, and then first can form first on the first intermediate insulating layer Via, is then forming the 3rd via so that second conductive pattern can pass sequentially through the first mistake on two intermediate insulating layers Hole and the 3rd via are connected with active layer pattern.If gate insulation layer is flood structure, for example, being shown when need to form Fig. 3-2 TFT when, before step 507, a patterning processes can be performed to the first intermediate insulating layer, and increase this patterning processes In etch period, and then the first via can be first formed on the first intermediate insulating layer, then on two intermediate insulating layers The 3rd via is formed, the 5th via is finally formed on gate insulation layer, at this time, which can pass sequentially through first Via, the 3rd via and the 5th via are connected with active layer pattern.

In second can be achieved mode, when the TFT is bottom gate type TFT, the manufacture method of the TFT can include： Sequentially formed on underlay substrate gate patterns, gate insulation layer, active layer pattern, the first conductive pattern, the first intermediate insulating layer and Second conductive pattern.

It is exemplary, Fig. 6 is refer to, Fig. 6 is the manufacture method flow for another TFT that the utility model embodiment provides Figure, the structure of the TFT manufactured by this method may be referred to Fig. 4-2, and this method can include：

Step 601, form gate patterns on underlay substrate.

The step 601 may be referred to the corresponding process in abovementioned steps 503, and the utility model embodiment is no longer superfluous herein State.

Step 602, form gate insulation layer on gate patterns.

The step 602 may be referred to the corresponding process in abovementioned steps 502, and the utility model embodiment is no longer superfluous herein State.

Step 603, form active layer pattern on gate insulation layer.

The step 603 may be referred to the corresponding process in abovementioned steps 501, and the utility model embodiment is no longer superfluous herein State.

Step 604, form the first conductive pattern in active layer pattern.

The step 604 may be referred to the corresponding process in abovementioned steps 505, and the utility model embodiment is no longer superfluous herein State.

Step 605, form the first intermediate insulating layer on the first conductive pattern.

The step 605 may be referred to the corresponding process in abovementioned steps 506, and the utility model embodiment is no longer superfluous herein State.

Step 606, form the second conductive pattern on the first intermediate insulating layer.

The step 606 may be referred to the corresponding process in abovementioned steps 507, and the utility model embodiment is no longer superfluous herein State.

, can be in step 606 in order to make the second conductive pattern be connected with active layer pattern in the utility model embodiment Before, a patterning processes are performed to the first intermediate insulating layer, and then the first via can be formed on the first intermediate insulating layer, Second conductive pattern is connected by the first via with active layer pattern.

It is apparent to those skilled in the art that for convenience and simplicity of description, the TFT's of foregoing description Concrete principle, may be referred to the corresponding content in the embodiment of foregoing TFT, details are not described herein.

The utility model embodiment also provides a kind of array base palte, and as shown in Fig. 7-1 and Fig. 7-2, Fig. 7-1 is that this practicality is new A kind of top view for array base palte that type embodiment provides, Fig. 7-2 is the sectional view at D-D ' places in Fig. 7-1, the array base palte 20 It can include：Underlay substrate 21；TFT and pixel electrode figure 22 are disposed with the underlay substrate 21.Need what is illustrated It is that the utility model embodiment is schematically illustrated so that the TFT in array base palte 20 is the TFT shown in Fig. 3-2 as an example, In practical application, which can also be the TFT shown in Fig. 2-2 or Fig. 4-2, and the TFT shown in the Fig. 2-2 or Fig. 4-2 is formed The structure of array base palte it is similar with the structure of the array base paltes formed of the TFT shown in Fig. 3-2, the utility model embodiment pair This is repeated no more.

The pixel electrode 22 is electrically connected with one of the first conductive pattern 14 and the second conductive pattern 15, and following embodiments are Schematically illustrated so that pixel electrode 22 is electrically connected with the first conductive pattern 14 as an example, led for pixel electrode 22 and second The situation that electrograph shape 15 is electrically connected does not repeat.

Optionally, the first conductive pattern 14 can include：Source electrode 141, the second conductive pattern 15 can include：Drain electrode 151.

It should be noted that the array base palte shown in Fig. 7-1 illustrate only source electrode in the TFT in array base palte, drain electrode, The structure of grid and active layer, other structures (for example, pixel electrode) are not shown, and Fig. 7-1 shows three pixels 30, often One TFT is set in a pixel 30.

In the prior art, in order to avoid there is the phenomenon of short circuit between source electrode in TFT and drain electrode, when designing TFT, need Consider the critical distance between source electrode and drain electrode.And in the utility model embodiment, led in the first conductive pattern and second The first intermediate insulating layer is provided between electrograph shape, therefore first conductive pattern and the second conductive pattern are by composition twice What technique was formed, without considering the critical distance between source electrode and drain electrode, source electrode can avoided short circuit occur with drain electrode Phenomenon, therefore the smaller that the distance between the source electrode and drain electrode can design, and then can be designed that the array with higher PPI Substrate.

In conclusion the array base palte that the utility model embodiment provides, due to conductive in the first conductive pattern and second First intermediate insulating layer is set between figure, and first conductive pattern and the second conductive pattern are respectively source electrode figure and drain electrode figure Shape, therefore the source electrode figure and drain patterns are formed by patterning processes twice, and then avoid existing by once When patterning processes form source electrode with drain electrode, since source electrode and the distance between drain electrode are too small, the source electrode is caused to occur with drain electrode short The phenomenon connect, and then effectively raise the product yield of TFT.And there is the premise of short circuit phenomenon with drain electrode avoiding source electrode Under, it can effectively reduce the distance between source electrode and drain electrode, and then the PPI of array base palte can be improved.

Optionally, Fig. 8-1 and Fig. 8-2 are refer to, Fig. 8-1 is another array base palte that the utility model embodiment provides Top view, Fig. 8-2 is the sectional view at D-D ' places in Fig. 8-1, which can also include：What is set on TFT is flat Smooth layer 23；The 6th via 231 is provided with the flatness layer 23, pixel electrode figure 22 can pass through the 6th via 231 and first Conductive pattern 14 is electrically connected.In practical application, the 7th via 162 is also provided with the first intermediate insulating layer 16 in TFT, Pixel electrode figure 22 can pass sequentially through the 6th via 231 and the 7th via 162 is electrically connected with the first conductive pattern 14.Need Illustrate, the array base palte shown in Fig. 8-1 illustrate only source electrode, drain electrode, grid and active layer in the TFT in array base palte Structure, other structures (for example, pixel electrode and flatness layer etc.) are not shown.

Optionally, Fig. 8-2 and Fig. 8-3 are refer to, Fig. 8-3 is the sectional view at E-E ' places in Fig. 8-1, for top gate type TFT For, when light is injected in array base palte 20 by underlay substrate 21, gate patterns 11, which can not hide, plays active layer pattern 12 To interception, in order to avoid the threshold voltage of TFT produces very serious drift, it is necessary to set light-shielding structure, therefore the battle array Row substrate 20 can also include：Shading layer pattern 24 and cushion 25, the shading layer pattern 24, cushion 25 and TFT are folded successively Add and put.

Optionally, as shown in Fig. 8-2 and Fig. 8-3, which can also include：Set on pixel electrode figure 22 Passivation layer 26 and common pattern of electrodes 27.

In the prior art, if drain electrode is connected with the data cable in array base palte, source electrode and the pixel electricity in array base palte Pole connects, and in order to improve the PPI of array base palte, can also reduce the width of source electrode, for example, refer to Fig. 9-1 and Fig. 9-2, schemes 9-1 is a kind of top view for array base palte that the prior art provides, and Fig. 9-2 is the sectional view at F-F ' places in Fig. 9-1, and Fig. 9-1 shows The array base palte gone out illustrate only the structure of source electrode 08a in array base palte, source electrode 08a, grid 06 and active layer pattern 04, its He is not shown structure (for example, pixel electrode), and Fig. 9-2 illustrate only intermediate insulating layer 07, flatness layer 09, source electrode 08a and part The structure of pixel electrode figure 010, other structures are not shown.Via 091 is provided with flatness layer 09, if reducing source electrode 08a Width, in order to ensure can fully to be overlapped between source electrode 08a and pixel electrode figure 010, the width of via 091 can be increased Degree, but at this time pixel electrode figure 010 at a or at b due to there are segment difference, easily there is the risk being broken, causing source electrode Weak overlap joint is formed between 08a and pixel electrode figure 010, finally after display device is formed, it is possible that dim spot phenomenon.

In order to avoid the risk being broken occurs in pixel electrode figure 010, Fig. 9-3 and Fig. 9-4 are refer to, Fig. 9-3 is existing The top view for another array base palte that technology provides, Fig. 9-4 is the sectional view at F-F ' places in Fig. 9-3, can increase source electrode 08a Width, while reduce the width of via 091, not only avoid pixel electrode figure 010 at this time and the risk being broken occur, and It can ensure that the PPI of the array base palte shown in Fig. 9-3 is identical with the PPI of the array base palte shown in Fig. 9-2.But due to via 091 width is too small, when forming the via 091, it is possible that the phenomenon that via does not penetrate, for example, Fig. 9-5 are refer to, Fig. 9-5 is the design sketch that the phenomenon that via does not penetrate occurs in via 091 in the prior art, some is residual for 091 bottom of via 092 is stayed, also results in and weak overlap joint is formed between source electrode 08a and pixel electrode figure 010, finally after display device is formed, It may still occur dim spot phenomenon.

And in the utility model embodiment, as shown in Fig. 8-1 and Fig. 8-2, due to that need not consider source electrode 141 and drain electrode Critical distance between 151, on the premise of the PPI higher of the array base palte 20 is ensured, can increase the width of source electrode 141, And the width of the 6th via 231 in increase flatness layer 23, and then can both ensure to fill between pixel electrode 22 and source electrode 141 Divide overlap joint, turn avoid the 6th via 231 and the non-penetration phenomenon of via occur, so as to effectively avoid the display being subsequently formed There is the phenomenon of dim spot in device.

Optionally, it is the structural representation that the utility model embodiment provides another array base palte to please refer to Fig.1 0, Figure 10 Figure, the orthographic projection of orthographic projection of the source electrode 141 on underlay substrate 21 in the array base palte 20 and drain electrode on underlay substrate it Between gap be 0, and orthographic projection of the source electrode 141 on underlay substrate 21 with drain electrode 151 orthographic projection on underlay substrate 21 not There are overlapping region, that is to say, source electrode 141 is 0 with drain electrode the distance between 151, at this point it is possible to make the source in array base palte 20 Pole 141 reaches minimum with drain electrode the distance between 151, and then the PPI of array base palte 20 can be made to reach maximum.

In conclusion the array base palte that the utility model embodiment provides, due to conductive in the first conductive pattern and second First intermediate insulating layer is set between figure, and first conductive pattern and the second conductive pattern are respectively source electrode figure and drain electrode figure Shape, therefore the source electrode figure and drain patterns are formed by patterning processes twice, and then avoid existing by once When patterning processes form source electrode with drain electrode, since source electrode and the distance between drain electrode are too small, the source electrode is caused to occur with drain electrode short The phenomenon connect, and then effectively raise the product yield of TFT.And there is the premise of short circuit phenomenon with drain electrode avoiding source electrode Under, it can effectively reduce the distance between source electrode and drain electrode, and then the PPI of array base palte can be improved, while effectively keep away There is the phenomenon of dim spot in the display device for having exempted to be subsequently formed.

The utility model embodiment provides a kind of manufacture method of array base palte, and it is this practicality to please refer to Fig.1 1, Figure 11 A kind of flow chart of the manufacture method for array base palte that new embodiment provides, this method can include：

Step 1101, form TFT on underlay substrate.

Step 1102, form pixel electrode figure on TFT.

Wherein, which can include：Gate patterns, active layer pattern and between gate patterns and active layer pattern Gate insulation layer；TFT is further included：First conductive pattern, the second conductive pattern and positioned at the first conductive pattern and the second conductive pattern The first intermediate insulating layer between shape；First conductive pattern and the second conductive pattern are respectively source electrode figure and drain patterns；The The first via is provided with one intermediate insulating layer, the second conductive pattern is connected by the first via with active layer pattern；Pixel electricity Pole figure shape is electrically connected with one of the first conductive pattern and the second conductive pattern.

Please refer to Fig.1 the flow that 2, Figure 12 is the manufacture method for another array base palte that the utility model embodiment provides Figure, this method can include：

Step 1201, on underlay substrate form shading layer pattern successively and ease up and rush layer.

It is exemplary, can be on underlay substrate by depositing, applying, any of the various ways such as sputtering and form shading Layer film, then performs the shading layer film patterning processes and forms shading layer pattern, which can wrap Include：Photoresist coating, exposure, development, etching and photoresist lift off.Pass through again on the underlay substrate formed with shading layer pattern Any of various ways such as deposition, coating, sputtering form cushion.

Step 1202, form TFT on the buffer layer.

The step 1202 may be referred to abovementioned steps 501 to the corresponding process in step 507, the utility model embodiment and exist This is repeated no more.

Step 1203, form flatness layer on TFT.

It is exemplary, can be on the underlay substrate formed with TFT by depositing, applying, the appointing in various ways such as sputtering One kind forms flatness layer.

Step 1204, form pixel electrode figure on flatness layer.

Optionally, the material of the pixel electrode figure can be tin indium oxide (English：Indium Tin Oxide；Referred to as： ITO)。

It is exemplary, can be on the underlay substrate formed with TFT by depositing, applying, the appointing in various ways such as sputtering One kind forms pixel electrode film, and a patterning processes are then performed to the pixel electrode film and form pixel electrode figure, should One time patterning processes can include：Photoresist coating, exposure, development, etching and photoresist lift off.

In the utility model embodiment, in order to make pixel electrode figure be led with the first conductive pattern in TFT and second One of electrograph shape is electrically connected, and before step 1204, can perform a patterning processes to flatness layer, and then can be in flatness layer The 6th via of upper formation so that the pixel electrode figure can be electrically connected by the 6th via with the second conductive pattern in TFT； Alternatively, before step 1204, a patterning processes can be performed to flatness layer, and increased when being etched in this patterning processes Between, and then after the 6th via can be formed on flatness layer, the 7th via is formed on the first intermediate insulating layer in TFT, is made Obtain that the pixel electrode figure can pass sequentially through the 6th via and the 7th via is electrically connected with the first conductive pattern in TFT.

Step 1205, sequentially form passivation layer and common pattern of electrodes on pixel electrode figure.

Optionally, the material of the common pattern of electrodes can be ITO.

It is exemplary, can be on the underlay substrate formed with TFT by depositing, applying, the appointing in various ways such as sputtering One kind forms passivation layer.Again by depositing, applying, the appointing in various ways such as sputtering on the array base palte formed with passivation layer One kind forms public electrode film, and a patterning processes are then performed to the public electrode film and form common pattern of electrodes, should One time patterning processes can include：Photoresist coating, exposure, development, etching and photoresist lift off.

It should be noted that above-mentioned steps 1201 can form the array base palte of top gate type to step 1205, for example, can be with Form the array base palte shown in Fig. 8-2.The utility model embodiment can also form the array base palte of bottom gate type, for example, can be with TFT is formed on underlay substrate, which may be referred to abovementioned steps 601 to the corresponding process in step 606, the utility model Details are not described herein for embodiment；Then above-mentioned steps 1203 are performed to step 1205.

It is apparent to those skilled in the art that for convenience and simplicity of description, the array of foregoing description The concrete principle of substrate, may be referred to the corresponding content in the embodiment of aforementioned array substrate, details are not described herein.

In conclusion the manufacture method for the array base palte that the utility model embodiment provides, due in the first conductive pattern First intermediate insulating layer is set between the second conductive pattern, and first conductive pattern and the second conductive pattern are respectively source electrode figure Shape and drain patterns, therefore the source electrode figure and drain patterns are formed by patterning processes twice, and then avoid existing When forming source electrode with drain electrode by patterning processes, since source electrode and the distance between drain electrode are too small, cause the source electrode and There is the phenomenon of short circuit in drain electrode, and then effectively raises the product yield of TFT.And there is short circuit with drain electrode avoiding source electrode It on the premise of phenomenon, can effectively reduce the distance between source electrode and drain electrode, and then the PPI of array base palte can be improved, together When effectively avoid the display device being subsequently formed and the phenomenon of dim spot occur.

The utility model embodiment additionally provides a kind of display device, the display device can include Fig. 7-2, Fig. 8-2 or Array base palte shown in person Figure 10.The display device can be：Liquid crystal panel, Organic Light Emitting Diode (English：Organic Light-Emitting Diode；Referred to as：OLED) display panel, Electronic Paper, mobile phone, tablet computer, television set, display, pen Remember any product or component with display function such as this computer, Digital Frame, navigator.

One of ordinary skill in the art will appreciate that hardware can be passed through by realizing all or part of step of above-described embodiment To complete, relevant hardware can also be instructed to complete by program, the program can be stored in a kind of computer-readable In storage medium, storage medium mentioned above can be read-only storage, disk or CD etc..

The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all in this practicality Within new spirit and principle, any modification, equivalent replacement, improvement and so on, should be included in the guarantor of the utility model Within the scope of shield.

Claims

A kind of 1. thin film transistor (TFT), it is characterised in that including：

Gate patterns, active layer pattern and the gate insulation layer between the gate patterns and the active layer pattern；

The thin film transistor (TFT) further includes：First conductive pattern, the second conductive pattern and positioned at first conductive pattern and institute State the first intermediate insulating layer between the second conductive pattern；

Wherein, first conductive pattern and second conductive pattern are respectively source electrode figure and drain patterns；

Be provided with the first via on first intermediate insulating layer, second conductive pattern by first via with it is described Active layer pattern connects.
2. thin film transistor (TFT) according to claim 1, it is characterised in that

The thin film transistor (TFT) further includes：Second intermediate insulating layer；

The active layer pattern, the gate insulation layer, the gate patterns, second intermediate insulating layer, first conduction Figure, first intermediate insulating layer and second conductive pattern are sequentially overlapped setting；

The second via and the 3rd via are provided with second intermediate insulating layer, first conductive pattern passes through described second Via is connected with the active layer pattern, second conductive pattern pass sequentially through first via and the 3rd via with The active layer pattern connection.
3. thin film transistor (TFT) according to claim 2, it is characterised in that

The 4th via and the 5th via are provided with the gate insulation layer,

First conductive pattern passes sequentially through second via and the 4th via is connected with the active layer pattern, institute State the second conductive pattern and pass sequentially through first via, the 3rd via and the 5th via and the active layer pattern Connection.
4. thin film transistor (TFT) according to claim 1, it is characterised in that

The gate patterns, the gate insulation layer, the active layer pattern, first conductive pattern, first centre are absolutely Edge layer and second conductive pattern are sequentially overlapped setting.
A kind of 5. array base palte, it is characterised in that including：

Underlay substrate；

Thin film transistor (TFT) and pixel electrode figure are disposed with the underlay substrate, the thin film transistor (TFT) is claim 1 to 4 any thin film transistor (TFT)；

The pixel electrode figure is electrically connected with one of first conductive pattern and second conductive pattern.
6. array base palte according to claim 5, it is characterised in that

The array base palte further includes：The flatness layer set on the thin film transistor (TFT)；

The 6th via is provided with the flatness layer, the pixel electrode figure is conductive with described first by the 6th via One of figure and second conductive pattern are electrically connected.
7. array base palte according to claim 5, it is characterised in that

The array base palte further includes：Shading layer pattern, which eases up, rushes layer；

The shading layer pattern, the cushion and the thin film transistor (TFT) are sequentially overlapped setting；

Wherein, the thin film transistor (TFT) further includes：Second intermediate insulating layer, it is the active layer pattern, the gate insulation layer, described Gate patterns, second intermediate insulating layer, first conductive pattern, first intermediate insulating layer and second conduction Figure is sequentially overlapped setting.
8. array base palte according to claim 5, it is characterised in that

The source electrode figure includes source electrode, and the drain patterns includes drain electrode,

Between the orthographic projection of orthographic projection and the drain electrode on the underlay substrate of the source electrode on the underlay substrate Gap is 0, and orthographic projection of orthographic projection of the source electrode on the underlay substrate with the drain electrode on the underlay substrate There is no overlapping region.
9. according to any array base palte of claim 5 to 8, it is characterised in that

The array base palte further includes：The passivation layer and common pattern of electrodes set on the pixel electrode figure.
A kind of 10. display device, it is characterised in that including：Any array base palte of claim 5 to 9.