CN207217527U - 一种带esd防护功能的mos管 - Google Patents

一种带esd防护功能的mos管 Download PDF

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CN207217527U
CN207217527U CN201721192929.4U CN201721192929U CN207217527U CN 207217527 U CN207217527 U CN 207217527U CN 201721192929 U CN201721192929 U CN 201721192929U CN 207217527 U CN207217527 U CN 207217527U
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黄景扬
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Wide Electronics (dongguan) Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本实用新型提供一种带ESD防护功能的MOS管,包括封装层、MOS芯片、G极焊盘、S极焊盘、D极焊盘,MOS芯片包含G极、S极、D极,G极焊盘、S极焊盘、D极焊盘分别与G极、S极、D极电性连接,封装层内部设置有抗ESD芯片,抗ESD芯片包含芯片正极、芯片负极,芯片正极与G极焊盘电性连接,芯片负极与S极焊盘电性连接。本实用新型设置独特的装配结构,在MOS管内部配置抗ESD芯片,当遇到ESD时,能够吸收ESD,达到抗ESD的功能。其抗ESD芯片配置在MOS管封装前完成,结构简单,更换二极管耐压值即可适用于不同电路的ESD要求,适用性强。

Description

一种带ESD防护功能的MOS管
技术领域
本实用新型涉及半导体技术领域,具体公开了一种带ESD防护功能的MOS管。
背景技术
MOS管指金属-氧化物半导体场效应晶体管,是一种可以广泛使用在模拟电路与数字电路的场效晶体管。MOS管一般属于对静电ESD比较敏感的器件,在应用线路中易受到静电的威胁而损坏。为了防止ESD对器件的损坏,通常是在MOS管芯片内部内置了防ESD的功能。
此类内置了防ESD功能的MOS管芯片价格通常较高,并且材料供应受限,成为MOS管封装领域亟需考虑的问题。
实用新型内容
基于此,有必要针对现有技术问题,提供一种带ESD防护功能的MOS管,设置独特的结构,在MOS管内部配置抗ESD芯片,达到防ESD的功能,其结构简单,适用性强。
为解决现有技术问题,本实用新型公开一种带ESD防护功能的MOS管,包括封装层、MOS芯片、G极焊盘、S极焊盘、D极焊盘,MOS芯片包含G极、S极、D极,G极焊盘、S极焊盘、D极焊盘分别与G极、S极、D极电性连接,封装层内部设置有抗ESD芯片,抗ESD芯片包含芯片正极、芯片负极,芯片正极与G极焊盘电性连接,芯片负极与S极焊盘电性连接。
优选地,抗ESD芯片还包含1号二极管、2号二极管,1号二极管、2号二极管为Zener或TVS二极管,1号二极管包含1号二极管正极、1号二极管负极,2号二极管包含2号二极管正极、2号二极管负极,2号二极管负极与1号二极管正极电性连接,2号二极管正极与1号二极管负极分别与芯片正极、芯片负极电性连接。
优选地,抗ESD芯片为无背金属芯片,抗ESD芯片底部连接一绝缘层连接在D极焊盘上。
优选地,绝缘层为DAF绝缘膜。
优选地,D极设置在MOS芯片的底端,S极、G极分别设置在MOS芯片的顶端一侧;D极通过导电胶电性连接在D极焊盘上。
优选地,抗ESD芯片设置在D极焊盘上靠近G极焊盘一端。
优选地,1号二极管负极搭接在S极上与S极焊盘电性连接。
本实用新型的有益效果为:本实用新型公开一种带ESD防护功能的MOS管,在MOS管内部配置抗ESD芯片,当遇到ESD时,能够吸收ESD,达到抗ESD的功能。其抗ESD芯片配置在MOS管封装前完成,结构简单,更换二极管耐压值即可适用于不同电路的ESD要求,适用性强。
附图说明
图1为本实用新型的MOS管内部结构示意图。
图2为本实用新型的MOS管内部截面示意图。
图3为本实用新型的MOS芯片内部截面示意图。
附图标记为:封装层1、MOS芯片2、G极21、S极22、D极23、G极焊盘3、S极焊盘4、D极焊盘5、抗ESD芯片6、芯片正极61、芯片负极62、1号二极管63、1号二极管正极631、1号二极管负极632、2号二极管64、2号二极管正极641、2号二极管负极642、导电胶7。
具体实施方式
为能进一步了解本实用新型的特征、技术手段以及所达到的具体目的、功能,下面结合附图与具体实施方式对本实用新型作进一步详细描述。
参考图1至图3。
本实用新型实施例公开一种带ESD防护功能的MOS管,包括封装层1、MOS芯片2、G极焊盘3、S极焊盘4、D极焊盘5,MOS芯片2包含G极21、S极22、D极23,G极焊盘3、S极焊盘4、D极焊盘5分别与G极21、S极22、D极23电性连接,封装层1内部设置有抗ESD芯片6,抗ESD芯片6包含芯片正极61、芯片负极62,芯片正极61与G极焊盘3电性连接,芯片负极62与S极焊盘4电性连接。
通过在MOS管内设置抗ESD芯片的结构设计,充分地利用了MOS管内部封装层的空间,当电路中存在ESD时,由于MOS管内连接了抗ESD芯片,ESD在进入MOS芯片前已被抗ESD芯片抵消吸收,达到消除防护ESD的功效。
基于上述实施例,抗ESD芯片6还包含1号二极管63、2号二极管64,1号二极管63、2号二极管64为Zener或TVS二极管,1号二极管63包含1号二极管正极631、1号二极管负极632,2号二极管64包含2号二极管正极641、2号二极管负极642,2号二极管负极642与1号二极管正极631电性连接,2号二极管正极641与1号二极管负极632分别与芯片正极61、芯片负极62电性连接。Zener二极管利用PN结反向击穿状态,其电流可在很大范围内变化而电压基本不变的现象,制成的起稳压作用的二极管,是一种直到临界反向击穿电压前都具有很高电阻的半导体器件;TVS二极管是普遍使用的一种新型高效电路保护器件,它具有极快的响应时间和相当高的浪涌吸收能力,当它的两端经受瞬间的高能量冲击时,TVS二极管能以极高的速度把两端间的阻抗值由高阻抗变为低阻抗,以吸收一个瞬间大电流,把它的两端电压箝制在一个预定的数值上,从而保护后面的电路元件不受瞬态高压尖峰脉冲的冲击。通过将两个Zener二极管串联,可以提高电路的稳压参数;通过将两个TVS二极管串联可以获得更高的箝位电压。
为了让抗ESD芯片与D极焊盘绝缘并具有更好的贴合效果,抗ESD芯片6为无背金属芯片,抗ESD芯片6底部连接一绝缘层65连接在所述D极焊盘5上。无背金属芯片和绝缘层65的设置,防止抗ESD芯片6底部与D极焊盘5导通。
基于上述实施例,绝缘层65为DAF绝缘膜。DAF绝缘膜对于堆叠小型芯片上具有很好的帖附效果。
为了让MOS管结构简单并充分利用MOS管内部空间,基于上述实施例,D极23设置在MOS芯片2的底端,S极22、G极21分别设置在MOS芯片2的顶端一侧;D极23通过导电胶7电性连接在D极焊盘5上。将MOS芯片2的D极23设置在底端,D极23即可直接与D极焊盘5平面接合,并通过导电胶7电性连接,节省MOS管空间。
为了缩短焊线长度,合理配置连接线路,基于上述实施例,抗ESD芯片6设置在D极焊盘5上靠近G极焊盘3一端。1号二极管负极632搭接在S极22上与S极焊盘4电性连接。
以上所述实施例仅表达了本实用新型的1种实施方式,其描述较为具体和详细,但并不能因此而理解为对本实用新型专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本实用新型构思的前提下,还可以做出若干变形和改进,这些都属于本实用新型的保护范围。因此,本实用新型专利的保护范围应以所附权利要求为准。

Claims (8)

1.一种带ESD防护功能的MOS管,包括封装体(1)、MOS芯片(2)、G极焊盘(3)、S极焊盘(4)、D极焊盘(5),所述MOS芯片(2)包含G极(21)、S极(22)、D极(23),所述G极焊盘(3)、S极焊盘(4)、D极焊盘(5)分别与所述G极(21)、S极(22)、D极(23)电性连接,其特征在于,所述封装体(1)内部设置有抗ESD芯片(6),所述抗ESD芯片(6)包含芯片正极(61)、芯片负极(62),所述芯片正极(61)与所述G极焊盘(3)电性连接,所述芯片负极(62)与所述S极焊盘(4)电性连接。
2.根据权利要求1所述的一种带ESD防护功能的MOS管,其特征在于,所述抗ESD芯片(6)包含二极管A(63)、二极管B(64),所述二极管A(63)、二极管B(64)均为Zener二极管,所述二极管A(63)包含二极管A正极(631)、二极管A负极(632),所述二极管B(64)包含二极管B正极(641)、二极管B负极(642),所述二极管B负极(642)与所述二极管A正极(631)电性连接,所述二极管B正极(641)与所述二极管A负极(632)分别与所述芯片正极(61)、芯片负极(62)电性连接。
3.根据权利要求1所述的一种带ESD防护功能的MOS管,其特征在于,所述抗ESD芯片(6)包含二极管A(63)、二极管B(64),所述二极管A(63)、二极管B(64)均为TVS二极管,所述二极管A(63)包含二极管A正极(631)、二极管A负极(632),所述二极管B(64)包含二极管B正极(641)、二极管B负极(642),所述二极管B负极(642)与所述二极管A正极(631)电性连接,所述二极管B正极(641)与所述二极管A负极(632)分别与所述芯片正极(61)、芯片负极(62)电性连接。
4.根据权利要求1所述的一种带ESD防护功能的MOS管,其特征在于,所述抗ESD芯片(6)为无背金属芯片,所述抗ESD芯片(6)底部邻接有一绝缘层(65)设置在所述D极焊盘(5)上。
5.根据权利要求4所述的一种带ESD防护功能的MOS管,其特征在于,所述绝缘层(65)为DAF绝缘膜。
6.根据权利要求1所述的一种带ESD防护功能的MOS管,其特征在于,所述D极(23)设置在MOS芯片(2)的底部,所述S极(22)、G极(21)分别设置在MOS芯片(2)的顶端一侧;所述D极(23)通过导电胶(7)电性连接在所述D极焊盘(5)上。
7.根据权利要求1所述的一种带ESD防护功能的MOS管,其特征在于,所述抗ESD芯片(6)设置在所述D极焊盘(5)上靠近所述G极焊盘(3)一侧。
8.根据权利要求1或2或3所述的一种带ESD防护功能的MOS管,其特征在于,所述二极管A负极(632)搭接在所述S极(22)上与所述S极焊盘(4)电性连接。
CN201721192929.4U 2017-09-18 2017-09-18 一种带esd防护功能的mos管 Expired - Fee Related CN207217527U (zh)

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