CN207097831U - Vertical power mos field effect transistor with planar channeling - Google Patents

Abstract

The utility model discloses a kind of power metal oxide semiconductor field-effect transistor (MOSFET) monomer, including a N+ silicon substrates, it has drain electrode.Low-mix debris concentration N-type drift layer is grown in the thereon.N-type layer with dopant concentrations more highly doped than the drift region is subsequently formed and etched, with side wall.P wells are formed in the N-type layer, and N+ source areas are formed in the P wells.Grid is formed on the lateral raceway groove of the P wells, and has perpendicular extension beside the tip portion of such side wall.Positive gate voltage inverts the lateral raceway groove and improves the conduction along such side wall, to reduce conducting resistance.Vertical screen field plate also is located at beside such side wall, and almost extends the whole length of such side wall.When the device is turns off to improve the breakdown voltage, the field plate laterally exhausts the N-type layer.

Description

Vertical power mos field effect transistor with planar channeling

Technical field

It the utility model is related to power metal oxide semiconductor field-effect transistor (MOSFET), more particularly to a kind of tool There is plane double diffusion metal oxide semiconductor (DMOS) the partly vertical transistor with vertical conduction part.

Background technology

Vertical MOSFET is because providing thick low-mix dopant concentrations drift layer to reach high-breakdown-voltage under the off state Ability, and generally as high voltage, high-capacity transistor.Generally, the MOSFET includes a high doped N-type substrate；One is thick Low-mix debris concentration N-type drift layer；One p-type body layer, it is formed in the drift layer；One N-type source, it is in the body layer Top；And a grid, it is separated by thin gate oxide and the channel region.Source electrode is formed in the top end surface On, and drain electrode is formed on the bottom surface.When the grid relative to the source electrode enough on the occasion of when, between the N-type source and the N The channel region reversion of p-type main body between type drift layer, to establish conducting path between the source electrode and drain electrode.

Under the off state of the device, when the gate short to the source electrode or when being negative value, the drift layer exhausts, and can High-breakdown-voltage (such as more than 600 volts) is kept between the source electrode and drain electrode.However, because of the required thick drift layer low-mix It is miscellaneous, and the conducting resistance is affected.The doping for improving the drift layer reduces the conducting resistance, but reduces the breakdown voltage.

Fig. 1 is the profile of the usual plane vertical DMOS transistor monomer 10 in the array of monomer.Plane DMOS is brilliant Body pipe is widely used in numerous power switching applications because of its durability compared to groove MOSFET.However, this is usual flat Face DMOS transistors have higher specified conducting resistance (Rsp, specific on-resistance), its be conducting resistance with The product of effective area.Required is with reduction Rsp and relatively low input capacitance (Ciss, input capacitances), output Electric capacity (Coss, output capacitances) and transfer electric capacity (Crss, transfer capacitances) OR gate are extremely electric The DMOS transistors of lotus (Qg, gate charge), to reduce the conduction of the transistor and handoff loss.

Important resistor assembly in the usual DMOS structures shown in Fig. 1 can be along inversion channel 12 and in P- Jing16Qu Occur during the voltage drop in junction field effect transistor (JFET) area 14 on side.When enough on the occasion of voltage put on grid 17 When, the inversion channel 12 of grid 17.Source electrode 18 contacts N++ source areas 20 and P- wells 16 by P+ contact areas 22.Dielectric substance 53 Isolated gate 17 and source electrode 18.When 17 inversion channel 12 of grid, in source area 20 and low-mix dopant density N-- drift regions Horizontal current path is formed between 24, then the electric current vertically flows through N-- drift regions 24, N++ substrates 26 and drain electrode 28. N-- drift regions 24 need relatively thick with high-breakdown-voltage, but the low-mix dopant density and thickness of N-- drift regions 24 improve Conducting resistance.

JFET areas 14 limit the electric current flowing, and are divided using sufficiently wide P- wells spacing (2Y) with minimizing the JFET resistance Measure critically important.However, improving spacing Y causes monomer spacing and effective area increase.Therefore, this weigh the advantages and disadvantages causes Rsp improvement is limited.

This area pole need to have good Rsp and compared to Fig. 1 small surface areas to improve the plane of monomer density, vertical DMOS transistors.Also, the transistor should have high-breakdown-voltage and high switch speed.

Utility model content

Disclosed is the brand-new DMOS transistor arrangements with reduction Rsp and gate charge Qg, while has high breakdown potential Pressure and high switch speed.

The MOSFET formed has the planar channeling area for being used for lateral current flowing, and for vertical current flow Vertical conduction path.In a specific embodiment, P- wells (body zone) are formed in N-type layer, wherein having more deeper than the P- wells Groove formed in the N-type layer, produce the vertical sidewall of the N-type layer.The N-type layer is than the N-type drift layer below the N-type layer more High doped.The N-type drift layer can be made to thinner than the drift layer in usual vertical MOSFET, while still reach identical Breakdown voltage.

Overlapped top plan channel region of Part I of the grid, and the Part II of the grid is extended perpendicularly at this In groove beside the vertical sidewall of N-type layer.

The MOSFET includes a vertical screen field plate, and it is formed by conductive material (such as DOPOS doped polycrystalline silicon), fills the ditch Groove is simultaneously isolated by dielectric material (such as oxide) with such side wall.The field plate is more deeper than the P- wells, with by the shut-off The N-type layer is laterally exhausted under state and effective electric field reduction is provided in the N-type layer.The field plate be likely to be connected to the source electrode or To the grid or it is suspension joint.

When the MOSFET for shut-off to improve the breakdown voltage when, the vertical component of the grid and the field plate both help In laterally exhausting the N-type layer.When the MOSFET is connects to reduce the conducting resistance, the vertical component of the grid also along Such N-type layer side wall accumulating electrons on the P- wells opposite.Therefore, because the JFET areas (between the P- wells and groove) can be with It is made to narrower without the Over-constrained current path, therefore such monomer may be more small-sized.Further, since the N-type layer can be with Relatively high doped is without reducing the breakdown voltage, therefore the conducting resistance further reduces.The vertical component of the grid, it is somebody's turn to do The compound action of the N-type drift layer of field plate, the N-type layer of the relatively heavy doping and reduction thickness, there is provided the breakdown voltage of raising, Reduce conducting resistance and (because the conducting resistance of per unit area is relatively low, therefore allow each crystal grain system per the relatively low cost of crystal grain Make more small-sized).The structure allows higher monomer density (including band because the conducting resistance of per unit area is relatively low (strips)), so as to realizing the larger current handling capability of per unit area.

Due to the low-mix dopant concentrations drift region between the N-type layer and the drain electrode can be made to it is relatively thin without The breakdown voltage can be reduced, therefore per unit area conducting resistance (specifying conducting resistance Ron* areas) is less than the usual vertical power MOSFET。

To accelerate switching to reduce the gate drain capacitor, the vertical field plate can be connected to the source electrode (rather than extremely The grid), and the horizontal grid part is not extended to above the field plate.

In a specific embodiment, the grid, the vertical field plate and N-type layer doping and thickness selection so that the N-type Layer is completely depleted when puncturing beginning.

In one application, load is coupled between the bottom drain electrode and positive voltage supply, and the top of the transistor Source electrode on end surfaces is ground connection.When the grid relative to the source electrode enough on the occasion of bias when, electric current is supplied to this Load.

If the MOSFET shares with alternating voltage, the PN diodes of the MOSFET will be in the drain electrode than the source electrode more negative value When conduct.When the pole reversal and the diode reverse bias, after the grid bias to off state, the MOSFET it is complete Fully closed break before has the storage electric charge that must go to remove.Due to having higher dopant degree in the N-type layer, so storage electric charge is very fast Remove, so as to realize that switching time accelerates.In other words, the MOSFET structure reduces this time after the PN diode biasings are connected The multiple time.

Insulated Gate Bipolar transistor (IGBT, Insulated gate bipolar transistor) structure is also led to Cross using P+ substrates and formed.

Illustrate other specific embodiments.

Brief description of the drawings

Fig. 1 is the profile of the usual plane vertical DMOS transistor monomer in the array that identical is connected monomer.

According to the specific embodiment of the present invention, Fig. 2A is single in the array that parallel connection connects the connected monomer of identical It is vertical to include one for the profile of one vertical DMOS transistor monomer (it may be a part for band), the wherein grid conductor Part, its around a part for trench vertical sidewalls to improve conducting resistance, and wherein vertical screen field plate also in the trench with Improve breakdown voltage.

According to other specific embodiments of the present invention, Fig. 2 B to Fig. 7 C and Fig. 9 A to Figure 10 W are also to connect phase in parallel connection The profile of single DMOS transistor monomers in the array of same connected monomer.

Fig. 2 B are illustrated in the beneath trenches using P- blind zones to improve breakdown voltage.

Fig. 2 C are illustrated using the P- files and N- files of relatively high doped to reduce conducting resistance.

Fig. 2 D are illustrated using the enhancing N-type surface district (N-Surf) of the adjacent P- wells to reduce conducting resistance.

Fig. 2 E are illustrated between the channel bottom and P- blind zones using enhancing N-type region (N- tops) to improve shut-off switching Time.

Fig. 2 F are illustrated using the P- files and N- files of relatively high doped and without P- blind zones to reduce conducting resistance With shut-off switching time.

Fig. 3 A are illustrated and are extended to the groove to improve durability and reduce the P- wells of the size of each monomer, the wherein grid Vertical component reversion close to the groove P- wells.

Fig. 3 B are illustrated using enhancing N-type surface district (N-Surf) to reduce conducting resistance.

Fig. 3 C are illustrated in the beneath trenches using P- blind zones to improve breakdown voltage.

Fig. 3 D are illustrated using the P- files and N- files of relatively high doped to reduce conducting resistance.

Fig. 3 E are illustrated using deep P+ areas with durable to improve by the such effect for reducing parasitic NPN bipolar transistor Property.

Fig. 3 F are illustrated using multilayer P- files and N- files to reduce conducting resistance.

Fig. 3 G are illustrated between the channel bottom and P- blind zones using enhancing N-type region (N- tops) to improve shut-off switching Time.

Fig. 3 H are illustrated using the P- files and N- files of relatively high doped and without P- blind zones to reduce conducting resistance With shut-off switching time.

Fig. 4 A illustrate the grid and do not overlap the vertical screen field plate to reduce gate drain capacitor and improve switch speed.

Fig. 4 B illustrate the vertical screen field plate that the source metal is connected to along different sections.

Fig. 4 C are illustrated between P- wells and P- blind zones using p type island region (P- connections) to improve shut-off switching time.

Fig. 5 A illustrate the extension of the grid to reduce the vertical screen field plate of conducting resistance, and the wherein gate oxide is thick Degree is stepped (stepped) for optimal conducting resistance and breakdown performance.

Fig. 5 B are illustrated using P- files and N- files to reduce conducting resistance.

Fig. 6 A illustrate the P- wells for coupling the trenched side-wall to improve durability.

Fig. 6 B are illustrated using enhancing N-type surface district to reduce conducting resistance.

Fig. 6 C illustrate the grid and do not overlap the vertical screen field plate to reduce gate drain capacitor and improve switch speed.

Fig. 7 A are illustrated in the equipotential line in the simulation of Fig. 2 C transistor when breakdown starts.Central monomer is with adjacent The each several part of monomer is shown.Summarize P- shieldings and the doping transformation of P- files.

Fig. 7 B are illustrated in the equipotential line in the simulation of Fig. 6 A transistor, wherein the P- wells when breakdown starts and extended to The groove is to improve durability.

Fig. 7 C are illustrated in equipotential line in the simulation of Fig. 2 E transistor when breakdown starts, its have N- top zones with Improve performance of handoffs.

Fig. 8 A are the top views of a part for the monomer to form band, wherein such grid is parallel to such groove, and its Shown in identical monomer be adjacent monomer.

Fig. 8 B are the top views of a part for the single monomer to form band, wherein such gate vertical is in such groove, And identical monomer shown in it is adjacent monomer.

Fig. 8 C are the top views of a part for the single monomer to form closing hexagon, and identical monomer shown in it is phase Adjacent monomer and shared groove.Such groove may also form square, rectangle etc. and close monomer to be formed.

Fig. 9 A illustrate forms IGBT using P+ substrates, reduces conducting resistance by cost of switch speed.

The segmentation P+ and N+ areas of Fig. 9 B illustrations in a substrate are to form the combination of IGBT and DMOS transistors, to reduce conducting Resistance but IGBT compared to Fig. 9 A has very fast switch speed.

Fig. 9 C are similar to Fig. 9 B, but P- wells close to the groove to improve durability.

Fig. 9 D are illustrated between the channel bottom and P- blind zones using enhancing N-type region (N- apical tiers), are somebody's turn to do with improving IGBT shut-off switching time.

Fig. 9 E are illustrated using the P- files and N- files of relatively high doped and without P- blind zones to reduce conducting resistance With IGBT shut-off switching time.

Figure 10 A to 10W illustrate the various novel manufacturing steps of the plane vertical DMOS transistor for forming Fig. 3 D, wherein The array of same monomer is connected in parallel to be formed.

In various accompanying drawings, identical or equivalent component is indicated with identical numbering.

Symbol description

10 monomers

12 inversion channels

14 junction field effect transistor areas

16 P- wells

17 grids

18 source electrodes

20 source areas

22 P+ contact areas

24 N-- drift regions

26 N++ substrates

28 drain electrodes

30 monomers

32 drain electrodes

34 source electrodes

36 grids

37 P+ contact areas

38 P- wellblocks

40 N- layers

42 perpendicular extensions

44 grooves

46 source areas

48 drift regions

50 substrates

52 field plates

53 dielectric substances

54 oxide skin(coating)s

56 gate oxides

60 P- blind zones

61 N- apical tiers

64 P- files

64A P- files

65 N- files

65A N- charge balance files

67 P- bonding pads

68 N- surface districts

70 P+ areas

80 substrates

81 N-- cushions

82 P+ areas

84 N+ areas

86 pad oxide skin(coating)s

88 N-type dopants

90 p-type dopants

92 photoresistance covers

94 oxide hard covers

96 oxide skin(coating)s

98 photoresistance covers

100 phosphorus or arsenic implantation

102 p-type dopants

104 sacrificial oxide layers

106 field oxide layers

108 conduction polysilicons

110 polysilicon layers

112 photoresistance covers

114 p-type dopants

116 N-type dopants

118 borophosphosilicate glass layers

120 boron

S spacing

Y spacing

Xj depth

Embodiment

According to the specific embodiment of the present invention, Fig. 2A is the number that the connected MOSFET monomers of identical are connected in parallel connection The profile of single vertical MOSFET monomer 30 in group.Aftermentioned Fig. 8 A to Fig. 8 C illustrate the various configurations of such monomer, this bag Include band and closing monomer.In such profile, such various regions are all not drawn on scale to be illustrated with facilitating.Fig. 7 A and figure 7B such analogous diagram shows more accurately relative size.

In fig. 2, the width of shown monomer 30 is about 5-15 microns.Monomer 30 may have the breakdown more than 600 volts Voltage, and the quantity of the monomer 30 in the array of identical monomer determines the current handling capability, such as 20 amperes.Monomer Array may be band, square, hexagon or other known forms.

In one is normally applied, load is connected between bottom drain electrode 32 and positive voltage supply, and top source electrode Electrode 34 is ground connection.When the positive voltage more than the critical voltage puts on conductive gate 36, the top end surface of P- wellblocks 38 is anti- Turn, and such vertical sidewall that N- layer 40 of the electronics along the perpendicular extension 42 close to grid 36 gathers, to propagate the electric current And reduce the conducting resistance of N- layers 40.P+ contact areas 37 connects P- wellblocks 38 to source electrode 34 on resistive.

The perpendicular extension 42 of grid 36 may extend below P- wellblocks 38, but (logical reducing the gate drain capacitor Cross and reduce its surface area) and by extending perpendicular extension 42 have balance profit deeper into groove 44 to reduce between conducting resistance Disadvantage.

N++ source areas 46, P- wellblocks 38 and the top end surface of N- layers 40 form the lateral dmos transistor of MOSFET monomers 30 Part.Under the on-state, have between source electrode 34 and drain electrode 32 by N++ source areas 46, P- wellblocks 38 Inversion channel, N- layers 40, the conduction N-type channel of N-- drift regions 48 and N++ substrates 50.

Lateral dmos transistor part, the higher-doped of N- layers 40, the perpendicular extension 42 of grid 36 and N-- drift regions 48 Reduction thickness combination, reduce the conducting resistance compared to prior art.This structure (is connected to the source because of vertical field plate 52 Pole) effect and the breakdown voltage is also improved compared to prior art, and if PN diodes become positive inside such MOSFET Bias and then reverse biased, then accelerate the switching time.

Dielectric substance 53 (such as oxide) isolates source electrode 34.

The side wall of groove 44 is covered with oxide skin(coating) 54, and the trench fill has to form the conductive material of vertical screen field plate 52 (such as polysilicon).The thickness of gate oxide 56 is less than grid 36, and compares oxide skin(coating) along the perpendicular extension 42 of grid 36 54 thinner many.This partially due to the top of N- layers 40 voltage potential than close to the more small thing in the bottom of N- layers 40 It is real, therefore the oxide can be with relatively thin without reducing the breakdown voltage close to the top.

Vertical screen field plate 52 combines with the perpendicular extension 42 of grid 36, is to turn off to improve the breakdown in the MOSFET N- layers 40 are laterally exhausted during voltage.Whole N- layers 40 are preferably completely depleted when puncturing beginning.Opened in breakdown N-- drift regions 48 Preferably also to be completely depleted during the beginning.

The effect of the perpendicular extension 42 of grid 36 allows to reduce P- wellblocks 38 to groove (along the side wall accumulating electrons) 44 interval Ss, so as to realize reduction monomer spacing and effective area, while still produce compared with low on-resistance, this causes relatively low Rsp. Interval S can be, for example, less than the 0.5 to 0.1 of P- well depths of engagement Xj.Field plate 52 can be electrically connected to grid 36 or Source electrode 34 can be suspension joint.Connection field plate 52 to source electrode 34 provides relatively low gate drain capacitor or relatively low grid Gate-drain electric charge (Qgd, gate-drain charge), and the field plate is connected to grid 36 due to being biased into positive electricity in grid 36 Electron accumulation layer is established along the long length of such trenched side-wall during pressure, therefore is produced compared with low on-resistance.

Groove 44 may be that 2-20 microns are deep.The width (between adjacent monomer) of groove 44 may be 1-2 microns.P- The depth of wellblock 38 may be about 2.5 microns.N- layers 40 and the thickness of N-- drift regions 48 are based on the required breakdown voltage and determined, and Simulation may be used to determine.

If monomer 30 is closing monomer (such as hexagon or square), the perpendicular extension 42 and perpendicualr field of grid 36 Plate 52 surrounds N- layers 40.If monomer 30 is band, the perpendicular extension 42 and vertical field plate 52 of grid 36 are along N- layers 40 Length extends.

Fig. 2 B show the another specific embodiment similar to Fig. 2A, but self-aligned P- blind zones 60 are under groove 44 Side.Under the off state, the electric field of the device reverse biased and the lower section of the reduction of P- blind zones 60 groove 44, due to P- blind zones 60 is completely depleted before breakdown, therefore causes high breakdown voltage.P- blind zones 60 are also used for laterally exhausting N- layers 40 to enter one Step improves breakdown voltage.P- blind zones 60 can be suspension joint, but switch device connection from the off state, due to Jie The parasitic capacitance of depletion layer must be discharged between P- blind zones 60 and N- layers 40 and N-- drift regions 48.It is therefore advantageous to pass through P- wellblocks 38 connect P- blind zones 60 to source electrode 34 with the p-type bonding pad on some positions of the crystal grain (not shown).P- Blind zone 60 is connected to source electrode 34, and for current discharge, the electric capacity provides path, and improves from the shut-off to the on-state Switch the switching delay during the device.

Fig. 2 C show the another specific embodiment similar to Fig. 2 B, but have the He of P- files 64 of P- charge balance files The N- files 65 of N- charge balance files are to reduce the Rsp.N- files 65 help to reduce than the more high doped of N- layer 40 Conducting resistance.P and N files 64/65 exhaust when the device is shut-off, and preferably completely depleted when puncturing beginning.

Fig. 2 D show the another specific embodiment similar to Fig. 2 C, but self-aligned strengthens N- surface districts 68 (N-Surf) Around the edge of P- wellblocks 38 and extend to the trenched side-wall.N- surface districts 68 have the doping concentration higher than N- layers 40.Grid 36 perpendicular extension 42 in N- surface districts 68 accumulating electrons further to reduce its conducting resistance.Therefore, N- surface districts 68 There is provided compared with low on-resistance and preferable current spread.Preferably P- blind zones 60 and P- files 64 and N- files 65 are worn out in assault It is completely depleted during the beginning.

Fig. 2 E show the another specific embodiment similar to Fig. 2 B, but the suspension joint of self-aligned P- blind zones 60 and by N Type N- apical tiers 61 separate with groove 44.Doping preferably in N- apical tiers 61 is higher than the doping of N- layers 40 without significantly Reduce the breakdown voltage.N- apical tiers 61 cause the electric capacity of such depletion layer to improve electric discharge on the top of P- blind zones 60, and Switching delay during reduction connection.

Fig. 2 F show the another specific embodiment similar to Fig. 2 E, but with P- files 64 and N- charge balance files N- files 65 are to reduce Rsp.N- files 65 help to reduce conducting resistance than the more high doped of N- layer 40.P and N files 64/65 exhausts when the device is shut-off, and preferably completely depleted when puncturing beginning.P- files 64 are surrounded by N-type region and led Causing the electric capacity of such depletion layer improves electric discharge, and reduces the switching delay during connecting.

Fig. 3 A to Fig. 6 C displays are similar to other specific embodiments of Fig. 2A to Fig. 2 F device, but P- wellblocks 38 couple The groove top corner is to reduce the size of the monomer and improve durability.

In figure 3 a, the top of the horizontal component reversion P- wellblocks 38 of grid 36, and the perpendicular extension 42 of grid 36 is anti- Turn the sides of P- wells 38 to establish vertical-channel.Perpendicular extension 42 also gathers electricity in the N- layers 40 close to perpendicular extension 42 Son.Therefore, the current path will not be constrained by the size reduction of the monomer.Perpendicular extension 42 can extend deeper into groove 44 Further to reduce conducting resistance；However, the gate drain capacitor will have increase, so as to reduce switch speed.

Fig. 3 B are shown using above-mentioned N- surface districts 68 further to reduce conducting resistance.

Fig. 3 C are shown using above-mentioned P- blind zones 60 to improve breakdown voltage.

Fig. 3 D are shown using above-mentioned P- files 64 and N- files 65 to reduce conducting resistance and improve the breakdown voltage.

Fig. 3 E show the another specific embodiment similar to Fig. 3 D, but deep P+ areas 70 are than 38 deeper source electrode of P- wellblock Below contact.P+ areas 70 establish nurse contact difficult to understand with source electrode 34, and electrically connect P- wellblocks 38 to source electrode 34.P+ areas 70 are logical Cross high doped and reduce the gain of the parasitic NPN transistor, effectively prevent the parasitic NPN bipolar transistor from connecting.By Do not allow the NPN transistor to connect, without high current via the NPN transistor caused by thermal runaway, and disaster will not occur Property second breakdown.

Fig. 3 F show the another specific embodiment similar to Fig. 3 D, but have the P- files of multilayer P- charge balance files The N- files 65 of 64 and N- charge balance files, the P- file 64A and N- charge balance files 65A of P- charge balance files.By It is multilayer " thin " layer by forming such P- files and N- files, has less lateral dopant to propagate, therefore such file can be more It is formed accurately.Pay attention to relatively low P- files 64A how because of the extra heat budget and the high P- files 64 of comparison are wider.It can be formed super Cross two layers of P- files and N- files.Preferably P- blind zones 60, N- files 65, P- files 64, N- layers 40 and N- drift regions 48 It is completely depleted when beginning is worn in assault.

Fig. 3 G show the another specific embodiment similar to Fig. 3 C, but have suspension joint P- blind zones 60 and N- apical tiers 61 To improve switch speed.

Fig. 3 H show the another specific embodiment similar to Fig. 3 D, but using P- files 64 and N- files 65 and without P- screens Area is covered to improve switch speed.

Fig. 4 A show the another specific embodiment similar to Fig. 3 C, but there is L-shaped grid 36 to minimize grid 36 Overlap, and for the shielding field plate 52 of relatively low gate drain capacitor to improve switch speed.

Fig. 4 B show Fig. 4 A specific embodiment, but are electrically connected to source via different sections, display shielding field plate 52 The region of pole electrode 34.In other specific embodiments, shielding field plate 52 be likely to be connected to grid 36 (so as to will improve electric capacity), Or it is suspension joint.

Fig. 4 C show the another specific embodiment similar to Fig. 2 B, but have P- blind zones 60 being electrically connected to P- wellblocks 38 and source electrode 34 to improve the P- bonding pads 67 of switch speed.

Such as in other such specific embodiments, the perpendicular extension 42 of grid 36 can extend any distance to groove 44 In, it is included in the lower section of P- wellblocks 38.

Fig. 5 A and Fig. 5 B display shielding field plates 52 are the specific embodiment of the extension of grid 36.Because the voltage potential connects The top of nearly groove 44 is more small, therefore the thickness of oxide skin(coating) 54 close to the top (on the opposite of P- wellblocks 38) of groove 44 can be with Less than close to the bottom of the groove, therefore without the breakdown of oxide skin(coating) 54.

Fig. 5 B show Fig. 5 A specific embodiment, but have above-mentioned P- files 64 and N- files 65.

Fig. 6 A to Fig. 6 C show that P- wellblocks 38 couple other specific embodiments of the side wall of groove 44, therefore the surface of N- layers 40 Will not be directly below grid 36.There is this device longer compound lateral and vertical-channel, a part for the wherein raceway groove to be Plane, and another part is vertical.Such horizontal and vertical part of grid 36 is used to invert the channel region.So reduce the grid Gate-drain electric capacity simultaneously reduces the monomer spacing, while also reduces this and specify conducting resistance.Fig. 6 A to Fig. 6 C such device has Longer channel length, without increasing the effective surface area.These devices can have shallower depth of engagement, and can provide Relatively low channel leakage stream and relatively low saturation current, and wider ESD protection area (SOA, Safe operation area).The longer raceway groove may also reduce the gain of the parasitic NPN transistor, to improve the dress by preventing second breakdown The durability put.Vertical screen field plate 52 is likely to be connected to source electrode 34 or to grid 36 or be suspension joint.

Fig. 6 B displays use foregoing N- surface districts 68.

Fig. 6 C show that grid 36 does not overlap vertical screen field plate 52 to reduce electric capacity, such as foregoing.

Fig. 7 A are illustrated in when device breakdown starts in the off case, in fig. 2 c between the top of the substrate and the device Equipotential line between end surfaces in depletion region.The complete process flow and resulting device characteristic are imitated by two-dimentional technique/device Really emulated.The transformation of such N-type dopant and p-type dopant passes through the summary corresponding to P- blind zones 60 and P- files 64 Scheme (outline) and show.Vertical screen field plate 52 is connected to source electrode 34.Can per the Ω of mm2 4.5 specified conducting resistance Reached with the breakdown voltage for 645V.

Fig. 7 B are illustrated in Fig. 6 A the equipotential line in depletion region between the substrate and the top end surface of the device, its Such edge of middle P- wellblocks 38 abuts such trenched side-wall.

Fig. 7 C, which are illustrated, has N- apical tiers 61 (Fig. 2 E) in Fig. 2 E between the substrate and the top end surface of the device Equipotential line in depletion region.

Fig. 8 A are the top views for being incorporated to a part for the vertical transistor of any such specific embodiment disclosed in text, its Middle groove 44, grid 36 and such various doped regions (source area 46, P+ contact areas 37 etc.) are formed as the thin strip being connected in parallel Array.Because groove 44 takes region along the X direction, therefore limitation is applied to the monomer pitch dimension shrinkage of the device.In order to subtract Light this limits, and groove 44 can be arranged perpendicular to grid 36, as shown in Figure 8 B.

Fig. 8 C illustrate the single hexagonal close monomer for being incorporated to any such specific embodiment in text.Adjacent monomer shares pen One of wall of straight flute 44 (seeming honeycomb), and all monomers are all connected in parallel.In addition, other closing monolithic designs are also contemplated within, Such as square.

Fig. 9 A, which are shown, is similar to foregoing specific embodiment, but there is P+ substrates 80 to form IGBT structure.In addition, Show N-- cushions 81.In this case, drain electrode 32 becomes anode or colelctor electrode.By apply critical voltage in Grid 36 connects the IGBT and connects the PNP transistor.IGBT has compared with low on-resistance compared to such non-IGBT devices, but It is that there is slower switch speed.Any such aforementioned means can all be fabricated to IGBT.

Fig. 9 B are shown with P+ areas 82 and N+ areas 84 with the substrate 80 in parallel for forming IGBT and DMOS transistor units.Switching IGBT of the speed compared to Fig. 9 A is improved.

Fig. 9 C show Fig. 9 B structure, but P- wellblocks 38 abut the groove, such as foregoing.

Fig. 9 D are illustrated using the enhancing N-type region (N- apical tiers 61) between the bottom of groove 44 and P- blind zones 60, with Improve the shut-off switching time of the IGBT.

Fig. 9 E are illustrated using relatively the P- files 64 of high doped and N- files 65 and without the P- blind zones, are led with reducing It is powered and hinders and turn off the switching time of the IGBT.

Illustrate the possibility technique of Fig. 3 D device in Figure 10 A to Figure 10 W below.Similar technique can be used for manufacturing any Other such specific embodiments.

In Figure 10 A, epitaxial layer (N-- drift regions 48) is grown on the top of N++ substrates 50.N-- drift regions 48 may In growth period doping in situ, or may be in about 1.5E12cm^-2Dosage with N-type dopant periodically be implanted into.Substrate 50 may With about 5E19cm^-3Concentration of dopant.For the device with about 600V breakdown voltages, in N-- drift regions 48 most Whole dopant density is about 3.5E14cm^-3.N-- drift regions 48 may be 30 microns of thickness.

In Figure 10 B and Figure 10 C, pad oxide skin(coating) 86 is formed and N-type dopant 88 (such as phosphorus) implantation N-- drift regions 48, then (Figure 10 C) is the implantation step of p-type dopant 90 (such as using boron) through cover to form N- files 65 and P- files 64.In addition, display photoresistance cover 92.The N-type implant dosage may be about 1-2E12cm^-2.The p-type implant dosage may be about 1E13cm^-2。

In figure 10d, the second epitaxial layer for forming N- layers 40 is raw after the photoresistance and oxide peel off (stripped) It is long.N- layers 40 have about 2.3E15cm^-3Dopant density, this is higher than dopant density in N-- drift regions 48.N- layers 40 About 8 microns of thickness.In another specific embodiment, dopant density in N- layers 40 and the substantially phase in N-- drift regions 48 Together.

In Figure 10 E, oxide hard cover 94 is formed on the top of N- layers 40.

In figure 10f, extra thick oxide layers 96 are formed.

In Figure 10 G, photoresistance cover 98 is laid out pattern on oxide skin(coating) 96, and oxide skin(coating) 96 and oxide hard are covered 94 are covered through dry etching to define the trench region.

During such various steps, such dopant in N- files 65 and P- files 64 is inlaid into (driven In) and spread, to form the thick file layer of about 4-5 microns, wherein the N-type dopant concentration about 2E15cm in N- files 65^-3, And the p-type concentration of dopant about 1E16cm in P- files 64^-3.Dopant density in N- files 65 may be greater than or less than N- layers 40.

In Figure 10 H, N- surface districts 68 optionally are implanted into using phosphorus or arsenic implantation 100.Obtained by Figure 10 I are shown N- surface districts 68.

In Figure 10 J, silicon dry etching is performed to form groove 44, and p-type dopant 102 (such as boron) is about 4E12cm^-2Dosage groove 44 is implanted into a manner of self-aligned, to establish P- blind zones 60.The etching groove is below groove 44 Leave the N- layers 40 of about 3-4 microns.In this step, N-type dopant (such as arsenic) optionally is in dosage about 2E12cm^-2With self Alignment is implanted into groove 44, to form N- apical tiers on P- blind zones 60.

In especially creative step, sideways diffusion enters N- layers 40 to N- surface districts 68, then etched to form ditch Groove 44.Therefore, N- surface districts 68 and the self-aligned of groove 44.

In Figure 10 K, sacrificial oxide layer 104 is formed, about 1000 angstroms of thickness.

In Figure 10 L, field oxide (FOX) layer 106 grow or be deposited on including the silicon mesa surfaces, the trenched side-wall and On the crystal column surface of the channel bottom.The thickness of FOX layers 106 is about 6000 angstroms.

In Figure 10 M, conduction polysilicon 108 (polysilicon) deposition is on the wafer to fill groove 44, then such as Figure 10 N The polysilicon is shown to be etched back.Polysilicon in groove 44 forms vertical screen field plate 52.

In Figure 10 O, by wet etching or wet/dry group technology, Figure 10 N field oxide (FOX) layer 106 from The silicon mesa surfaces remove completely, and are removed along the sidewall sections of groove 44.The residue that field plate 52 and the trenched side-wall are separated FOX layers mark oxide skin(coating) 54 now.

In Figure 10 P, gate oxide 56 then grows into about 900 angstroms of thickness.

In Figure 10 Q, conductive polysilicon layer 110 then deposits.

In Figure 10 R, polysilicon layer 110 is laid out pattern using photoresistance cover 112, and etched is vertically prolonged with being formed to have Stretch the grid 36 of thing 42.

In Figure 10 S, photoresistance cover 112 is peeled off and p-type dopant 114 (boron) implantation N- layers 40, to be formed and grid 36 The P- wellblocks 38 of self-aligned.Such dopant is then inlaid into.

In Figure 10 T, N-type dopant 116 (arsenic or phosphorus) implantation, to form the N++ source areas with the self-aligned of grid 36 46。

In Figure 10 U and Figure 10 V, thickness lining oxide and boron-phosphorosilicate glass (BPSG) layer 118 are formed to define P+ contacts Area 37, and boron 120 is implanted into.

In Figure 10 W, the source metal for example deposits simultaneously cloth by sputter aluminum bronze (AlCu) or aluminium copper silicon (AlSiCu) Office's pattern may be about 4 microns of thickness to form source electrode 34.Figure 10 W are identical with Fig. 3 D.

The back metal then for example by sputter each the titanium (Ti) of 1000,2000 and 10000 angstroms of thickness, nickel (Ni) and Silver-colored (Ag) layer and deposit to form drain electrode 32.

All accompanying drawings of display are all not drawn on scale to be illustrated with facilitating.Actual apparatus structure size and engagement profile will It is different from shown in above-mentioned accompanying drawing depending on required breakdown voltage, conducting resistance, the current requirements etc..Fig. 7 A and Fig. 7 B's is such Simulation result shows more accurately representative dimensions.

Any such disclosed feature can all be combined in MOSFET or IGBT with any combinations, with for application-specific Reach such specific benefit of this feature.

Although the certain specific embodiments of the present invention have shown and illustrated that those skilled in the art will be evident change Example may accomplish and not depart from the present invention in its more extensive aspect for example and modification, and therefore, appended claims such as fall within this hair In bright true spirit and category, all such change case and modification example are covered in its category.

Claims (21)

1. a kind of vertical power mos field effect transistor with planar channeling, it is characterised in that include：

Semiconductor substrate, on its bottom surface with a first electrode；

A first layer of one first conduction type of side, the first layer have one first concentration of dopant on the substrate；

A second layer of first conduction type above the first layer, the second layer have higher than first concentration of dopant One second concentration of dopant, the second layer have a top end surface；

One groove, it has the vertical sidewall for coupling the second layer；

A wellblock of one second conduction type on the top end surface of the second layer, the wellblock have a top end surface；

One first area of first conduction type on the top end surface of the wellblock, wherein between firstth area and the one of the wellblock A region between edge includes a raceway groove, and it is used to be inverted by a grid；

One conductive gate, it covers the raceway groove so that when the grid bias is higher than a critical voltage, side is established in the raceway groove To conductive path,

The grid, its perpendicular extension for having towards the vertical sidewall and isolating with the side wall；

One vertical field plate, its towards the second layer vertical sidewall and isolate with the side wall；

One second area, it is first conduction type, surrounds and completely cuts off the wellblock and extend to

The groove of vertical sidewall, secondth area have the concentration of dopant higher than second concentration of dopant, and it is reduction Conducting resistance；And

One second electrode, it makes electrical contact with the wellblock and firstth area, wherein when a voltage put on the first electrode with this second Between electrode and when the grid bias is higher than the critical voltage, a lateral current flows through the raceway groove and an electric current flowing is in the raceway groove Between the substrate.

2. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, also includes：

One third layer of first conduction type, it is between the first layer and the second layer and below the raceway groove；With And

One the 4th layer of second conduction type, it laterally abuts the third layer on the opposite side of the third layer, the 3rd A concentration of dopant in layer and the 4th layer is higher than first concentration of dopant.

3. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 2, its It is characterised by, also the layer 5 comprising second conduction type, it is in the beneath trenches and laterally close to the second layer.

4. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 3, its It is characterised by, the layer 5 abuts the 4th layer.

5. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 3, its It is characterised by, the first layer is spaced vertically apart from the 4th layer.

6. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the vertical field plate is electrically connected to the second electrode.

7. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by that the grid is had into a perpendicular extension, it completely cuts off in face of the vertical sidewall and from the side wall, and the wherein grid At least it is partly to face secondth area in the perpendicular extension of pole.

8. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the vertical field plate is electrically connected to the grid.

9. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the vertical field plate is more deeper than the wellblock.

10. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the grid has a perpendicular extension, and it completely cuts off in face of the vertical sidewall and from side wall, and the wherein grid The perpendicular extension extends below the wellblock.

11. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the wellblock extends to the vertical sidewall of the second layer.

12. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 11, Characterized in that, the grid is had into a perpendicular extension, it completely cuts off in face of the vertical sidewall and from the side wall, and wherein should The wellblock of the perpendicular extension reversion of grid close to the part of the vertical sidewall.

13. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, one the 3rd area also comprising second conduction type, it is in the beneath trenches and laterally close to the second layer.

14. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, one second area also comprising second conduction type, it is in the beneath trenches and laterally close to the second layer.

15. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the substrate is first conduction type, and wherein the transistor is a metal oxide semiconductor field effect transistor Pipe.

16. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the substrate is second conduction type, and wherein the transistor is an Insulated Gate Bipolar transistor.

17. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, the second concentration of dopant of the vertical field plate and the second layer is configured to strengthen laterally exhausting for the second layer, with Make the second layer completely depleted in a breakdown voltage of the transistor.

18. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, also includes：

One third layer of first conduction type, it is between the first layer and the second layer and below the raceway groove；With And

One the 4th layer of second conduction type, it laterally abuts the third layer on the opposite side of the third layer, the 3rd A concentration of dopant in layer and the 4th layer is higher than first concentration of dopant；

The wherein third layer and the 4th layer of formation N-type and p-type file, wherein such N-type and p-type file are the one of the transistor Breakdown voltage is completely depleted.

19. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, also the third layer comprising second conduction type, it is in the beneath trenches and laterally close to the second layer.

20. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, also includes：

One the 3rd area of second conduction type, it is in the beneath trenches and laterally close to the second layer；And

One the 4th area of first conduction type, its between the 3rd area and the groove and laterally close to the second layer, its In a concentration of dopant in the 4th area be higher than second concentration of dopant in the second layer.

21. there is the vertical power mos field effect transistor of planar channeling as claimed in claim 1, its It is characterised by, first layer is formed at the epitaxial layer on the substrate.