TWM544107U - Vertical power MOSFET with planar channel - Google Patents

Description

Vertical power MOS field effect transistor with planar channel

This work is about power MOSFETs, especially for a vertical transistor with a planar double-diffused metal oxide semiconductor (DMOS) portion and a vertical conducting portion.

Vertical MOSFETs are popular as high voltage, high power transistors due to their ability to provide a thick, low dopant concentration drift layer to achieve high breakdown voltages in this off state. Typically, the MOSFET includes a highly doped N-type substrate; a thick low dopant concentration N-type drift layer; a P-type body layer formed in the drift layer; and an N-type source at the body a top end of the layer; and a gate separated from the channel region by a thin gate oxide. A source electrode is formed on the top end surface, and a drain electrode is formed on the bottom surface. When the gate is sufficiently positive with respect to the source, a channel region of the P-type body between the N-type source and the N-type drift layer is reversed to establish between the source and the drain Conduction path.

In the off state of the device, when the gate is shorted to the source or is negative, the drift layer is depleted and a high breakdown voltage (eg, over 600 volts) can be maintained between the source and the drain. . However, the on-resistance is affected by the low doping required for the thick drift layer. Increasing the doping of the drift layer reduces the on-resistance but reduces the breakdown voltage.

1 is a cross-sectional view of a conventional planar vertical DMOS transistor cell 10 in an array of cells. Planar DMOS transistors are widely used in many power switching applications due to their durability compared to trench MOSFETs. However, the conventional planar DMOS transistor has a higher specific on-resistance (Rsp), which is the product of the on-resistance and the effective area. Required to have reduced Rsp and lower input capacitances (Ciss, input capacitances), output capacitances (Coss, output capacitances) and DMOS transistors with transfer capacitance (Crss, transfer capacitances) or gate charge (Qg, gate charge) to reduce the conduction and switching losses of the transistor.

The significant resistance component in the conventional DMOS structure shown in Figure 1 will occur at this voltage drop along the inversion channel 12 and the junction field effect transistor (JFET) region 14 beside the P-well 16 region. When a sufficiently positive voltage is applied to the gate 17, the gate 17 reverses the channel 12. Source electrode 18 contacts N++ source region 20 and P-well 16 through P+ junction region 22. The dielectric body 53 isolates the gate 17 and the source electrode 18. When the gate 17 inverts the channel 12, a horizontal current path is formed between the source region 20 and the low dopant density N--drift region 24, and then the current flows vertically through the N--drift region 24, the N++ substrate 26 And the drain electrode 28. The N--drift region 24 needs to be relatively thick to have a high breakdown voltage, but the low dopant density and thickness of the N--drift region 24 increase the on-resistance.

JFET region 14 limits this current flow, and it is important to use a sufficiently wide P-well spacing (2Y) to minimize this JFET resistance component. However, increasing the pitch Y results in an increase in the cell pitch and the effective area. Therefore, this trade-off has led to limited improvements in Rsp.

There is a great need in the art for planar, vertical DMOS transistors having good Rsp and a relatively small surface area compared to Figure 1 to increase monomer density. Also, the transistor should have a high breakdown voltage and a high switching speed.

It is disclosed as a new DMOS transistor structure with reduced Rsp and gate charge Qg, with high breakdown voltage and high switching speed.

The resulting MOSFET has a planar channel region for lateral current flow and a vertical conduction path for vertical current flow. In a specific embodiment, a P-well (body region) is formed in the N-type layer, wherein a trench deeper than the P-well is formed in the N-type layer to create a vertical sidewall of the N-type layer. The N-type layer is more highly doped than the N-type drift layer below the N-type layer. The N-type drift layer can be made thinner in the conventional vertical MOSFET than the drift layer while still achieving the same breakdown voltage.

A first portion of the gate overlaps the top planar channel region and a second portion of the gate extends vertically into a trench adjacent the vertical sidewall of the N-type layer.

The MOSFET includes a vertical shield field plate formed of a conductive material (e.g., doped polysilicon) that fills the trench and is isolated from the sidewalls by a dielectric material such as an oxide. The field plate is deeper than the P-well to provide effective electric field reduction in the N-type layer by laterally depleting the N-type layer in the off state. The field plate may be connected to the source, or to the gate, or to a floating connection.

When the MOSFET is turned off to increase the breakdown voltage, both the vertical portion of the gate and the field plate contribute to lateral depletion of the N-type layer. When the MOSFET is turned "on" to reduce the on-resistance, the vertical portion of the gate also accumulates electrons along the sidewalls of the N-type layers opposite the P-well. Thus, since the JFET region (between the P-well and the trench) can be made narrower without unduly constraining the current path, the cells may be smaller. In addition, since the N-type layer can be doped relatively high without lowering the breakdown voltage, the on-resistance is further reduced. The combination of the vertical portion of the gate, the field plate, the relatively heavily doped N-type layer, and the reduced thickness N-type drift layer provides increased breakdown voltage, reduced on-resistance, and lower per-die Cost (since the on-resistance per unit area is low, each die is allowed to be made smaller). This structure allows for higher monomer density (including strips) due to lower on-resistance per unit area, thereby achieving greater current handling capability per unit area.

Since the low dopant concentration drift region between the N-type layer and the drain electrode can be made thin without reducing the breakdown voltage, the on-resistance per unit area (specified on-resistance Ron* area) is low. This is a conventional vertical power MOSFET.

To reduce switching the gate-drain capacitance, the vertical field plate can be connected to the source electrode (rather than to the gate) and the horizontal gate portion does not extend above the field plate.

In a specific embodiment, the gate, the vertical field plate, and the N-type layer doping and thickness are selected such that the N-type layer is completely depleted at the beginning of the collapse.

In one application, a load is coupled between the bottom drain electrode and a positive voltage supply, and the source electrode on the top surface of the transistor is grounded. When the gate is sufficiently positively biased relative to the source electrode, current is supplied to the load.

If the MOSFET is shared with an AC voltage, the PN diode of the MOSFET will conduct when the drain is more negative than the source. When the polarity is reversed and the diode is reverse biased, there is a stored charge that must be removed after the gate is biased to the off state and before the MOSFET is completely turned off. Due to the higher dopant level in the N-type layer, the stored charge is removed faster, thereby achieving switching time acceleration. In other words, the MOSFET structure reduces the recovery time after the PN diode bias is turned "on".

An insulated gate bipolar transistor (IGBT) structure is also formed by using a P+ substrate.

Other specific embodiments are described.

10‧‧‧Single

12‧‧‧Reversal channel

14‧‧‧Connected field effect transistor area

16‧‧‧P-well

17‧‧‧ gate

18‧‧‧Source electrode

20‧‧‧ source area

22‧‧‧P+ junction area

24‧‧‧N--drift zone

26‧‧‧N++ substrate

28‧‧‧汲electrode

30‧‧‧single

32‧‧‧汲electrode

34‧‧‧Source electrode

36‧‧‧ gate

37‧‧‧P+ junction area

38‧‧‧P-well area

40‧‧‧N-layer

42‧‧‧Vertical extension

44‧‧‧ trench

46‧‧‧ source area

48‧‧‧ drift zone

50‧‧‧Substrate

52‧‧‧ Field Board

53‧‧‧ dielectric

54‧‧‧Oxide layer

56‧‧‧gate oxide

60‧‧‧P-shield

61‧‧‧N-top layer

64‧‧‧P-column

64A‧‧‧P-column

65‧‧‧N-column

65A‧‧‧N-charge balance column

67‧‧‧P-connection area

68‧‧‧N-surface area

70‧‧‧P+ District

80‧‧‧Substrate

81‧‧‧N--buffer layer

82‧‧‧P+ District

84‧‧‧N+ District

86‧‧‧Mat oxide layer

88‧‧‧N type dopant

90‧‧‧P type dopant

92‧‧‧Photoresist mask

94‧‧‧Oxide hard mask

96‧‧‧Oxide layer

98‧‧‧Photoresist mask

100‧‧‧Phosphorus or arsenic implants

102‧‧‧P type dopant

104‧‧‧Sacrificial oxide layer

106‧‧ ‧ field oxide layer

108‧‧‧ Conductive polysilicon

110‧‧‧Polysilicon layer

112‧‧‧Photoresist mask

114‧‧‧P type dopant

116‧‧‧N type dopant

118‧‧‧Boron phosphate glass layer

120‧‧‧ Boron

S‧‧‧ spacing

Y‧‧‧ spacing

Xj‧‧ depth

[Fig. 1] is a cross-sectional view of a conventional planar vertical DMOS transistor cell in an array of identical connected cells.

[Fig. 2A] is a cross-sectional view of a single vertical DMOS transistor cell (which may be part of a strip) in an array of identical connected cells connected in parallel, in accordance with an embodiment of the present invention.

[Fig. 2B] A cross-sectional view showing a DMOS transistor unit using a P-shielding region under the trench.

2C] A cross-sectional view of a DMOS transistor cell using P-columns and N-columns doped with relatively higher degrees.

[Fig. 2D] A cross-sectional view showing a DMOS transistor cell using an enhanced N-type surface region (N-Surf) adjacent to the P-well.

[Fig. 2E] A cross-sectional view showing a DMOS transistor unit using an enhanced N-type region (N-top) between the bottom of the trench and the P-shielding region.

[FIG. 2F] A cross-sectional view of a DMOS transistor cell using a relatively high degree doped P-column and N-column without a P-shielding region is illustrated.

[Fig. 3A] A cross-sectional view of a DMOS transistor unit of a P-well extending to the trench to improve durability and reduce the size of each cell.

[Fig. 3B] A cross-sectional view showing a DMOS transistor cell using an enhanced N-type surface region (N-Surf).

[Fig. 3C] A cross-sectional view showing a DMOS transistor unit using a P-shielding region under the trench.

[Fig. 3D] A cross-sectional view of a DMOS transistor cell using P-columns and N-columns doped with a relatively high degree is exemplified.

[Fig. 3E] A cross-sectional view showing a DMOS transistor unit using a deep P+ region.

[Fig. 3F] A cross-sectional view showing a DMOS transistor unit using a plurality of P-columns and N-columns.

[Fig. 3G] A cross-sectional view showing a DMOS transistor unit using an enhanced N-type region (N-top) between the bottom of the trench and the P-shielding region.

[Fig. 3H] A cross-sectional view showing a DMOS transistor cell using a relatively high degree doped P-column and N-column without a P-shielding region.

[Fig. 4A] A cross-sectional view showing a DMOS transistor unit in which the gate electrode does not overlap the vertical shield field plate to reduce the gate-drain capacitance.

[Fig. 4B] A cross-sectional view showing a DMOS transistor unit connected to a vertical shield field plate of the source metal along different sections.

[Fig. 4C] A cross-sectional view showing a DMOS transistor unit using a P-type region (P-connection) between a P-well and a P-shielding region.

[Fig. 5A] A cross-sectional view showing a DMOS transistor unit of a vertical shield field plate which is an extension of the gate electrode to reduce on-resistance.

[Fig. 5B] A cross-sectional view showing a DMOS transistor unit using P-columns and N-columns.

[Fig. 6A] A cross-sectional view showing a DMOS transistor unit of a P-well coupled to a sidewall of the trench.

[Fig. 6B] A cross-sectional view showing a DMOS transistor unit using an enhanced N-type surface region.

[Fig. 6C] A cross-sectional view showing a DMOS transistor unit in which the gate electrode does not overlap the vertical shield field plate.

[Fig. 7A] illustrates an equipotential line in the simulation of the transistor of Fig. 2C at the start of the collapse.

[Fig. 7B] An equipotential line in the simulation of the transistor of Fig. 6A at the start of the collapse is exemplified.

[Fig. 7C] An equipotential line in the simulation of the transistor of Fig. 2E at the start of the collapse is exemplified.

[Fig. 8A] is a plan view of a portion of a monomer forming a strip.

[Fig. 8B] is a plan view of a portion of a single monomer forming a strip.

[Fig. 8C] is a plan view of a portion of a single cell forming a closed hexagon.

[Fig. 9A] A cross-sectional view showing a DMOS transistor unit in which an IGBT is formed using a P+ substrate.

[Fig. 9B] A cross-sectional view of a DMOS transistor unit exemplifying a segmented P+ and N+ regions in a substrate to form a combination of an IGBT and a DMOS transistor.

[Fig. 9C] A cross-sectional view similar to Fig. 9B, but with the P-well immediately adjacent to the DMOS transistor of the trench.

[Fig. 9D] A cross-sectional view showing a DMOS transistor unit using an enhanced N-type region (N-tip layer) between the bottom of the trench and the P-shielding region.

[Fig. 9E] A cross-sectional view showing a DMOS transistor cell using a relatively high degree doped P-column and N-column without a P-shielding region.

[Figs. 10A to 10W] illustrate various novel manufacturing steps for forming the planar vertical DMOS transistor of Fig. 3D in which arrays of the same cells are formed in parallel connection.

In the various figures, the same or equivalent elements are designated by the same reference numerals.

In accordance with a specific embodiment of the present writing, FIG. 2A is a cross-sectional view of a single vertical MOSFET cell 30 in an array of identical connected MOSFET cells connected in parallel. 8A to 8C, which will be described later, illustrate various configurations of the monomers, including strips and blocking monomers. In the cross-sectional views, the various regions are not drawn to scale for convenience. The simulations of Figures 7A and 7B show a more accurate relative size.

In Figure 2A, the illustrated monomer 30 has a width of between about 5 and 15 microns. Monomer 30 may have a breakdown voltage in excess of 600 volts, and the amount of monomer 30 in the same array of monomers determines the current handling capability, such as 20 amps. The array of cells may be strips, squares, hexagons or other known shapes.

In one general application, the load is connected between the bottom drain electrode 32 and the positive voltage supply, while the top source electrode 34 is grounded. When a positive voltage greater than the threshold voltage is applied to the conductive gate 36, the top surface of the P-well region 38 is reversed and the electrons are accumulated along the N-layer 40 of the vertical extension 42 adjacent the gate 36. The sidewalls propagate the current and reduce the on-resistance of the N-layer 40. The P+ contact region 37 is ohmically connected to the P-well region 38 to the source electrode 34.

The vertical extension 42 of the gate 36 may extend below the P-well 38, but is reduced by reducing the gate-dipper capacitance (by reducing its surface area) and deepening the trench 44 through the extended vertical extension 42. There is a trade-off between the on-resistance.

The N++ source region 46, the P-well region 38, and the top surface of the N-layer 40 form a lateral DMOS transistor portion of the MOSFET cell 30. In the on state, there is an inversion channel through the N++ source region 46, the P-well region 38, the N-layer 40, the N--drift region 48, and the N++ between the source electrode 34 and the drain electrode 32. The substrate 50 conducts an N-type channel.

The combination of the lateral DMOS transistor portion, the higher doping of the N-layer 40, the vertical extension 42 of the gate 36, and the reduced thickness of the N--drift region 48 reduces the on-resistance compared to prior art techniques. This structure also increases the breakdown voltage due to the action of the vertical field plate 52 (connected to the source) compared to the prior art, and if the PN diodes inside the MOSFET become forward biased and then reverse biased, then Accelerate the switching time.

A dielectric body 53 (e.g., an oxide) isolates the source electrode 34.

The sidewalls of trench 44 are covered with an oxide layer 54, and the trench is filled with a conductive material (e.g., polysilicon) that forms vertical shield field plate 52. The gate oxide 56 is less thick than the gate 36 and is substantially thinner along the vertical extension 42 of the gate 36 than the oxide layer 54. This is due in part to the fact that the voltage potential at the top of the N-layer 40 is much smaller than the bottom of the N-layer 40, so that the oxide can be thinner near the tip without reducing the breakdown voltage.

The vertical shield field plate 52 is combined with the vertical extension 42 of the gate 36 to laterally deplete the N-layer 40 when the MOSFET is turned off to improve the breakdown voltage. The entire N-layer 40 is preferably completely depleted at the beginning of the crash. The N--drift region 48 is preferably also completely depleted at the beginning of the crash.

The function of the vertical extension 42 of the gate 36 (accumulating electrons along the sidewall) allows the P-well 38 to the trench 44 spacing S to be reduced, thereby reducing the cell spacing and effective area while still producing a lower on-resistance, This results in a lower Rsp. Spacing S may be, for example, less than P- well junction depth X _j of 0.5 to 0.1. Field plate 52 can be electrically connected to gate 36, or source electrode 34, or can be floating. Connecting the field plate 52 to the source electrode 34 provides a lower gate-drain capacitance or a lower gate-drain charge (Qgd), while the field plate is connected to the gate 36 due to the gate 36. The electron accumulation layer is established along the longer length of the sidewalls of the trenches when biased to a positive voltage, thus producing a lower on-resistance.

The trench 44 may be 2-20 microns deep. The width of the trenches 44 (between adjacent cells) may be 1-2 microns. The P-well 38 depth may be approximately 2.5 microns. The thickness of N-layer 40 and N--drift region 48 is determined based on the desired breakdown voltage and may be determined using simulation.

If the monomer 30 is a closed monomer (e.g., hexagonal or square), the vertical extension 42 of the gate 36 and the vertical field plate 52 surround the N-layer 40. If the cell 30 is a strip, the vertical extension 42 of the gate 36 and the vertical field plate 52 extend along the length of the N-layer 40.

FIG. 2B shows another embodiment similar to FIG. 2A, but with self-aligned P-shield region 60 below trench 44. In this off state, the device is reverse biased and the P-shield region 60 reduces the electric field below the trench 44, resulting in a higher breakdown voltage due to the complete depletion of the P-shield region 60 prior to collapse. The P-shield region 60 is also used to laterally deplete the N-layer 40 to further increase the breakdown voltage. The P-shielding region 60 may be floating, but switching the device from the off state is caused by a parasitic layer between the P-shielding region 60 and the N-layer 40 and the N--drift region 48. The capacitor must be discharged. Accordingly, it is preferred to connect the P-shielding region 60 to the source electrode 34 via a P-well region 38 and a P-type connection region at certain locations of the die (not shown). The connection of the P-shielding region 60 to the source electrode 34 provides a path for current discharge to the capacitor and improves the switching delay during switching of the device from the turn-off to the turn-on state.

2C shows another embodiment similar to FIG. 2B, but with a P-column 64 of the P-charge balancing column and an N-column 65 of the N-charge balancing column to reduce the Rsp. The N-column 65 is more highly doped than the N-layer 40, thus helping to reduce the on-resistance. The P and N columns 64/65 are depleted when the device is turned off, and are preferably completely depleted at the beginning of the crash.

2D shows another embodiment similar to FIG. 2C, but a self-aligned enhanced N-surface region 68 (N-Surf) surrounds the edge of the P-well region 38 and extends to the trench sidewall. The N-surface region 68 has a higher doping concentration than the N-layer 40. The vertical extension 42 of the gate 36 accumulates electrons in the N-surface region 68 to further reduce its on-resistance. Thus, N-surface region 68 provides lower on-resistance and better current propagation. Preferably, the P-shielding zone 60 and the P-column 64 and the N-column 65 are completely depleted at the beginning of the collapse.

2E shows another embodiment similar to FIG. 2B, but the self-aligned P-shielding region 60 is floated and separated from the trench 44 by an N-type N-top layer 61. Preferably, the doping in the N-top layer 61 is higher than the doping of the N-layer 40 without substantially reducing the breakdown voltage. The N-top layer 61 causes a capacitance-enhancing discharge of the depletion layers on the top of the P-shielding region 60 and reduces the switching delay during turn-on.

2F shows another embodiment similar to FIG. 2E, but with a P-column 64 and an N-column 65 of N-charge balancing columns to reduce Rsp. The N-column 65 is more highly doped than the N-layer 40, thus helping to reduce the on-resistance. The P and N columns 64/65 are depleted when the device is turned off, and are preferably completely depleted at the beginning of the crash. The P-column 64 is surrounded by an N-type region to cause a capacitor to improve discharge of the depletion layers and to reduce switching delays during turn-on.

Figures 3A-6C show other embodiments of the apparatus similar to Figures 2A-2F, but P-well 38 couples the top end corners of the trench to reduce the size of the unit and improve durability.

In FIG. 3A, the horizontal portion of the gate 36 reverses the top end of the P-well region 38, and the vertical extension 42 of the gate 36 reverses the side of the P-well 38 to establish a vertical channel. Vertical extensions 42 also accumulate electrons in the N-layer 40 adjacent to the vertical extensions 42. Therefore, the current path is not constrained by the reduced size of the cell. The vertical extension 42 can extend deeper into the trench 44 to further reduce the on-resistance; however, the gate-drain capacitance will increase, thereby reducing the switching speed.

FIG. 3B shows the use of the N-surface region 68 described above to further reduce the on-resistance.

Figure 3C shows the use of the P-shielding region 60 described above to increase the breakdown voltage.

FIG. 3D shows the use of P-column 64 and N-column 65 described above to reduce the on-resistance and increase the breakdown voltage.

FIG. 3E shows another embodiment similar to FIG. 3D, but the deep P+ region 70 is below the source junction deeper than the P-well region 38. The P+ region 70 establishes an ohmic junction with the source electrode 34 and electrically connects the P-well region 38 to the source electrode 34. The P+ region 70 is highly doped and reduces the gain of the parasitic NPN transistor, effectively preventing the parasitic NPN bipolar transistor from being turned on. By not allowing the NPN transistor to turn on, there is no thermal runaway caused by the high current through the NPN transistor, and no catastrophic secondary collapse occurs.

Figure 3F shows another embodiment similar to Figure 3D, but with a P-column 64 of multiple layers of P-charge balanced columns and an N-column 65 of N-charge balanced columns, a P-charge balanced column P-column 64A and N-charge balancing column 65A. By forming the P-columns and N-columns as a plurality of "thin" layers, there is less lateral dopant propagation, so the columns can be formed more accurately. Note how the lower P-column 64A is wider than the higher P-column 64 due to this extra thermal budget. More than two layers of P-columns and N-columns can be formed. Preferably, P-shielding region 60, N-column 65, P-column 64, N-layer 40, and N-drift region 48 are completely depleted at the onset of a collapse.

Figure 3G shows another embodiment similar to Figure 3C, but with floating P-shielding regions 60 and N-top layer 61 to improve switching speed.

Figure 3H shows another embodiment similar to Figure 3D, but with P-column 64 and N-column 65 without P-shielding regions to improve switching speed.

4A shows another embodiment similar to FIG. 3C, but with an L-shaped gate 36 to minimize overlap of gates 36, and a shield field plate 52 for lower gate-drain capacitance to increase switching speed. .

4B shows a particular embodiment of FIG. 4A, but with the different cross-sections showing the area where the shield field plate 52 is electrically connected to the source electrode 34. In other embodiments, the shield field plate 52 may be connected to the gate 36 (thus increasing capacitance) or floating.

4C shows another embodiment similar to FIG. 2B, but with a P-connection region 67 that electrically connects the P-shield region 60 to the P-well region 38 and the source electrode 34 to increase the switching speed.

As in these other embodiments, the vertical extension 42 of the gate 36 can extend any distance into the trench 44, including below the P-well region 38.

5A and 5B show a specific embodiment in which the shield field plate 52 is an extension of the gate 36. Since the voltage potential is much smaller near the top end of the trench 44, the thickness of the oxide layer 54 near the top end of the trench 44 (opposite the P-well region 38) can be less than the bottom of the trench, so there is no oxide layer. The collapse of 54.

Figure 5B shows a particular embodiment of Figure 5A, but with the P-column 64 and N-column 65 described above.

6A-6C show other embodiments of the P-well 38 coupling the sidewalls of the trench 44 such that the surface of the N-layer 40 is not directly below the gate 36. This device has a long composite lateral and vertical channel, wherein one of the channels is partially planar and the other portion is vertical. The horizontal and vertical portions of the gate 36 are used to invert the channel region. This gate-drain capacitance is reduced and the cell pitch is reduced, while also reducing the specified on-resistance. The devices of Figures 6A through 6C have longer channel lengths without increasing the effective surface area. These devices can have shallower junction depths and provide lower channel leakage current and lower saturation current, as well as a wider Safe Operating Area (SOA). The longer channel may also reduce the gain of the parasitic NPN transistor to improve by preventing secondary collapse. The durability of the device. The vertical shield field plate 52 may be connected to the source electrode 34, or to the gate 36, or to be floating.

Figure 6B shows the use of the aforementioned N-surface region 68.

Figure 6C shows that the gate 36 does not overlap the vertical shield field plate 52 to reduce capacitance, as previously described.

Figure 7A illustrates the equipotential lines in the depletion region between the substrate and the top surface of the device in Figure 2C in an off state at the beginning of the device collapse. The complete process flow and final device characteristics are simulated by 2D process/device simulation. The transition of the N-type dopants and the P-type dopants is shown by an outline corresponding to the P-shielding region 60 and the P-column 64. The vertical shield field plate 52 is connected to the source electrode 34. The specified on-resistance of 4.5 Ω per mm ² can be achieved for a breakdown voltage of 645V.

Figure 7B illustrates equipotential lines in the depletion region between the substrate and the top surface of the device in Figure 6A, wherein the edges of the P-well region 38 abut the trench sidewalls.

Figure 7C illustrates an equipotential line having an N-tip layer 61 (Figure 2E) in the depletion region between the substrate and the top surface of the device in Figure 2E.

Figure 8A is a top plan view of a portion of a vertical transistor incorporating any of the embodiments disclosed herein, wherein trench 44, gate 36 and the various doped regions (source region 46, P+ junction region 37, etc.) ) formed as an array of thin strips connected in parallel. Since the trench 44 occupies a region along the X direction, a limitation is imposed on the cell pitch reduction of the device. To alleviate this limitation, the trenches 44 can be arranged perpendicular to the gate 36 as shown in Figure 8B.

Figure 8C illustrates a single hexagonal closed monomer incorporating any of these specific embodiments herein. Adjacent cells share one of the walls of the straight trench 44 (like a honeycomb) and all of the cells are connected in parallel. In addition, other closed cell designs, such as squares, are also contemplated.

Figure 9A shows a specific embodiment similar to the previous one, but with a P+ substrate 80 to form an IGBT structure. In addition, the N-buffer layer 81 is also shown. In such a case, the drain electrode 32 becomes an anode or a collector. The PNP transistor is turned on by applying a threshold voltage to turn on the IGBT at the gate 36. IGBTs have lower on-resistance than these non-IGBT devices, but have slower switching speeds. Any of the foregoing devices can be fabricated as IGBTs.

Figure 9B shows a substrate 80 having a P+ region 82 and an N+ region 84 to form IGBT and DMOS transistor devices in parallel. The switching speed is improved compared to the IGBT of Figure 9A.

Figure 9C shows the structure of Figure 9B, but P-well 38 abuts the trench as previously described.

Figure 9D illustrates the use of an enhanced N-type region (N-top layer 61) between the bottom of trench 44 and P-shielding region 60 to improve the turn-off switching time of the IGBT.

Figure 9E illustrates the use of a relatively higher degree of doping P-column 64 and N-column 65 without the P-shielding region to reduce the on-resistance and turn off the switching time of the IGBT.

The possible process of the apparatus of Figure 3D is illustrated below in Figures 10A-10W. A similar process can be used to make any of these other specific embodiments.

In FIG. 10A, an epitaxial layer (N--drift region 48) is grown on top of the N++ substrate 50. The N--drift region 48 may be doped in situ during growth, or may be implanted periodically with an N-type dopant at a dose of about 1.5E12 cm" ² . Substrate 50 may have a dopant concentration of about 5E19 cm" ³ . For devices having a breakdown voltage of about 600 V, the final dopant density in the N-drift region 48 is about 3.5E14 cm ^-3 . The N--drift region 48 may be 30 microns thick.

In FIGS. 10B and 10C, a pad oxide layer 86 is formed and an N-type dopant 88 (eg, phosphorous) is implanted into the N--drift region 48, followed by (FIG. 10C) a masked P-type dopant 90. The implantation step (e.g., using boron) is to form N-column 65 and P-column 64. In addition, a photoresist mask 92 is displayed. The N-type implant dose may be approximately 1-2E12 cm ^-2 . The P-type implant dose may be approximately 1E13 cm ^-2 .

In FIG. 10D, the second epitaxial layer forming the N-layer 40 is grown after the photoresist and oxide are stripped. The N-layer 40 has a dopant density of about 2.3E15 cm ^-3 , which is higher than the dopant density in the N--drift region 48. The N-layer 40 is approximately 8 microns thick. In another embodiment, the dopant density in the N-layer 40 is substantially the same as in the N--drift region 48.

In FIG. 10E, an oxide hard mask 94 is formed on the top of the N-layer 40.

In Figure 10F, an additional thick oxide layer 96 is formed.

In FIG. 10G, a photoresist mask 98 is patterned over oxide layer 96, and oxide layer 96 and oxide hard mask 94 are dry etched to define the trench regions.

During the various steps, the dopants in N-column 65 and P-column 64 are driven in and diffused to form a column layer of about 4-5 microns thick, wherein The concentration of the N-type dopant in the N-column 65 is about 2E15 cm ^-3 , while the concentration of the P-type dopant in the P-column 64 is about 1E16 cm ^-3 . The dopant density in the N-column 65 may be greater or less than the N-layer 40.

In Figure 10H, the optional N-surface region 68 is implanted using a phosphorus or arsenic implant 100. Figure 10I shows the resulting N-surface region 68.

In FIG. 10J, a dry etch is performed to form trench 44, and a P-type dopant 102 (eg, boron) is implanted into trench 44 in a self-aligned manner at a dose of about 4E12 cm" ² to establish a P-shielded region. 60. The trench etch leaves an N-layer 40 of about 3-4 microns below the trench 44. At this step, an optional N-type dopant (e.g., arsenic) is implanted into the trench 44 in a self-aligned manner at a dose of about 2E12 cm<^2> to form an N-top layer over the P-shielding region 60.

In a particularly inventive step, the N-surface region 68 has been laterally diffused into the N-layer 40 and then etched to form the trenches 44. Thus, the N-surface region 68 is self-aligned with the trenches 44.

In FIG. 10K, a sacrificial oxide layer 104 is formed having a thickness of about 1000 angstroms.

In FIG. 10L, a field oxide (FOX) layer 106 is grown or deposited on the surface of the wafer including the mesa surface, the trench sidewalls, and the trench bottom. The FOX layer 106 has a thickness of about 6000 angstroms.

In FIG. 10M, a conductive polysilicon 108 (polysilicon) is deposited on the wafer to fill the trench 44, and then the polysilicon is etched back as shown in FIG. 10N. The polysilicon in trench 44 forms a vertical shield field plate 52.

In FIG. 10O, the field oxide (FOX) layer 106 of FIG. 10N is completely removed from the mesa surface by a wet etch or a wet/dry combination process and is removed along the sidewall portions of the trench 44. The remaining FOX layer separating the field plate 52 from the trench sidewalls now marks the oxide layer 54.

In FIG. 10P, gate oxide 56 is then grown to a thickness of about 900 angstroms.

In FIG. 10Q, the conductive polysilicon layer 110 is subsequently deposited.

In FIG. 10R, polysilicon layer 110 is patterned using photoresist mask 112 and etched to form gate 36 with vertical extensions 42.

In FIG. 10S, photoresist mask 112 is stripped and P-type dopant 114 (boron) is implanted into N-layer 40 to form P-well region 38 that is self-aligned with gate 36. The dopants are then embedded.

In FIG. 10T, an N-type dopant 116 (arsenic or phosphorous) is implanted to form an N++ source region 46 that is self-aligned with the gate 36.

In FIGS. 10U and 10V, a thick liner oxide and a borophosphorus glass (BPSG) layer 118 are formed to define a P+ junction region 37, and boron 120 is implanted.

In FIG. 10W, the source metal is deposited and patterned, for example, by sputtering aluminum copper (AlCu) or aluminum beryllium copper (AlSiCu) to form source electrode 34, and may be approximately 4 microns thick. Fig. 10W is the same as Fig. 3D.

The back metal is then deposited, for example, by sputtering a layer of titanium (Ti), nickel (Ni), and silver (Ag) each having a thickness of 1000, 2000, and 10,000 angstroms to form a drain electrode 32.

All figures shown are not drawn to scale for convenience of illustration. The actual device structure size and joint shape will depend on the required breakdown voltage, on-resistance, current requirements, etc., as shown in the above figures. The simulation results of Figures 7A and 7B show a more accurate representative size.

Any of the disclosed features can be combined in any combination in a MOSFET or IGBT to achieve these particular benefits of the feature for a particular application.

Although specific embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that modifications and modifications may be made without departing from the scope of the invention. The scope is within the true spirit and scope of this creation, and all such variations and modifications are covered within its scope.

30‧‧‧single

32‧‧‧汲electrode

34‧‧‧Source electrode

36‧‧‧ gate

37‧‧‧P+ junction area

38‧‧‧P-well area

40‧‧‧N-layer

42‧‧‧Vertical extension

44‧‧‧ trench

46‧‧‧ source area

48‧‧‧ drift zone

50‧‧‧Substrate

52‧‧‧ Field Board

53‧‧‧ dielectric

54‧‧‧Oxide layer

56‧‧‧gate oxide

S‧‧‧ spacing

Xj‧‧ depth

Claims (21)

A vertical transistor comprising: a semiconductor substrate having a first electrode on a bottom surface thereof; a first layer of a first conductivity type above the substrate, the first layer having a first dopant concentration; a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface; a trench a groove having a vertical sidewall coupled to the second layer; a well region of a second conductivity type on a top surface of the second layer, the well region having a top surface; the top surface of the well region a first region of a first conductivity type, wherein a region between the first region and an edge of the well region includes a channel for inversion by a gate; a conductive gate covering The channel establishes a lateral conductive path in the channel when the gate bias is above a threshold voltage, the gate having a vertical extension facing the vertical sidewall and isolated from the sidewall; a vertical a field plate facing the vertical sidewall of the second layer and the sidewall a second region, which is of the first conductivity type, surrounds and isolates the well region and extends to the trench of the vertical sidewall, the second region having a doping higher than the concentration of the second dopant Concentration of matter, which is to reduce on-resistance; a second electrode electrically contacting the well region and the first region, wherein a voltage is applied between the first electrode and the second electrode and the gate bias is higher than the threshold voltage A current flows through the channel and a current flows between the channel and the substrate. The transistor of claim 1, further comprising: a third layer of the first conductivity type between the first layer and the second layer and below the channel; and the second conductivity type a fourth layer that laterally adjoins the third layer on opposite sides of the third layer, a dopant concentration in the third layer and the fourth layer being higher than the first dopant concentration. The transistor of claim 2, further comprising a fifth layer of the second conductivity type, below the trench and laterally adjacent to the second layer. The transistor of claim 3, wherein the fifth layer is adjacent to the fourth layer. The transistor of claim 3, wherein the first layer is vertically spaced from the fourth layer. The transistor of claim 1, wherein the vertical field plate is electrically connected to the second electrode. The transistor of claim 1, wherein the gate has a vertical extension that faces and is isolated from the vertical sidewall, and wherein at least a portion of the vertical extension of the gate is facing The second zone. The transistor of claim 1, wherein the vertical field plate is electrically connected to the gate. The transistor of claim 1, wherein the vertical field plate is deeper than the well region. The transistor of claim 1, wherein the gate has a vertical extension that faces the vertical sidewall and is isolated from the sidewall, and wherein the vertical extension of the gate extends below the well region. The transistor of claim 1, wherein the well region extends to a vertical sidewall of the second layer. The transistor of claim 11, wherein the gate has a vertical extension that faces and is isolated from the vertical sidewall, and wherein the vertical extension of the gate is reversed adjacent to the vertical sidewall Part of the well area. The transistor of claim 1, further comprising a third region of the second conductivity type, below the trench and laterally adjacent to the second layer. The transistor of claim 1, further comprising a second region of the second conductivity type, which is below the trench and laterally adjacent to the second layer. The transistor of claim 1, wherein the substrate is of the first conductivity type, and wherein the transistor is a MOS field effect transistor (MOSFET). The transistor of claim 1, wherein the substrate is of the second conductivity type, and wherein the transistor is an insulated gate bipolar transistor (IGBT). The transistor of claim 1, wherein the vertical field plate and the second dopant concentration of the second layer are configured to enhance lateral depletion of the second layer such that the second layer is in the transistor A crash voltage is completely depleted. The transistor of claim 1, further comprising: a third layer of the first conductivity type between the first layer and the second layer and below the channel; and the second conductivity type a fourth layer that laterally adjoins the third layer on opposite sides of the third layer, a dopant concentration in the third layer and the fourth layer being higher than the first dopant concentration; Wherein the third layer and the fourth layer form an N-type and a P-type column, wherein the N-type and P-type columns are completely depleted in a breakdown voltage of one of the transistors. The transistor of claim 1, further comprising a third layer of the second conductivity type, under the trench and laterally adjacent to the second layer. The transistor of claim 1, further comprising: a third region of the second conductivity type, under the trench and laterally adjacent to the two layers; and a fourth region of the first conductivity type Between the third region and the trench and laterally adjacent to the second layer, wherein a dopant concentration in the fourth region is higher than the second dopant concentration in the second layer . The transistor of claim 1, wherein the first layer is formed on an epitaxial layer on the substrate.