CN207096860U - Linear voltage-controlled current source topological structure and sun battle array simulator - Google Patents

Abstract

The utility model discloses a kind of linear voltage-controlled current source topological structure and the sun battle array simulator applied to sun battle array simulator, and linear voltage-controlled current source topological structure includes：Three port linear power Darlingtons, three port linear power Darlingtons are made up of multiple N-channel open type JFET and N-channel closed type MOSFET cascades.The utility model is cascaded using multiple N-channel open type JFET and N-channel closed type MOSFET to substitute single tube power MOSFET, and the heat consumption power of each JFET power tube is limited by the clamper voltage-stabiliser tube from suitable drain-source voltage, therefore the number linear proportional example relation of the heat consumption power of single channel current source and cascade JFET, and the current source parallel connection way under the conditions of same nominal dissipated power and the cascade JFET linear inversely prroportional relationship of number, greatly reduce the parallel branch number of current source, the volume of sun battle array simulator can largely be optimized and simplify circuit structure.

Description

Linear voltage-controlled current source topological structure and sun battle array simulator

Technical field

It the utility model is related to sun battle array simulator technology field, more particularly to a kind of line applied to sun battle array simulator Property voltage-controlled current source topological structure and sun battle array simulator.

Background technology

Sun battle array simulator is generally divided into three basic links, power stage design, control system and benchmark generation technique. Power stage design framework is broadly divided into two kinds of frameworks, respectively linear power level framework and switch power level framework.In medium and small work( Under rate rating conditions, typically realized using linear power level framework, linear power level implementation is to use power crystal Pipe, controls it to work in linearly variable resistance area, so as to realize the characteristic of constant current output.And using multi-channel linear current source simultaneously The mode of connection is to improve the ability of its processing power, and the ability of its processing power depends on thermal control design, using linear power level The sun battle array simulator power supply output quality of architectural schemes is high, and dynamic property is excellent, is primarily adapted for use in space flight, military affairs etc. to the sun The higher occasion of battle array simulator test equipment dynamic performance requirements.

Typically use switch power level scheme in powerful application scenario, switching mode PV source simulators are in order to realize I-V For power curve output function, it is necessary to work in decompression mode, different switch power level photovoltaic source simulator switching mode topologys can To be single-phase DC-DC Buck converters, three-phase AC-DC voltage sources and current source rectifier, half-bridge and full-bridge DC-DC are converted Device, and LLC resonance DC-DC converters, there is the direct current programmable power electricity of other power stages topology such as belt current thresholding Source, dc power power supply or gate-controlled switch resistance and the active power load of belt variable resistor.Made using switch solution Realize that framework can handle higher power for sun battle array simulator power stage, suitable for general photovoltaic industry test occasion and The occasion not high to sun battle array simulator dynamic performance requirements.

Using the sun battle array simulator of linear power level scheme, typically exported using linear current type, and use multi-route Property voltage-controlled current source carry out parallel connection and improve power handling capability., can be complete due to being limited by volume and space physics size Into way in parallel it is limited, power output is typically small, requires higher suitable for dynamic characteristic and exports simulation I-V precision religion The middle low power occasion led.

Summarize implementation above sun battle array simulator two kinds realize framework scheme, the sun battle array simulation of linear power level scheme Utensil has excellent dynamic characteristic, and the voltage x current simulation precision of simulator output is higher, but subjected to power constraints, and Efficiency is low, produces substantial amounts of heat, bulky, so being difficult to apply to large-power occasions.

Although switch power level scheme efficiency high, the ability of high-power processing can be achieved, relative to linear power level The output voltage current ripples of scheme are larger, and power supply quality is general；And dynamic property is poor, it is not suitable for high-power and high The occasion of dynamic characteristic demand.

But the occasion higher to the dynamic response of test power supply and power output required precision such as space flight and military affairs is directed to, Switching power level scheme can not meet the index request, typically use linear power level scheme.Existing linear power level side Case topology is difficult to accomplish the fan-out capability of relatively high power, and in order to improve the ability of processing power, using multi-channel linear electric current Source carries out scheme in parallel to realize.But due to the limitation of volume and space physics distance, the linear power of in general design Level topology can not realize the parallel connection of more way, and select optimization method without the transistor of complete linear current source.

Utility model content

Main purpose of the present utility model is that providing a kind of linear voltage-controlled current source applied to sun battle array simulator opens up Structure and sun battle array simulator are flutterred, to optimize the sun battle array simulator of linear power level, reduces the parallel branch of linear current source Number, it can largely optimize the volume of sun battle array simulator and simplify circuit structure.

In order to achieve the above object, the utility model proposes a kind of linear voltage-controlled current source applied to sun battle array simulator Topological structure, including：Three port linear power Darlingtons, the three port linears power Darlington is by multiple N ditches Road open type JFET and N-channel closed type MOSFET cascades are formed.

Wherein, the three port linears power Darlington serves as cascaded-branch by a N-channel closed type MOSFET Least significant end power transistor M, and some same models cascaded with M phases N-channel open type JFET form.

Wherein, the N-channel open type JFET is at least 5.

Wherein, the voltage-stabiliser tube phase of same model is used between the grid between each JFET and the adjacent JFET in upper end source electrode Connect.

Wherein, it is connected with current-limiting resistance between the voltage-stabiliser tube and corresponding JFET source electrode.

Wherein, the both ends of the voltage-stabiliser tube, which are parallel with, eliminates noise electric capacity.

The utility model also proposes a kind of sun battle array simulator, including linear voltage-controlled current source topology knot as described above Structure.

The utility model devises a kind of linear voltage-controlled current source topological structure and the sun applied to sun battle array simulator Battle array simulator, it can be applicable in the systems such as new energy, inverter power supply test, spacecraft power supply test, using new cascade Formula JFET linear power level current sources topological project topology, provide reality of the optimization applied to the linear power level of sun battle array simulator Existing scheme, realizes sun battle array simulator power density and high dynamic response characteristic, using multiple N-channel open type JFET and N ditches Road closed type MOSFET is cascaded to substitute single tube power MOSFET, and the heat consumption power of each JFET power tube passes through selection The clamper voltage-stabiliser tube of suitable drain-source voltage limits, thus the heat consumption power of single channel current source and cascade JFET number into Linear proportional relationship, and the current source parallel connection way under the conditions of same nominal dissipated power and cascade JFET number are linear Inversely prroportional relationship, greatly reduce the parallel branch number of current source, so as to largely optimize the body of sun battle array simulator Product and simplified circuit structure.

Brief description of the drawings

Fig. 1 a are the utility model to be polarized code encoding method embodiment schematic flow sheet based on punching without speed；

Fig. 1 b are three port linear power composite transistor circuit knots of the linear voltage-controlled current source of the utility model Optimization-type Composition；

Fig. 2 a and Fig. 2 b are circuit work corresponding to the change of the port hybrid power transistor voltage of linear current source three respectively Make view；

Fig. 3 is with the change feelings of each JFET voltages corresponding to three port composite crystal tube voltage Vdrain change Condition schematic diagram；

Fig. 4 is linear voltage-controlled current source operation principle curve synoptic diagram；

Fig. 5 figures be based on compound power transistor cascade JFET number be p (p >=5) current source parallel connection way be N (N >= 4) sun battle array simulator realization principle schematic diagram of linear power level topology；

Fig. 6 is the sun battle array simulator output characteristic curve using novel linear power topology.

In order that the technical solution of the utility model is clearer, clear, it is described in further detail below in conjunction with accompanying drawing.

Embodiment

It should be appreciated that specific embodiment described herein is not used to limit this only to explain the utility model Utility model.

The utility model can be applicable in the systems such as new energy, inverter power supply test, spacecraft power supply test, using new The tandem type JFET linear powers level topology of type, method of the optimization applied to the linear power level of sun battle array simulator is provided, it is real Existing sun battle array simulator power density and high dynamic response characteristic.Linear power level typically uses the single power form of tubes in many roads The mode in parallel of linear current source improve power grade demand, the parallel-current source of excessive way can cause sun battle array mould The volume of plan device is larger, and the increase of the space physics distance between current source can cause the difference of electric property between each current source The opposite sex is larger.For the problem, the utility model proposes a kind of new linear current source topological project, using multiple N raceway grooves Open type JFET and N-channel closed type MOSFET is cascaded to substitute single tube power MOSFET, and the heat of each JFET power tube Wasted work rate is limited by the clamper voltage-stabiliser tube from suitable drain-source voltage, therefore the heat consumption power of single channel current source and cascade JFET number linear proportional example relation, and the current source parallel connection way under the conditions of same nominal dissipated power and cascade JFET The linear inversely prroportional relationship of number, greatly reduce current source parallel branch number, so as to largely optimize the sun The volume of battle array simulator and simplified circuit structure.

Specifically, reference picture 1a, Fig. 1 a are the electrical block diagrams of the linear voltage-controlled current source of the utility model Optimization-type Schematic diagram.

As shown in Figure 1a, the utility model proposes a kind of new linear voltage-controlled current source applied to sun battle array simulator Topological structure, for the voltage-controlled current source of in general high side current type output, the utility model is brilliant by single power Body pipe (typically using N-channel power MOSFET) replaces with cascade connection type N raceway groove open type JFET and N-channel normally-off MOSFET Composite line Linear power transistor.

Specifically, the linear voltage-controlled current source topological structure includes：Three port linear power Darlingtons, three end Mouth linear power Darlington is made up of multiple N-channel open type JFET and N-channel closed type MOSFET cascades.

Wherein, the three port linears power Darlington serves as cascaded-branch by a N-channel closed type MOSFET Least significant end power transistor M, and some same models cascaded with M phases N-channel open type JFET form.Such as Fig. 1 b institutes Show, figure Fig. 1 b are three port linear power composite transistor circuit structures of the linear voltage-controlled current source of the utility model Optimization-type Figure.

As a kind of preferred scheme, the N-channel open type JFET is at least 5.

Wherein, the voltage-stabiliser tube phase of same model is used between the grid between each JFET and the adjacent JFET in upper end source electrode Connect.Current-limiting resistance is connected between the voltage-stabiliser tube and corresponding JFET source electrode.The both ends of the voltage-stabiliser tube are parallel with elimination Noise electric capacity.

As shown in Fig. 2 the utility model proposes three port linear power Darlingtons be by a N-channel normally-off Power MOSFET serves as the least significant end power transistor M of cascaded-branch；The N-channel for series of identical model cascaded with M phases Open type JFET forms J₁~J_p(p≥5)；And used between the source electrode of the adjacent JFET of grid and upper end between each JFET The voltage-stabiliser tube of same model connects, respectively Z₁~Z_p-1；And R_z1~R_zp-1It is equal for the current-limiting resistance of voltage-stabiliser tube, each resistance It is R to be consistent_z, it is ensured that corresponding voltage-stabiliser tube can securely and reliably work in reverse breakdown regulation region；C_z1~ C_zp-1For the elimination noise electric capacity of each voltage-stabiliser tube, typically in pF ranks, its capacitance is smaller and capacitance is in the same size, is C_z。

The three port linears power Darlington operation principle is：

It can ensure that M works in linear saturation region, M gate source voltage control by controlling the voltage between M grid and source electrode The size of whole piece branch power electric current processed.As the voltage for the equivalent drain drain for being added in Darlington gradually rises, work( Rate branch current is constant, and M drain-source voltage gradually rises, so as to control the adjacent JFET in upper end to be progressed into linearly by normally opened Saturation region, and by M drain-source voltage clamper to J₁Source electrode and grid between voltage.

Similarly, then with the drain voltage of Darlington further improve, voltage-stabiliser tube Z₁Voltage stabilizing state is progressed into, will The J of adjacent low side₁Drain-source voltage clamper in fixed voltage value.Similarly by that analogy, Z₂By J₂Drain-source voltage carry out clamper, Z_p-1By J_p-1Drain-source voltage carry out clamper, and the JFET drain-source voltages of most flash are the drain voltage of be added in Darlington With each voltage-stabiliser tube difference in voltage into voltage stabilizing working condition.

By the substantially description of above-mentioned operation principle, it is equivalent to one for Darlington and works in linear saturation region Power transistor, the power current of the voltage-controlled current source topology merging branch road keep constant, as long as therefore voltage-controlled current source Given reference control voltage keeps constant, and the electric current that the hybrid power transistor flows through keeps constant.There is above-mentioned operation principle again Description, each power JFET voltage is substantially by voltage-stabiliser tube clamper in a certain fixed voltage value, then each JFET works In the dissipated power corresponding to linear saturation region be confirmable.

For example, it is assumed that the single channel for the traditional voltage-controlled current source being not optimised can dissipated power be 30W, single power JFET works Make in linear saturation region maximum can dissipated power be 30W, compound transistor npn npn forms (p=5) by 5 JFET cascades.It is then former To need the linear power level unit of dissipation 600W power, parallel connection is carried out to complete using traditional voltage-controlled current source branch road, needed 20 road current sources carry out in parallel；And use Optimization-type voltage-controlled current source scheme, single channel current source can with dissipation 150W power, Need only to 4 road voltage-controlled current source branch roads and carry out the demand in parallel that can complete power dissipation rating.So as to greatly reduce The parallel branch number of linear voltage-controlled current source, while the circuit structure of linear power level unit can be greatly simplified, reduce electricity The space physics distance of control circuit between the branch road of stream source, be advantageous to improve the control essence of linear power level unit output current Degree.

The electricity that the specific compound transistor power branch road of three port powers changes with the change of equivalent drain voltage As shown in Figure 2 a and 2 b, Fig. 2 a are as the voltage Vdrain of three port hybrid power tubes is gradual for road working condition concrete analysis I during increase, II, tri- status circuit operating diagrams of III, Fig. 2 b are with the voltage of three port hybrid power tubes IV during the gradual increases of Vdrain, tri- status circuit operating diagrams of V, VI.

Compound power transistor is cascaded by the JFET of p (p >=5) individual same model in Fig. 2 a and Fig. 2 b, p-1 phase With the voltage-stabiliser tube Z of model₁~Z_p-1, it is equal into the voltage of the voltage stabilizing state of reverse breakdown, respectively V_ZT1=V_ZT2=...= V_ZTp-1=V_ZT；Current-limiting resistance all same, that is, have R corresponding to each voltage-stabiliser tube_z1=R_z2=...=R_zp-1=R_z；Each de-noising electricity Hold all same, that is, have C_z1=C_z2=...=C_zp-1=C_z.Working condition is simply divided into six stages, respectively to each stage Circuit state is analyzed as follows.

State I are first state, now V_drain≤|V_P|, wherein V_PMagnitude of voltage is blocked for JFET.Wherein at M In linear saturated, J₁~J_pWorking condition is on, it is as follows to there is equation：

V_{ds_M}=V_drain (1)

With V_drainBe gradually increasing, initially enter second stage state State II, now | V_P|<V_drain≤V_ZD1 Wherein V_ZD1For Z₁Just into the magnitude of voltage at lower state moment, define such as formula：

V_DZ1=I_{ZT_min}R_z+V_ZT (2)

Wherein：

I_{ZT_min}The minimum electric current of voltage regulation value entered for voltage-stabiliser tube required for voltage stabilizing state；

V_ZTFor the reverse breakdown voltage stabilizing value of voltage-stabiliser tube.

The state II states, M, J₁In linear saturated, J₂~J_pIt is on working condition, Z₁Start Voltage stabilizing working condition is progressed into, equation such as following formula can be arranged to obtain：

Wherein I_z1To flow into voltage-stabiliser tube Z₁Reverse leakage current, V_Z1For voltage-stabiliser tube Z₁Into before reverse breakdown voltage stabilizing state Both ends magnitude of voltage.

State III circuit states as shown in Figure 2 a, now V_ZD1<V_drain≤V_ZD2Wherein V_ZD2For Z₂Just into stable state The magnitude of voltage at state moment, is defined such as formula：

V_DZ2=I_{ZT_min}R_z+2V_ZT (4)

M, J₁, J₂In linear saturated, J₃~J_pIt is on working condition, Z₁In voltage stabilizing working condition, Z₂Start to progress into voltage stabilizing working condition, it is as follows that the equation obtained under the state can be arranged：

Wherein I_z2To flow into voltage-stabiliser tube Z₂Reverse leakage current, V_Z2For voltage-stabiliser tube Z₂Into before reverse breakdown voltage stabilizing state Both ends magnitude of voltage.

State IV circuit states as shown in Figure 2 b, now V_ZD2<V_drain≤V_ZD3Wherein V_ZD3For Z₃Just into stable state shape The magnitude of voltage at state moment, is defined such as formula：

V_DZ3=I_{ZT_min}R_z+3V_ZT (6)

M, J₁, J₂, J₃In linear saturated；J₄~J_pIt is on working condition；Z₁, Z₂Worked in voltage stabilizing State；Z₃Start to progress into voltage stabilizing working condition, and it is as follows to arrange the equation obtained under the state：

Wherein I_z3To flow into voltage-stabiliser tube Z₃Reverse leakage current, V_Z3For voltage-stabiliser tube Z₃Into before reverse breakdown voltage stabilizing state Both ends magnitude of voltage.

State V circuit states as shown in Figure 2 b, now V_ZDp-2<V_drain≤V_ZDp-1Wherein V_ZDp-1For Z_p-1Just into steady The magnitude of voltage at state state moment, is defined such as formula：

V_DZp-2=I_{ZT_min}R_z+(p-2)V_ZT (7)

V_DZp-1=I_{ZT_min}R_z+(p-1)V_ZT (8)

M, J₁..., J_p-1In linear saturated；J_pIt is on working condition；Z₁, Z₂..., Z_p-2In steady Press working condition；Z_pStart to progress into voltage stabilizing working condition, and it is as follows to arrange the equation obtained under the state：

Wherein I_zp-1To flow into voltage-stabiliser tube Z_p-1Reverse leakage current, V_Zp-1For voltage-stabiliser tube Z_p-1Into reverse breakdown voltage stabilizing shape The magnitude of voltage at the both ends before state.

State V circuit states as shown in Figure 2 b, now V_drain＞ V_ZDp-1；M, J₁..., J_pIn linear saturation work shape State；Z₁, Z₂..., Z_p-1In voltage stabilizing working condition, and it is as follows to arrange the equation obtained under the state：

And six states can obtain waveform diagram as shown in figure 3, Fig. 3 is with three port composite crystal tube voltages above The situation of change schematic diagram of each JFET voltages corresponding to Vdrain change.

V_drainConstantly slowly from zero increase, respectively by six states.In state I, low side MOSFET V_{ds_M}Both ends Voltage is V_drain, the two waveform is consistent, to V_drainReach | V_P| when, M drain-source voltages, which are clamped, keeps constant.Into state I I When, J₁Initially enter linear saturation region operation state, V_{ds_J1}The voltage and V at end_drainBetween differ a grid source driving voltage- V_{gs_J1}, dotted line uphill process part and V_drainIt is equal, work as Z₁During into reverse breakdown voltage stabilizing state, V_{ds_J1}It is solid to be clamped at one Determine magnitude of voltage.During into state I II, J₂Initially enter linear saturation region operation state, V_{ds_J2}The voltage and V at end_drainAscent stage Between differ a grid source driving voltage-V_{gs_J2}, dotted line uphill process part and V_drainAscent stage is equal, works as Z₂Into reversely hitting When wearing voltage stabilizing state, V_{ds_J2}It is clamped at a fixed voltage value.During into state I V, J₃Initially enter linear saturation region operation State, V_{ds_J3}The voltage and V at end_drainA grid source driving voltage-V is differed between ascent stage_{gs_J3}, dotted line uphill process part With V_drainAscent stage is equal, works as Z₃During into reverse breakdown voltage stabilizing state, V_{ds_J3}It is clamped at a fixed voltage value.And with this Analogize, continuous one-level one-level removes respectively V_drainVoltage, so as to effectively control each power JFET dissipated power, It is p times of traditional single tube linear current source to realize the accessible power grade of single channel current source.

The ideal operation math equation expression formula of the linear voltage-controlled current source of the Optimization-type such as formula (11)：

Wherein U_IrefFor the control voltage of voltage-controlled current source, the electric current I with power circuit_pathProportional relation.Steady operation Curve is as shown in figure 4, Fig. 4 is linear voltage-controlled current source operation principle curve synoptic diagram.

Wherein #1 is given reference voltage U_IrefVersus time curve, #2 positions output current I_pathChange with time Curve.Wherein I_pathWith U_IrefChange and change, and in Fig. 4 operating point A and operating point B reference voltage and output current Proportionate relationship is consistent.U simultaneously_IrefWith I_pathSynchronism it is excellent, i.e. I_pathU can be tracked without time phase with being delayed_Iref Change and change.

Realize that less way completion sun battle array simulator in parallel is defeated using the linear voltage-controlled current source of Optimization-type set forth above Go out function, its system construction drawing as shown in figure 5, Fig. 5 be based on compound power transistor cascade JFET number be p (p >=5) The sun battle array simulator realization principle schematic diagram for the linear power level topology that current source parallel connection way is N (N >=4).

The sun battle array simulation system is divided into two major parts, respectively linear power level unit and high speed digital controller list Member.

Linear power level unit is to be made up of the linear voltage-controlled current source parallel connections of N and N >=4, multi-channel linear voltage-controlled current source Parallel connection does not interfere with the bandwidth of whole power stage not only, and can greatly increase the power handling capability of linear power level, can To realize the high dynamic characteristic under high-power output condition.The benchmark of the linear voltage-controlled current sources of wherein N is common reference U_Iref, shown in the mathematical relationship such as formula (12) of reference voltage and total current：

High speed digital controller reduces numeral using high-speed digital-analog conversion ADC and high speed analog-digital conversion DAC and high speed FPGA Be delayed influences on the loop of whole simulation system.The simulator output end voltage that high speed FPGA is provided by difference sample circuit Using domestic signal, carry out I-V forms and table look-up, provide the electric current output reference value of work at present moment needs, and pass through at a high speed DAC is converted to analog voltage reference and is sent into linear power level unit.The benchmark I-V curve and simulator of sun battle array simulator work The power I-V curve that output interface externally exports is as shown in fig. 6, Fig. 6 is the sun battle array simulation using novel linear power topology Device output characteristic curve.

Wherein #3 is simulator output end sampled voltage U_{sas_sa}The reference voltage U provided with DAC_IrefBetween relation, obtain The simulator power output I-V curve arrived is that simulator is according to output voltage U shown in #4_sasExport controllable power current I_sas。 By using the linear voltage-controlled current source and high speed FPGA digitial controllers of high bandwidth, it is possible to achieve the output of sun battle array simulator High dynamic response characteristic, can with fast reaction output end shunt cut carry under the conditions of I-V curve on operating point switch.

The utility model is opened up based on a kind of linear voltage-controlled current source of the compound linear power transistors of New Cascading JFET Structure is flutterred, analyzes and gives the operation principle of the design and the organization plan applied to solar array simulator occasion. The new type compound linear power transistor proposed is using p JFET cascaded-branch come equivalence replacement conventional linear current source list The method of individual power transistor, its dissipated power relative to the dissipated power under the equal conditions of traditional single channel current source p Times.The current source number of parallel under equal-wattage rating conditions can greatly be reduced, so as to largely optimize solar energy The machine volume size and circuitry structure of array simulator, are advantageous to centralized heat dissipation design.Linear voltage-controlled current source is adopted With new controling circuit structure, the parallel connection being equally beneficial between multipath current-source, can further carry on this basis The dissipated power grade of High Linear power stage unit, it can further improve at the rated power of sun battle array simulator of linear arrangement Reason ability.And same linear power level scheme, it can both ensure that sun battle array simulator possessed preferably output current simulation Precision, the dynamic property of sun battle array simulator will not also be had an impact, the output current essence of its higher dynamic response capability Degree can equally go to test spacecraft power supply system with preferably working condition.The sun battle array simulator of the design uses high bandwidth Linear power level and high speed digitial controller unit, not only possess the dynamic property of superelevation, and the power current exported Ripple-free is high to power I-V curve simulation precision.

In addition, the utility model embodiment also proposes a kind of sun battle array simulator, including linear voltage-controlled electricity as described above Stream source topological structure, will not be repeated here.

Preferred embodiment of the present utility model is the foregoing is only, not thereby limits the scope of the claims of the present utility model, Every equivalent structure made using the utility model specification and accompanying drawing content or flow conversion, or be directly or indirectly used in Other related technical fields, are similarly included in scope of patent protection of the present utility model.

Claims (7)

1. A kind of 1. linear voltage-controlled current source topological structure applied to sun battle array simulator, it is characterised in that including：Three port lines Property power Darlington, the three port linears power Darlington are normally closed by multiple N-channel open type JFET and N-channel Type MOSFET cascades are formed.
2. 2. the linear voltage-controlled current source topological structure according to claim 1 applied to sun battle array simulator, its feature exists In the three port linears power Darlington is served as the least significant end work(of cascaded-branch by a N-channel closed type MOSFET Rate transistor M, and the N-channel open type JFET of some same models cascaded with M phases are formed.
3. 3. the linear voltage-controlled current source topological structure according to claim 2 applied to sun battle array simulator, its feature exists In the N-channel open type JFET is at least 5.
4. 4. the linear voltage-controlled current source topological structure according to claim 2 applied to sun battle array simulator, its feature exists In being connected between the source electrode of the adjacent JFET of grid and upper end between each JFET using the voltage-stabiliser tube of same model.
5. 5. the linear voltage-controlled current source topological structure according to claim 4 applied to sun battle array simulator, its feature exists In being connected with current-limiting resistance between the voltage-stabiliser tube and corresponding JFET source electrode.
6. 6. the linear voltage-controlled current source topological structure according to claim 4 applied to sun battle array simulator, its feature exists In the both ends of the voltage-stabiliser tube, which are parallel with, eliminates noise electric capacity.
7. 7. a kind of sun battle array simulator, it is characterised in that including the linear voltage-controlled current source any one of claim 1-6 Topological structure.