CN206948284U - A kind of gate quenching circuit of ultralow threshold value - Google Patents
A kind of gate quenching circuit of ultralow threshold value Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 239
- 229910052738 indium Inorganic materials 0.000 claims description 6
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- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
The utility model discloses a kind of gate quenching circuit of ultralow threshold value, including charging valve metal-oxide-semiconductor M2, quenching tube metal-oxide-semiconductor M1 and multiple metal-oxide-semiconductors.Ultralow threshold value of the present utility model gates quenching circuit, can detect faint avalanche current signal, can be light（Secretly）The avalanche current moment of carrier triggering is amplified to more than one NMOS threshold voltage, makes the voltage at SPAD both ends by more than avalanche breakdown voltage being down to below avalanche breakdown voltage, and then avalanche current is quenched.Compared with traditional voltage amplification, the response time of the utility model circuit is shorter, thus more can effectively reduce dead time and afterpulse effect.
Description
Technical field
A kind of quenching circuit is the utility model is related to, belongs to field of circuit technology.
Background technology
Laser radar is a kind of active probing technique that can accurately and quickly obtain ground or air three-dimensional spatial information,
Can be used for carrying out ranging angle measurement etc., thus its in military and civilian field to being widely applied.Visited using traditional large area array
The Non-scanning mode imaging laser radar for surveying device is to be based on linear APD (Avalanche Photo Diode) principle, and it can be with very high
Speed imaging, but need high power laser irradiate target, so operating distance will not be too remote.
(reverse-biased is crossed when the bias voltage at APD both ends is more than avalanche breakdown voltage), and a photo-generated carrier can
The self-sustaining avalanche current of trigger electrode large gain, i.e. APD are operated in Geiger mode angular position digitizer.It is this quickly to be triggered by single photo-generated carrier
Caused detectable avalanche current so that APD can realize effective detection of single photon.Therefore, based on large area array Geiger (GM) APD
Laser radar not only image taking speed is fast, can constantly catch dynamic object, and very remote distance can be acted on, realize super
Remote imaging.The high sensitivity APD being operated under Geiger pattern is referred to as single-photon avalanche diode (Single Photo
Avalanche Diode,SPAD)。
The SPAD detectors of large area array need supporting large area array laser radar reading circuit, and domestic laser radar is read at present
Go out circuit still based on discrete device, thus it is small, and resolution ratio and imaging rate are relatively low.Battle array scale reaches face to face
During 64x64 pixel cell even more highs, laser radar reading circuit can only use single chip integrated method to realize.It is measured
CMOS technology realizes large area array laser radar readout circuit chip, can reduce the volume of control system, mitigate weight, reduces work(
Consumption, antijamming capability, increase reliability are improved, the high-precision time point is obtained while realizing and the high frame rate of target is captured
Resolution.
When SPAD was in it is reverse-biased when, due to the triggering of photon, SPAD can be produced from follow current.If do not take any
Braking measure, avalanche process will continue until device permanent damage.So generally after avalanche multiplication effect generation
The quick voltage for reducing SPAD both ends is needed to suppress snowslide.
The effect of SPAD quenching circuits is exactly the data signal for being quickly detected avalanche current and extracting a standard, together
When reduce below SPAD reversed bias voltage to avalanche voltage, and then avalanche current is quenched.The performance of quenching circuit directly affects spy
The entirety of examining system.
Utility model content
Limited by existing SPAD material properties and domestic manufacturing process, the electric current that single photon triggers nearly mA levels is difficult reality
It is existing；The inconsistent uniformity of face battle array SPAD avalanche breakdown voltages is considered simultaneously, and some pixel cell photon trigger currents may
Less than 0.1mA.So, tradition gate quenching circuit is difficult to avalanche current is quenched or the response time is very long, adds the dead time.This
Utility model is in order to solve existing technical problem, there is provided a kind of ultralow threshold value gates quenching circuit, can detect faint snow
Collapse current signal.Passively it is quenched with traditional resistance, compared with control mode is quenched in active and mixing, gate mode can make SPAD
Under working in reverse-biased pattern in only hearing when of short duration, thus SPAD service life and reliability are improved, and imitate and reduce
Device dark count rate.
In order to solve the above technical problems, the utility model provides a kind of gate quenching circuit of ultralow threshold value, it is characterized in that,
Including charging valve metal-oxide-semiconductor M2, quenching tube metal-oxide-semiconductor M1, metal-oxide-semiconductor M3, M4, M5, M6, M7, M8, M9, M10 and M11；
Metal-oxide-semiconductor M2 and metal-oxide-semiconductor M1 drain electrode is connected to A points and metal-oxide-semiconductor M3 source electrode altogether；Metal-oxide-semiconductor M1 source electrode connects power supply
VDD；Metal-oxide-semiconductor M2 source ground；Metal-oxide-semiconductor M2 grid connects ARM signals；Metal-oxide-semiconductor M1 grid connects E points as quenching circuit
STOP is exported, while is connected to the output end of metal-oxide-semiconductor M11 drain electrode, metal-oxide-semiconductor M4 drain electrode and constant-current source I, constant-current source I's is defeated
Enter end and be connected to power supply ADD；Metal-oxide-semiconductor M3 grid connectsSignal, metal-oxide-semiconductor M3 drain electrode are connected to B points and metal-oxide-semiconductor M7
The drain electrode of source electrode, metal-oxide-semiconductor M5, metal-oxide-semiconductor M5 source grounds；Metal-oxide-semiconductor M11 source electrode meets power supply ADD, and metal-oxide-semiconductor M11 grid connectsSignal；Metal-oxide-semiconductor M4 source grounds, metal-oxide-semiconductor M4 grid connect D points and metal-oxide-semiconductor M7, M9 drain electrode contact altogether；Metal-oxide-semiconductor M9's
Source electrode connects power vd D, metal-oxide-semiconductor M9 grid tie point C and metal-oxide-semiconductor M10 grid and drain electrode, metal-oxide-semiconductor M8 drain electrode, metal-oxide-semiconductor
M10 source electrode meets power vd D；Metal-oxide-semiconductor M7 grid and metal-oxide-semiconductor M8 grid, the grid of metal-oxide-semiconductor M5 grid and metal-oxide-semiconductor M6
VC is connected to altogether, and metal-oxide-semiconductor M8 source electrode is connected to metal-oxide-semiconductor M6 drain electrode, metal-oxide-semiconductor M6 source ground.
A points are connected by indium post with SPAD.
ARM signals export after phase inverterSignal.
Metal-oxide-semiconductor M9 and M10 breadth length ratio are equal.
Metal-oxide-semiconductor M7 breadth length ratios are n times of metal-oxide-semiconductor M8, n>1.
Metal-oxide-semiconductor M5 breadth length ratios are n times of metal-oxide-semiconductor M6, n>1.
A kind of gate quenching circuit of ultralow threshold value, it is characterized in that, including charging valve metal-oxide-semiconductor M2, quenching tube metal-oxide-semiconductor M1,
Metal-oxide-semiconductor M4, M5, M6, M7, M8, M9, M10, M11, M12, M13 and M14；
Metal-oxide-semiconductor M2 and metal-oxide-semiconductor M1 drain electrode is connected to A points altogether；Metal-oxide-semiconductor M1 source electrode meets power vd D；Metal-oxide-semiconductor M2 source electrode
Ground connection；Metal-oxide-semiconductor M2 grid connects ARM signals；Metal-oxide-semiconductor M1 grid meets output STOP of the E points as quenching circuit, connects simultaneously
The drain electrode of drain electrode, metal-oxide-semiconductor M4 and constant-current source I output end to metal-oxide-semiconductor M11, constant-current source I input are connected to power supply ADD；
The drain electrode of metal-oxide-semiconductor M7 source electrode, metal-oxide-semiconductor M5 is connected to B points altogether, is connected through B points with A points；The leakage of metal-oxide-semiconductor M5 source electrodes and metal-oxide-semiconductor M13
Pole connects, and metal-oxide-semiconductor M13 source ground, metal-oxide-semiconductor M13 grid is connected to E points；Metal-oxide-semiconductor M11 source electrode meets power supply ADD, MOS
Pipe M11 grid connectsSignal；Metal-oxide-semiconductor M4 source electrodes are connected to metal-oxide-semiconductor M12 drain electrode, and metal-oxide-semiconductor M12 grid connects
Signal, metal-oxide-semiconductor M12 source ground, metal-oxide-semiconductor M4 grid connect D points and metal-oxide-semiconductor M7, M9 drain electrode contact altogether；Metal-oxide-semiconductor M9 source
Pole meets power vd D, metal-oxide-semiconductor M9 grid tie point C and metal-oxide-semiconductor M10 grid and drain electrode, metal-oxide-semiconductor M8 drain electrode, metal-oxide-semiconductor M10
Source electrode meet power vd D；The grid of metal-oxide-semiconductor M7 grid and metal-oxide-semiconductor M8 grid, metal-oxide-semiconductor M5 grid and metal-oxide-semiconductor M6 connects altogether
VC is connected to, metal-oxide-semiconductor M8 source electrode is connected to metal-oxide-semiconductor M6 drain electrode, and metal-oxide-semiconductor M6 source electrode is connected to metal-oxide-semiconductor M14 drain electrode, MOS
Pipe M14 grid connects power vd D, metal-oxide-semiconductor M14 source ground.
Metal-oxide-semiconductor M13 breadth length ratios are n times of metal-oxide-semiconductor M14, n>1.
A points are connected by indium post with SPAD.
ARM signals export after phase inverterSignal.
The beneficial effect that the utility model is reached：
Ultralow threshold value of the present utility model gates quenching circuit, can detect faint avalanche current signal.With traditional
Resistance is passively quenched, active is quenched control mode with mixing and compared, gate mode can make SPAD only hear when of short duration in work
Made under reverse-biased pattern, thus improve SPAD service life and reliability, and imitate reduction device dark count rate.This practicality
The avalanche current moment that light (dark) carrier triggers can be amplified to more than one NMOS threshold by new gate quenching circuit
Threshold voltage, make the voltage at SPAD both ends by more than avalanche breakdown voltage being down to below avalanche breakdown voltage, and then snowslide electricity is quenched
Stream.Compared with traditional voltage amplification, the response time of the utility model circuit is shorter, thus more can effectively reduce the dead time
With afterpulse effect.
Brief description of the drawings
The quenching circuit of Fig. 1 embodiments of the present utility model；
The timing diagram of Fig. 2 quenching circuits；
The quenching circuit of Fig. 3 another embodiments of the present utility model.
Embodiment
The utility model is further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating this
The technical scheme of utility model, and the scope of protection of the utility model can not be limited with this.
Embodiment 1
The each pixel cell of large area array laser radar includes a reading circuit unit and a corresponding SPAD detection
Device unit.Wherein, reading circuit unit is made up of quenching circuit and timing circuit.SPAD anode passes through indium post and quenching circuit
It is connected, the SPAD external reversed bias voltage VB of negative electrode, the output STOP of quenching circuit are the timing stopping mark of timing circuit.
Quenching circuit of the present utility model is as shown in figure 1, including charging valve metal-oxide-semiconductor M2, quenching tube metal-oxide-semiconductor M1, metal-oxide-semiconductor
M3, M4, M5, M6, M7, M8, M9, M10 and M11.Metal-oxide-semiconductor M2 and metal-oxide-semiconductor M1 drain electrode is connected to A points and metal-oxide-semiconductor M3 source electrode altogether,
It is connected through A points by indium post with SPAD；Metal-oxide-semiconductor M1 source electrode meets power vd D；Metal-oxide-semiconductor M2 source ground；Metal-oxide-semiconductor M2 grid
Pole connects ARM signals；Metal-oxide-semiconductor M1 grid meets output STOP of the E points as quenching circuit, while is connected to metal-oxide-semiconductor M11 leakage
The output end of pole, metal-oxide-semiconductor M4 drain electrode and constant-current source I, constant-current source I input are connected to power supply ADD.Metal-oxide-semiconductor M3 grid
Connect what ARM signals exported after phase inverterSignal, metal-oxide-semiconductor M3 drain electrode be connected to the source electrode of B points and metal-oxide-semiconductor M7,
Metal-oxide-semiconductor M5 drain electrode, metal-oxide-semiconductor M5 source grounds；Metal-oxide-semiconductor M11 source electrode meets power supply ADD, and metal-oxide-semiconductor M11 grid connects ARM signals
Exported after phase inverterSignal；Metal-oxide-semiconductor M4 source grounds, metal-oxide-semiconductor M4 grid connect D points and metal-oxide-semiconductor M7, M9 leakage
Extremely it is total to contact；Metal-oxide-semiconductor M9 source electrode meets power vd D, metal-oxide-semiconductor M9 grid tie point C and metal-oxide-semiconductor M10 grid and drain electrode,
Metal-oxide-semiconductor M8 drain electrode, metal-oxide-semiconductor M10 source electrode meet power vd D.Metal-oxide-semiconductor M7 grid and metal-oxide-semiconductor M8 grid, metal-oxide-semiconductor M5
The grid of grid and metal-oxide-semiconductor M6 is connected to VC points altogether, and metal-oxide-semiconductor M8 source electrode is connected to metal-oxide-semiconductor M6 drain electrode, metal-oxide-semiconductor M6 source
Pole is grounded.
Wherein, VC points are the bias voltages of metal-oxide-semiconductor M5, M6, M7 and M8 grid.
Quenching circuit major design main points are：
(1) metal-oxide-semiconductor M2 is charging valve, and M1 is quenching tube.
(2) metal-oxide-semiconductor M9 and M10 breadth length ratio is equal.Metal-oxide-semiconductor M7 breadth length ratios are n times of M8, and M5 breadth length ratios are n times of M6
(n>1).The voltage for ensureing high-impedance node D under stable state is low.
(3) constant-current source I electric current very little, E points are avoided indefinite state occur.
With reference to Fig. 2, when external signal START rising edge arrives, timing starts.ARM is SPAD charging signals, its high electricity
Flat to continue only several nanoseconds, then ARM is low；ARM signals export by phase inverterARM is during height, circuit is given
SPAD charges, and is at inclined state.ARM from high to low after, SPAD charging terminates, in prepare the detection phase.Work as light
When (dark) carrier arrives and is converted to certain current signal by SPAD, the output STOP (E points) of quenching circuit is by high step-down.
The mark that timing circuit is started with START rising edge as timing, the mark stopped with STOP trailing edge as timing, then
Length between START rising edge and STOP trailing edge is the distance value of target.
The course of work is as follows：
(1) ARM=1, SPAD charging stages are worked as.
ARM=1, M2 grid voltage are height, and A point voltages are pulled to ground, and SPAD was in reverse-biased, and its reversed bias voltage is VB
(VB>0).Because E points current potential is height, quenching tube M1 grid voltage is height, thus M1 is turned off.
(2) work as ARM=0, prepare the detection phase.
ARM=0, M2 grid voltage are low, M2 shut-offs；M3 is turned on, and A points voltage is equal to B point voltages.Because D is low potential, M4
Shut-off, E current potentials avoid the appearance of indefinite state because constant-current source I pull-up is VDD.
(3) quenching stage.
Appropriate selection VDD and VB size, makes VB be more than SPAD avalanche breakdown voltage, while ensure that (VB-VDD) is less than
SPAD avalanche breakdown voltage；VC is M5, M6, M7 and M8 gate bias voltage.
When light (dark) carrier triggering SPAD produces avalanche current, the electric current charges to node A, and A point voltages pass through switch
M3 is transferred to B, and B points voltage is transferred to D points by amplification, and when D voltages are more than M4 threshold value, M1 is opened.A point voltages are increased to
VDD, SPAD reversed bias voltage are down to (VB-VDD) by VB.Then PAD avalanche conditions are quenched；Meanwhile STOP is by high step-down, mark
Timing terminates.When timing terminates, START=0, detection is completed.Until the next photon detection of system reset progress, then repeat above-mentioned
Process.
If M9 channel resistance is r9, M7 mutual conductance is gm7, M4 threshold voltage is VTH4, then A points be quenched voltage minimum
Threshold value is only：VTH4/(gm7*r9), this voltage is that (the g of voltage 1/ is quenched in traditionm7*r9) times；Meanwhile put by the voltage of B points to D points
Greatly with mutually amplification, speed.And traditional voltage amplification needs current mirror, 180 degree reversion occurs for phase, produces larger
Response time delay.
Embodiment 2
On the basis of embodiment 1, in the present embodiment, increase the n times of (n that metal-oxide-semiconductor M13 and M14, M13 breadth length ratio are M14>
1)；Increase metal-oxide-semiconductor M12, while remove metal-oxide-semiconductor M3.
Metal-oxide-semiconductor M13 grid voltage is E, and M14 grid voltage is power vd D；M12 grid voltage is
Increased metal-oxide-semiconductor M13 can further shorten light (dark) carrier quenching time.
Remaining is same as Example 1.
Physical circuit as shown in figure 3, including charging valve metal-oxide-semiconductor M2, quenching tube metal-oxide-semiconductor M1, metal-oxide-semiconductor M4, M5, M6, M7,
M8, M9, M10, M11, M12, M13 and M14；
Metal-oxide-semiconductor M2 and metal-oxide-semiconductor M1 drain electrode is connected to A points altogether；Metal-oxide-semiconductor M1 source electrode meets power vd D；Metal-oxide-semiconductor M2 source electrode
Ground connection；Metal-oxide-semiconductor M2 grid connects ARM signals；Metal-oxide-semiconductor M1 grid meets output STOP of the E points as quenching circuit, connects simultaneously
The drain electrode of drain electrode, metal-oxide-semiconductor M4 and constant-current source I output end to metal-oxide-semiconductor M11, constant-current source I input are connected to power supply ADD；
The drain electrode of metal-oxide-semiconductor M7 source electrode, metal-oxide-semiconductor M5 is connected to B points altogether, is connected through B points with A points；The leakage of metal-oxide-semiconductor M5 source electrodes and metal-oxide-semiconductor M13
Pole connects, and metal-oxide-semiconductor M13 source ground, metal-oxide-semiconductor M13 grid is connected to E points；Metal-oxide-semiconductor M11 source electrode meets power supply ADD, MOS
Pipe M11 grid connectsSignal；Metal-oxide-semiconductor M4 source electrodes are connected to metal-oxide-semiconductor M12 drain electrode, and metal-oxide-semiconductor M12 grid connects
Signal, metal-oxide-semiconductor M12 source ground, metal-oxide-semiconductor M4 grid connect D points and metal-oxide-semiconductor M7, M9 drain electrode contact altogether；Metal-oxide-semiconductor M9 source
Pole meets power vd D, metal-oxide-semiconductor M9 grid tie point C and metal-oxide-semiconductor M10 grid and drain electrode, metal-oxide-semiconductor M8 drain electrode, metal-oxide-semiconductor M10
Source electrode meet power vd D；The grid of metal-oxide-semiconductor M7 grid and metal-oxide-semiconductor M8 grid, metal-oxide-semiconductor M5 grid and metal-oxide-semiconductor M6 connects altogether
VC is connected to, metal-oxide-semiconductor M8 source electrode is connected to metal-oxide-semiconductor M6 drain electrode, and metal-oxide-semiconductor M6 source electrode is connected to metal-oxide-semiconductor M14 drain electrode, MOS
Pipe M14 grid connects power vd D, metal-oxide-semiconductor M14 source ground.
Described above is only preferred embodiment of the present utility model, it is noted that for the common skill of the art
For art personnel, on the premise of the utility model technical principle is not departed from, some improvement and deformation can also be made, these change
Enter and deform and also should be regarded as the scope of protection of the utility model.
Claims (10)
1. a kind of gate quenching circuit of ultralow threshold value, it is characterized in that, including charging valve metal-oxide-semiconductor M2, quenching tube metal-oxide-semiconductor M1, MOS
Pipe M3, M4, M5, M6, M7, M8, M9, M10 and M11；
Metal-oxide-semiconductor M2 and metal-oxide-semiconductor M1 drain electrode is connected to A points and metal-oxide-semiconductor M3 source electrode altogether；Metal-oxide-semiconductor M1 source electrode meets power vd D；MOS
Pipe M2 source ground；Metal-oxide-semiconductor M2 grid connects ARM signals；Metal-oxide-semiconductor M1 grid connects output of the E points as quenching circuit
STOP, while the output end of metal-oxide-semiconductor M11 drain electrode, metal-oxide-semiconductor M4 drain electrode and constant-current source I is connected to, constant-current source I input
It is connected to power supply ADD；Metal-oxide-semiconductor M3 grid connectsSignal, metal-oxide-semiconductor M3 drain electrode be connected to the source electrode of B points and metal-oxide-semiconductor M7,
Metal-oxide-semiconductor M5 drain electrode, metal-oxide-semiconductor M5 source grounds；Metal-oxide-semiconductor M11 source electrode meets power supply ADD, and metal-oxide-semiconductor M11 grid connectsLetter
Number；Metal-oxide-semiconductor M4 source grounds, metal-oxide-semiconductor M4 grid connect D points and metal-oxide-semiconductor M7, M9 drain electrode contact altogether；Metal-oxide-semiconductor M9 source electrode connects electricity
Source VDD, metal-oxide-semiconductor M9 grid tie point C and metal-oxide-semiconductor M10 grid and drain electrode, metal-oxide-semiconductor M8 drain electrode, metal-oxide-semiconductor M10 source electrode
Meet power vd D；The grid of metal-oxide-semiconductor M7 grid and metal-oxide-semiconductor M8 grid, metal-oxide-semiconductor M5 grid and metal-oxide-semiconductor M6 is connected to altogether
VC, metal-oxide-semiconductor M8 source electrode are connected to metal-oxide-semiconductor M6 drain electrode, metal-oxide-semiconductor M6 source ground.
2. a kind of gate quenching circuit of ultralow threshold value according to claim 1, it is characterized in that, A points by indium post with
SPAD connections.
3. a kind of gate quenching circuit of ultralow threshold value according to claim 1, it is characterized in that, ARM signals are by anti-phase
Exported after deviceSignal.
4. a kind of gate quenching circuit of ultralow threshold value according to claim 1, it is characterized in that, metal-oxide-semiconductor M9 and M10 width
Length is than equal.
5. a kind of gate quenching circuit of ultralow threshold value according to claim 1, it is characterized in that, metal-oxide-semiconductor M7 breadth length ratios are
N times of metal-oxide-semiconductor M8, n>1.
6. a kind of gate quenching circuit of ultralow threshold value according to claim 1, it is characterized in that, metal-oxide-semiconductor M5 breadth length ratios are
N times of metal-oxide-semiconductor M6, n>1.
7. a kind of gate quenching circuit of ultralow threshold value, it is characterized in that, including charging valve metal-oxide-semiconductor M2, quenching tube metal-oxide-semiconductor M1, MOS
Pipe M4, M5, M6, M7, M8, M9, M10, M11, M12, M13 and M14；
Metal-oxide-semiconductor M2 and metal-oxide-semiconductor M1 drain electrode is connected to A points altogether；Metal-oxide-semiconductor M1 source electrode meets power vd D；Metal-oxide-semiconductor M2 source ground；
Metal-oxide-semiconductor M2 grid connects ARM signals；Metal-oxide-semiconductor M1 grid meets output STOP of the E points as quenching circuit, while is connected to MOS
The output end of pipe M11 drain electrode, metal-oxide-semiconductor M4 drain electrode and constant-current source I, constant-current source I input are connected to power supply ADD； MOS
The drain electrode of pipe M7 source electrode, metal-oxide-semiconductor M5 is connected to B points altogether, is connected through B points with A points；The drain electrode of metal-oxide-semiconductor M5 source electrodes and metal-oxide-semiconductor M13
Connection, metal-oxide-semiconductor M13 source ground, metal-oxide-semiconductor M13 grid are connected to E points；Metal-oxide-semiconductor M11 source electrode connects power supply ADD, metal-oxide-semiconductor
M11 grid connectsSignal；Metal-oxide-semiconductor M4 source electrodes are connected to metal-oxide-semiconductor M12 drain electrode, and metal-oxide-semiconductor M12 grid connectsLetter
Number, metal-oxide-semiconductor M12 source ground, metal-oxide-semiconductor M4 grid connects D points and metal-oxide-semiconductor M7, M9 drain electrode contact altogether；Metal-oxide-semiconductor M9 source electrode
Power vd D, metal-oxide-semiconductor M9 grid tie point C and metal-oxide-semiconductor M10 grid and drain electrode, metal-oxide-semiconductor M8 drain electrode are connect, metal-oxide-semiconductor M10's
Source electrode meets power vd D；Metal-oxide-semiconductor M7 grid is connected altogether with metal-oxide-semiconductor M8 grid, metal-oxide-semiconductor M5 grid with metal-oxide-semiconductor M6 grid
To VC, metal-oxide-semiconductor M8 source electrode is connected to metal-oxide-semiconductor M6 drain electrode, and metal-oxide-semiconductor M6 source electrode is connected to metal-oxide-semiconductor M14 drain electrode, metal-oxide-semiconductor
M14 grid connects power vd D, metal-oxide-semiconductor M14 source ground.
8. a kind of gate quenching circuit of ultralow threshold value according to claim 7, it is characterized in that, metal-oxide-semiconductor M13 breadth length ratios are
N times of metal-oxide-semiconductor M14, n>1.
9. a kind of gate quenching circuit of ultralow threshold value according to claim 7, it is characterized in that, A points by indium post with
SPAD connections.
10. a kind of gate quenching circuit of ultralow threshold value according to claim 7, it is characterized in that, ARM signals are by anti-phase
Exported after deviceSignal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107124173A (en) * | 2017-06-26 | 2017-09-01 | 北方电子研究院安徽有限公司 | A kind of gate quenching circuit of ultralow threshold value |
| CN110763335A (en) * | 2018-07-25 | 2020-02-07 | 苏州超锐微电子有限公司 | Novel SPAD quenching circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107124173A (en) * | 2017-06-26 | 2017-09-01 | 北方电子研究院安徽有限公司 | A kind of gate quenching circuit of ultralow threshold value |
| CN107124173B (en) * | 2017-06-26 | 2023-10-27 | 安徽北方微电子研究院集团有限公司 | Ultra-low threshold gating quenching circuit |
| CN110763335A (en) * | 2018-07-25 | 2020-02-07 | 苏州超锐微电子有限公司 | Novel SPAD quenching circuit |
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