CN206945946U - A kind of digital quantity inputs combining unit test system - Google Patents

Abstract

This application discloses a digital input merging unit test system, including a host computer, a communicator, a central processing unit, a multi-channel collector, an optical receiver, a synchronous signal device and a digital signal source; a multi-channel collector, an optical receiver, Both the synchronous annunciator and the digital signal source are respectively connected to the central processing unit; the upper computer is connected to the central processing unit through a communicator; the optical receiver is connected to the digital signal source; the central processing unit includes a drive unit, a receiving unit and a computing unit; the application In the embodiment, the digital signal output by the multi-channel collector is sent discretely and asynchronously, and multiple signals are simultaneously tested on the digital input merging unit, thereby improving the test efficiency. In addition, the optical receiver realizes the closed-loop test of the digital input merging unit to be tested and the high-precision retrieval of the data sent by the test system.

Description

A Digital Quantity Input Merging Unit Test System

technical field

The present application relates to the technical field of smart grid testing, in particular to a digital input merging unit testing system.

Background technique

The merging unit appears as an independently operating automation device, responsible for completing the real-time data acquisition of analog quantities output by multiple transformers within a time interval, data synchronization, data processing and sending, and other necessary functions such as switch quantity acquisition and self-inspection . The merging unit is responsible for electric energy metering and information digital transmission. The on-site test of the merging unit is particularly important in ensuring the accuracy of electric energy measurement of the smart substation metering system and the reliability, accuracy and safety of networked information transmission.

The merging unit test system is a system that detects the function and performance of the operating equipment of the merging unit. It is a detection system that checks the protection, metering, monitoring, and fault recording of the data of the merging unit. Its main functions include testing Indexes such as ratio difference, angle difference, composite error, absolute delay time, signal-to-noise ratio, transient maximum peak error, and decay time constant of all data channels of the merging unit, as well as message jitter time of the merging unit, synchronization punctuality accuracy, etc. Function.

When the existing test system is actually running on site, it can only test a single signal for the digital input merging unit, which takes a long time and ultimately leads to low test efficiency.

Utility model content

The purpose of this application is to provide a digital input merging unit testing system to solve the problem of low efficiency of merging unit testing in the prior art.

According to an embodiment of the present application, a digital input merging unit test system is provided, including: a host computer, a communicator, a central processing unit, a multi-channel collector, an optical receiver, a synchronous signal device, and a digital signal source;

The multi-channel collector, the optical receiver, the synchronization annunciator and the digital signal source are respectively connected to the central processing unit;

The host computer is connected with the central processing unit through the communicator;

The optical receiver is connected to the digital signal source;

The central processing unit includes a drive unit, a receiving unit and a computing unit;

One end of the drive unit is connected to the communicator, and the other end of the drive unit is connected to the digital signal source; the multi-channel collector, the optical receiver and the digital signal source are respectively connected to the The receiving unit is connected; one end of the computing unit is connected to the communicator, and the other end of the computing unit is connected to the receiving unit.

Optionally, in the digital input merging unit test system, the communicator includes any two of optical fiber communicator, serial communicator and Ethernet communicator.

Optionally, in the digital input merging unit test system, the communicator includes a fiber optic communicator, a serial communicator, and an Ethernet communicator.

Optionally, in the digital input merging unit test system, the system further includes a digital-to-analog converter, and the digital-to-analog converter is connected to the central processing unit.

Optionally, in the digital input merging unit test system, the system further includes a pulse transceiver connected to the central processing unit.

It can be seen from the above technical solutions that the embodiment of the present application provides a digital input merging unit test system, including: a host computer, a communicator, a central processing unit, a multi-channel collector, an optical receiver, a synchronous signal device and a digital signal source; The multi-channel collector, the optical receiver, the synchronous signal device and the digital signal source are respectively connected to the central processing unit; the host computer is connected to the central processing unit through the communicator; The optical receiver is connected to the digital signal source; the central processing unit includes a drive unit, a receiving unit and a computing unit; one end of the drive unit is connected to the communicator, and the other end of the drive unit is connected to the The digital signal source is connected; the multi-channel collector, the optical receiver and the digital signal source are respectively connected to the receiving unit; one end of the computing unit is connected to the communicator, and the computing unit The other end is connected to the receiving unit; the embodiment of the present application is based on a random sequence algorithm generated by a random function to realize the discrete asynchronous transmission of the digital signal output by the multi-channel collector, and to realize the digital input combining unit for multiple signals. Test, solve the problem of low signal stability and reliability in testing digital input merging units at present, and improve test efficiency. In addition, after receiving the signal from the digital signal source, the optical receiver completes data frame reception and time scale calibration, and then sends the data frame to the central processing unit, which completes the analysis and processing of the data frame to realize the input of the measured digital quantity. The closed-loop test of the merging unit and the high-precision retrieval of the data sent by the test system.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present application. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is a schematic structural diagram of a digital input merging unit test system shown according to an embodiment;

Fig. 2 is a schematic structural diagram of another digital input merging unit test system shown according to an embodiment;

Fig. 3 is a schematic structural diagram of a central processing unit shown according to an embodiment;

4 is a circuit diagram illustrating a serial communicator according to an embodiment;

Fig. 5 is a schematic structural diagram of another digital input merging unit test system shown according to an embodiment;

Fig. 6 is the circuit diagram of the pulse transceiver shown according to the embodiment;

Fig. 7 is a circuit diagram of a central processing unit clock unit shown according to an embodiment;

Fig. 8 is a circuit diagram of a CPU power module according to an embodiment.

Graphical description:

Among them, 1-host computer, 2-communicator, 21-optical fiber communicator, 22-serial communicator, 23-Ethernet communicator, 3-digital-to-analog converter, 4-pulse transceiver, 5-central processing unit , 501-driving unit, 502-receiving unit, 503-computing unit, 511-multimedia personal computer, 512-Ethernet controller, 513-microcontroller, 514-peripheral device interconnection bus, 515-field programmable gate array , 516-storage chip, 517-Synchronous DRAM, 6-multiplexer, 7-optical receiver, 8-synchronous signal generator, 9-digital signal source, 10-merging unit.

detailed description

Referring to Figures 1 to 2, the embodiment of the present application provides a digital input merging unit test system, including: a host computer 1, a communicator 2, a central processing unit 5, a multi-channel collector 6, an optical receiver 7, and a synchronization signal Device 8 and digital signal source 9;

The multi-channel collector 6, the optical receiver 7, the synchronous signal device 8 and the digital signal source 9 are respectively connected with the central processing unit 5;

The upper computer 1 is connected with the central processing unit 5 through the communicator 2;

The optical receiver 7 is connected to the digital signal source 9;

The central processing unit 5 includes a drive unit 501, a receiving unit 502 and a computing unit 503;

One end of the drive unit 501 is connected to the communicator 2, and the other end of the drive unit 501 is connected to the digital signal source 9; the multi-channel collector 6, the optical receiver 7 and the digital The signal source 9 is respectively connected to the receiving unit 502; one end of the computing unit 503 is connected to the communicator 2, and the other end of the computing unit 503 is connected to the receiving unit 502;

The multi-channel collector 6 is used to send the digital quantity data of the multi-channel collector simulated by the system;

The digital signal source 9 is used to provide a digital signal for the test system;

The optical receiver 7 is used to transmit the signal sent by the receiving digital signal source 9 to the central processing unit 5 for analysis, and to judge the integrity of the signal sent by the test system;

Before use, one end of the synchronous annunciator 8 is connected to the clock unit of the central processing unit 5, and the other end of the synchronous annunciator 8 is connected to an external clock, so that the test system and the merging unit 10 to be tested are communicated, so that the communication between the two Information received or sent can be consistent in time.

It should be noted that the synchronous annunciator 8 receives the second pulse TRIG signal sent externally or from the clock unit, receives and detects the quality of the synchronous signal (effective pulse width, jitter and frequency, etc.), and after receiving multiple valid synchronous signals continuously , lock its own clock frequency and enter the main clock following mode, and use the main system clock period to generate the running interruption clock of the test terminal. When the synchronization signal is lost, it can realize synchronization and punctuality within a period of time by its own high-precision constant temperature crystal oscillator and software algorithm , to ensure the time consistency of all test terminals.

During the test, the host computer 1 sends a test command, and the test signal is transmitted to the drive unit 501 of the central processing unit 5 through the communicator 2, and the drive unit 501 drives the digital signal source 9 to generate a digital signal, and sends the same digital signal to the receiver. Unit 502 and light receiver 7. After receiving the digital signal, the optical receiver 7 completes data frame reception and time scale calibration, and then sends the data frame to the receiving unit 502, and the receiving unit 502 compares the digital signal sent by the digital signal source 9 with the data frame sent by the optical receiver , to ensure that the signal sent to the merging unit 10 under test is complete information; the receiving unit 502 sends the digital signal to the multi-channel collector 6, and passes it to the merging unit 10 through the multi-channel collector 6, and the merging unit under test 10 After receiving the digital signal, it is fed back to the receiving unit 502 by the multi-channel collector 6, and the receiving unit 502 sends the sent and fed back digital signal to the calculation unit 503, and the calculation unit 503 calculates the sent and fed back digital signal and display the test result on the host computer 1 through the communicator 2.

It can be seen from the above technical solutions that the embodiment of the present application provides a digital input merging unit test system, including: a host computer 1, a communicator 2, a central processing unit 5, a multi-channel collector 6, an optical receiver 7, and a synchronous signal device 8 and a digital signal source 9; the multi-channel collector 6, the optical receiver 7, the synchronous signal device 8 and the digital signal source 9 are respectively connected with the central processing unit 5; the upper computer 1 The communicator 2 is connected to the central processing unit 5; the optical receiver 7 is connected to the digital signal source 9; the central processing unit 5 includes a drive unit 501, a receiving unit 502 and a computing unit 503; One end of the drive unit 501 is connected to the communicator 2, and the other end of the drive unit 501 is connected to the digital signal source 9; the multi-channel collector 6, the optical receiver 7 and the digital signal The source 9 is respectively connected to the receiving unit 502; one end of the computing unit 503 is connected to the communicator 2, and the other end of the computing unit 503 is connected to the receiving unit 502; the embodiment of the present application is based on random function generation The random sequence algorithm realizes the discrete and asynchronous transmission of the digital signal output by the multi-channel collector 6, realizes the test of multiple signals on the digital input merging unit 10, and solves the problem of signal stability in testing the digital input merging unit 10 at present. Performance and reliability, improve test efficiency. In addition, after receiving the signal from the digital signal source 9, the optical receiver 7 completes the data frame reception and time scale calibration, and then sends the data frame to the central processing unit 5, and the central processing unit 5 completes the analysis and processing of the data frame to realize the Measure the closed-loop test of the digital input merging unit 10 and the high-precision retrieval of the data sent by the test system.

Optionally, in the digital input merging unit test system, the communicator 2 includes any two of an optical fiber communicator 21 , a serial communicator 22 and an Ethernet communicator 23 . Utilize the high-efficiency mechanism of the optical fiber serial port communication module to formulate a fully compatible communication code, which can sample the protocols of different domestic manufacturers at the same port, and no longer need to formulate corresponding interfaces for different manufacturers.

Among them, the optical fiber communicator 21 adopts the AFBR 5803ATZ type interface of AVAGO Company, and adopts multi-mode 850nm optical fiber to realize the receiving and sending of optical fiber signals.

Among them, the serial communicator 22 is used to complete the communication between the test system and the merging unit. The display of the data output value of the system is completed on the host computer 1, and the data configuration is also completed by the software of the host computer 1. The private communication protocol of each electronic transformer manufacturer is used when the data of the collector in the simulated electronic transformer is sent. The system supports domestic Communication protocol of mainstream manufacturers; optical fiber serial receiver is mainly used to receive FT3 data. The serial communication interface adopts the optical fiber joint of AVAGO Company. Its loop design is shown in Figure 4.

Wherein, the Ethernet communicator 23 directly uses the Ethernet communication port of the MPC8247 in hardware, and the interface adopts an RJ45 interface and a dedicated communication cable. The optical fiber Ethernet communication module is used to complete the Ethernet communication between the test system and the detected merging unit and electric energy meter. It is mainly used to realize the data transmission between the merging unit 10 and the electric energy meter during virtual load detection and the reception of data from the merging unit 10 received by the detected electric energy meter during real load detection. According to the relevant technical requirements of the smart substation, the communication module needs to adopt multi-mode optical fiber devices, and the interface mode adopts ST interface. AFBR5803ATZ of AVAGO Company is proposed to be used for realization. The Ethernet communication port directly uses the Ethernet port of the main CPU, and is connected to the AFBR5803ATZ through the signal processing circuit to complete the receiving and sending function of optical fiber Ethernet data.

Optionally, in the digital input merging unit test system, referring to FIG. 5 , the communicator 2 includes a fiber optic communicator 21 , a serial communicator 22 and an Ethernet communicator 23 . Utilize the high-efficiency mechanism of the optical fiber serial port communication module to formulate a fully compatible communication code. The test system can be connected to the digital input merging unit 10 manufactured by domestic mainstream manufacturers with only one interface, and it is no longer necessary to separately formulate the corresponding interface to match it. , to reduce the size of the test system.

Optionally, in the digital input merging unit test system, the system further includes a digital-to-analog converter 3 connected to the central processing unit 5 . The test system of the present application can test all the functions of the digital input merging unit 10, and can also test the functions of the electric energy meter. Among them, the function of the digital-to-analog converter 3 is to convert digital signals such as time synchronization and message monitoring into analog signals and transmit them to the electric energy meter. Because the electric energy meter used in the smart substation is an analog signal input, it is necessary to convert the signal form , this function is realized through a professional digital-to-analog converter 3 output data conversion chip.

Optionally, in the digital input merging unit test system, the system further includes a pulse transceiver 4 connected to the central processing unit 5 . The test system of the present application can test all the functions of the digital input merging unit 10, and can also test the functions of the electric energy meter. The function of the pulse transceiver module is to send the power data signal to the electric energy meter, because the electric energy meter in the smart substation performs superimposed counting in the form of pulses when counting the electric power.

The pulse transceiver 4 is used to complete the test system's reception of the low-frequency power pulse of the detected electric energy meter and the detection pulse generation of the power calculation of the system itself. According to the characteristics of the calibration pulse of the electric energy meter, the pulse input interface of the system is an active interface, and the power supply is +5V. When the detected electric energy meter sends out a pulse, it can receive the electric quantity pulse in real time. The external pulse and the internal working power supply of the system use an optocoupler Quarantine. The transmission of the system's own electricity metering pulse is similar to the low-frequency calibration pulse of the electric energy meter. The MPC8247 directly transmits the pulse through the control port line, and at the same time uses an optocoupler to electrically isolate the system from the outside to avoid interference when the output pulse signal is connected to other devices. . Refer to Figure 6 for the circuit design of the pulse transceiver 4.

Optionally, in the digital input merging unit test system, the host computer 1 includes a liquid crystal display and a keyboard, and the liquid crystal display and the keyboard are arranged on the front of the host computer 1 . The LCD screen can intuitively display the test status and test results of the test system, and the keyboard can facilitate the staff to control the test system.

Optionally, the upper computer 1 adopts a notebook mode, and its function is to control the operation of the test system and display data.

Optionally, central processing unit (Central Processing Unit, CPU) 5 adopts MPC8247511 (Multimedia Personal Computer, multimedia personal computer) embedded microprocessor of Freescale Company, referring to Fig. 3, this processor belongs to PowerQUICC II series, comprises a based on PowerPC The core of MPC603e, and a communication processing core CPM. The CPU working clock is 66MHz; at the same time, two MT48LC4M16A2 chips are used to expand 16Mx32bit SDRAM 517 (Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory); one AM29LV081B externally expanded 8Mbit memory chip 516 is used to solidify the program; in addition, SPI Bus, WATCHDOG circuit and a large number of receiving control ports constitute a small embedded computer system to complete data processing and analysis as well as corresponding communication and control functions. FPGA (Field-Programmable Gate Array, that is, Field Programmable Gate Array) 515 uses Xilinx's Spartan3 series product XC3S1500, which contains 1.5 million system gates, 32 dedicated multipliers, and 4 digital clock management modules. It has rich logic resources and can run high speed. FPGA515 utilizes precise timing control capability to complete Ethernet MAC sublayer design, interface design between MAC sublayer and Ethernet controller 512, Ethernet data transmission and FT3 data transmission. The specific design is as follows:

(1) The Ethernet controller 512 is LXT971 of Intel Corporation. LXT971 is a single-port 10/100M dual-speed fast Ethernet controller, which is compatible with IEEE802.3; supports 10Base5, 10Base2, 10BaseT, 100BASE-X, 100BASE-TX and 100BASE-FX, and can automatically detect the connected medium, choose Agi lent AFBR5803 as a fiber optic network transceiver.

(2) The crystal oscillator is planned to use OCXO50 constant temperature crystal oscillator, with an operating temperature of -40 to 85°C, a temperature drift characteristic of less than 1ppb, a low phase noise of -160dBc/1KHz, and a maximum of 10ppb/year low aging. The high-precision crystal oscillator is PowerPC And FPGA 515 provides the clock beat, which ensures the accuracy and long-term stability of timing control.

(3) The MPU system also has its own Ethernet communication interface, serial communication interface, external interrupt interface and a large number of input and output lines, which can be easily controlled by software, with good reliability and excellent real-time performance and The scalable embedded real-time operating system (RTOS) can conveniently realize the overall test simulation function of digital metering (measurement). :

(4) CPU clock unit design

The CPU clock of this system is planned to adopt the real-time clock chip DS1306 of DALLAS Company, and the DS1306 plans to use an external backup power supply, an external crystal oscillator output and an alarm clock interrupt application function, and the minimum connection line with the main control device is 11 mode or serial peripheral interface (SPI ) mode, the clock loop design principle is shown in Figure 7:

(5) CPU power module design

The power supply module is a special power supply for the test system. It is planned to use AC/DC converters produced by high-reliability components, combining the advantages of small size, light weight, and high efficiency of switching power supplies and low ripple of linear power supplies. The front stage uses light series modules to replace traditional transformers, and the rear stage uses linear power supply circuits to reduce ripple voltage. It has the characteristics of small ripple voltage, light and compact appearance, high efficiency, high power density and good electromagnetic compatibility. The casing of the power supply is made of high-density aluminum alloy radiator, and the surface of the casing is evenly and densely distributed with cooling fins, which effectively increases the cooling area. It is close to the minimum value, so that its electrical performance can be effectively combined with the physical structure.

Since the CPU power supply of the system hardware circuit is 3.3V, a power conversion circuit is designed on the main board. It is proposed to use MAXIM's 16441 chip design. The specific design is shown in Figure 8:

Optionally, the system power supply is designed with a switching power supply module. The performance requirements of the power module are as follows: input voltage: 220V, AC and DC, input voltage range: -120%～+120% UN; output voltage: 5V, deviation range: 4.85 ~ 5.15V; output current: 2A.

It can be seen from the above technical solutions that the embodiment of the present application provides a digital input merging unit test system, including: a host computer 1, a communicator 2, a central processing unit 5, a multi-channel collector 6, an optical receiver 7, and a synchronous signal device 8 and a digital signal source 9; the multi-channel collector 6, the optical receiver 7, the synchronous signal device 8 and the digital signal source 9 are respectively connected with the central processing unit 5; the upper computer 1 The communicator 2 is connected to the central processing unit 5; the optical receiver 7 is connected to the digital signal source 9; the central processing unit 5 includes a drive unit 501, a receiving unit 502 and a computing unit 503; One end of the drive unit 501 is connected to the communicator 2, and the other end of the drive unit 501 is connected to the digital signal source 9; the multi-channel collector 6, the optical receiver 7 and the digital signal The source 9 is respectively connected to the receiving unit 502; one end of the computing unit 503 is connected to the communicator 2, and the other end of the computing unit 503 is connected to the receiving unit 502; the embodiment of the present application is based on random function generation The random sequence algorithm realizes the discrete and asynchronous transmission of the digital signal output by the multi-channel collector 6, realizes the test of multiple signals on the digital input merging unit 10, and solves the signal stability of the digital input merging unit 10 currently being tested and reliability, improve test efficiency. In addition, after receiving the signal from the digital signal source 9, the optical receiver 7 completes the data frame reception and time scale calibration, and then sends the data frame to the central processing unit 5, and the central processing unit 5 completes the analysis and processing of the data frame to realize the Measure the closed-loop test of the digital input merging unit 10 and the high-precision retrieval of the data sent by the test system.

Other embodiments of the application will be readily apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any modification, use or adaptation of the application, these modifications, uses or adaptations follow the general principles of the application and include common knowledge or conventional technical means in the technical field not disclosed in the application . The specification and examples are to be considered exemplary only, with a true scope and spirit of the application indicated by the following claims.

It should be understood that the present application is not limited to the precise constructions which have been described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (5)

1. a kind of digital quantity input merging unit test system is characterized in that, comprises: upper computer (1), communicator (2), central processing unit (5), multi-channel collector (6), optical receiver (7 ), synchronous annunciator (8) and digital signal source (9); The multi-channel collector (6), the optical receiver (7), the synchronous signal device (8) and the digital signal source (9) are respectively connected to the central processing unit (5); The host computer (1) is connected with the central processing unit (5) through the communicator (2); The optical receiver (7) is connected to the digital signal source (9); The central processing unit (5) includes a drive unit (501), a receiving unit (502) and a computing unit (503); One end of the drive unit (501) is connected to the communicator (2), and the other end of the drive unit (501) is connected to the digital signal source (9); the multiplexer (6), The optical receiver (7) and the digital signal source (9) are respectively connected to the receiving unit (502); one end of the computing unit (503) is connected to the communicator (2), and the computing The other end of the unit (503) is connected to the receiving unit (502). 2. digital input merging unit test system according to claim 1, is characterized in that, described communicator (2) comprises optical fiber communicator (21), serial communicator (22) and Ethernet communicator (23 ) in any two. 3. digital input merging unit test system according to claim 1, is characterized in that, described communicator (2) comprises optical fiber communicator (21), serial communicator (22) and Ethernet communicator (23 ). 4. digital input merging unit test system according to claim 1, is characterized in that, described system also comprises digital-to-analog converter (3), and described digital-to-analog converter (3) and described central processing unit ( 5) Connect. 5. digital input merging unit test system according to claim 1, is characterized in that, described system also comprises pulse transceiver (4), and described pulse transceiver (4) and described central processing unit (5) connect.