CN206863403U - Prevent panel periphery cabling from the structure of damage by static electricity occurs - Google Patents
Prevent panel periphery cabling from the structure of damage by static electricity occurs Download PDFInfo
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- CN206863403U CN206863403U CN201721474661.3U CN201721474661U CN206863403U CN 206863403 U CN206863403 U CN 206863403U CN 201721474661 U CN201721474661 U CN 201721474661U CN 206863403 U CN206863403 U CN 206863403U
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- metal
- metal routing
- damage
- static electricity
- routing
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Abstract
It the utility model is related to a kind of structure for preventing panel periphery cabling from damage by static electricity occurs.This prevents panel periphery cabling from the structure of damage by static electricity occurs and includes：The first metal routing made of the first metal layer as peripheral wiring, and the metal routing of multistage second made of second metal layer；The metal routing of multistage second and the first metal routing arrange with respect to and along the direction of routing order of the first metal routing up and down, are provided between second metal routing and the first metal routing and are connected between dielectric layer and adjacent two section of second metal routing by dielectric layer；The multiple electric capacity formed for the second metal routing and the first relative metal routing as relative electrode, wherein at least including unequal two electric capacity of capacitance.The structure of the present utility model for preventing that panel periphery cabling from occurring damage by static electricity does ESD protection circuit on anterior peripheral cabling by increasing layer of metal line, reaches anti-static effect；Shorten the detection of process time, reduce production cost.
Description
Technical field
Field of liquid crystal is the utility model is related to, more particularly to one kind prevents panel periphery cabling from damage by static electricity occurs
Structure.
Background technology
The flat display apparatus such as liquid crystal display (Liquid Crystal Display, LCD) are because with high image quality, saving
Electricity, fuselage are thin and the advantages that have a wide range of application, and be widely used in mobile phone, TV, personal digital assistant, digital camera,
The various consumption electronic products such as notebook computer, desktop computer, turn into the main flow in display device.
In active liquid crystal display, each sub-pixel has a thin film transistor (TFT) (TFT), the connection of its grid (Gate)
To horizontal scanning line, source electrode (Source) is connected to the data wire of vertical direction, and drain electrode (Drain) is then connected to pixel electrode.
Apply enough voltage on horizontal scanning line, all TFT on this horizontal scanning line can be caused to open, now this level
Pixel electrode in scan line can connect with the data wire in vertical direction, so as to which the display signal voltage on data wire be write
Pixel, control the light transmittance of different liquid crystal and then control the effect of color.
In LCD production processes, generally because yield factor considers, it may be desirable to which some specific link in processing procedure is to the production
Product are detected, and find the problem of existing, to be repaired it to lift product yield；If desired product is examined
Survey, then need GOA circuits and effective display area (AA) of counter plate etc. to be powered, it is necessary to set letter around panel periphery cabling
Number weld pad (pad) is powered so as to probe；However, when panel peripheral wiring generation Electro-static Driven Comb (ESD), using automatic optics inspection
Board (AOI), which carries out panel scan, to be scanned to peripheral wiring, it is necessary to taken pictures using fixed point or hand inspection, due to
ESD occurs position and many randomnesss under normal circumstances be present, therefore is difficult effectively to find ESD in a short time point position or leakage occurs
Inspection causes capacity loss (loss).
As shown in figure 1, it is available liquid crystal display panel peripheral wiring design diagram.Wherein, one group of HVA weld pad (pad) 1
Peripheral wiring 3 proximally enters inside panel 5, and another group of HVA weld pad 2 is then from lower left side around long peripheral wiring 4 to the right side
Enter behind upper angle inside panel 5, so as to provide detection signal needed for panel 5.The peripheral wiring 3 and 4 generally only does first at present
Layer metal (M1) single-layer metal cabling, and without ESD protection circuit design, therefore peripheral wiring 3 and 4 relatively holds during processing procedure
Easily accumulation electrostatic, ESD then occurs at weld pad cross-line and wounds.
Utility model content
Therefore, the purpose of this utility model is to provide a kind of structure for preventing panel periphery cabling from damage by static electricity occurs,
ESD protection circuit is provided, ESD occurs for prevention panel periphery cabling.
To achieve the above object, the utility model provides a kind of knot for preventing panel periphery cabling from damage by static electricity occurs
Structure, including：The first metal routing made of the first metal layer as peripheral wiring, and made of second metal layer it is more
The second metal routing of section；The metal routing of multistage second and the first metal routing are up and down with respect to and along the first metal routing
Direction of routing order is arranged, and dielectric layer and adjacent two section second is provided between second metal routing and the first metal routing
Connected between metal routing by dielectric layer；Multiple electricity are formed between the metal routing of multistage second and the first metal routing
Hold, wherein, unequal two electric capacity of capacitance is comprised at least in the multiple electric capacity.
Wherein, the first metal layer is gate metal layer.
Wherein, the second metal layer is source-drain electrode metal level.
Wherein, the width of the metal routing of multistage second is identical, at least two section of the metal routing of multistage second
The length of two metal routings is different.
Wherein, length sequence's increase of each section of the second metal routing.
Wherein, including three section of second metal routing.
Wherein, the dielectric layer is made up of non-crystalline silicon.
Wherein, covered with insulating barrier on first metal routing.
Wherein, the peripheral wiring is active LCD peripheral wiring.
To sum up, the structure of the present utility model for preventing panel periphery cabling from damage by static electricity occurs is led on anterior peripheral cabling
Increase layer of metal line is crossed to do ESD protection circuit, reaches anti-static effect；Shorten the detection of process time, reduce production cost,
Improve yield.
Brief description of the drawings
Below in conjunction with the accompanying drawings, by the way that specific embodiment of the present utility model is described in detail, will make of the present utility model
Technical scheme and other beneficial effects are apparent.
In accompanying drawing,
Fig. 1 is available liquid crystal display panel peripheral wiring design diagram；
Fig. 2 is that the utility model prevents panel periphery cabling from the principle of the preferred embodiment of structure one of damage by static electricity occurs and shows
It is intended to；
Fig. 3 is schematic diagram of the preferred embodiment after the completion of array process shown in Fig. 2.
Embodiment
Referring to Fig. 2, it is that the utility model prevents panel periphery cabling from the preferred embodiment of structure one of damage by static electricity occurs
Principle schematic, for convenience of show structure, Fig. 2 show passivation (PV) processing procedure progress before structure, that is to say, that eliminate
Passivation layer and structure afterwards.The structure of the present utility model for preventing panel periphery cabling from damage by static electricity occurs, mainly includes：By
The first metal routing 10 made of the first metal layer as peripheral wiring, and the gold medal of multistage second made of second metal layer
Belong to cabling 20, in general display panel, the first metal layer can be the gate metal layer that is formed by gate metal, the second gold medal
Category layer can be the source-drain electrode metal level that is formed by source-drain electrode metal, that is, the first metal routing 10 and the second metal routing 20
It can be made by existing processing procedure；Multistage second metal routing 20 and the first metal routing are relative about 10 and along the
The direction of routing order of one metal routing 10 is arranged, and dielectric is provided between the metal routing 10 of the second metal routing 20 and first
Connected between layer 30 and adjacent two section of second metal routing 20 by dielectric layer 30, so as to using the first metal routing 10, be situated between
Electric layer 30 and adjacent two section of second metal routing 20 form TFT structure, and dielectric layer 30 can be by dielectric material such as non-crystalline silicon system
Into, can be covered with insulating barrier on the first metal routing 10 according in general display panel structure；Multiple second metal routings 20
And first form multiple electric capacity between metal routing 10, wherein, capacitance unequal two is comprised at least in the multiple electric capacity
Individual electric capacity.Unequal two electric capacity of the capacitance can with it is adjacent can also be non-conterminous.In the preferred embodiment, the multistage
Second metal routing 20 includes three sections：Second metal routing 21, the second metal routing 22, the second metal routing 23, wherein, second
Shape between formation electric capacity C1, the second metal routing 22 and the first metal routing 10 between the metal routing 10 of metal routing 21 and first
Into in formation electric capacity C3, electric capacity C1, electric capacity C2 and electric capacity C3 between electric capacity C2, the 3rd metal routing 23 and the first metal routing 10
The capacitance of at least two electric capacity is unequal.
Typically in order to simplify design, it is constant to set the width of the first metal routing 10 and the second metal routing 20, this
When formed for the second metal routing 20 and the first relative metal routing 10 as relative electrode multiple electric capacity C1,
C2, C3, capacitance can be controlled by setting the length of each section of the second metal routing 20.As shown in Fig. 2 including three section second
Metal routing 20, length H1, H2, H3 of each section of the second metal routing 20 can be set as sequentially increasing.
The structure of the present utility model for preventing panel periphery cabling from damage by static electricity occurs is applied to all active LCD production
Product, peripheral wiring are active LCD GOA circuits and the peripheral wiring of effective display area.
The design that anti-panel periphery cabling generation ESD of the present utility model wounds circuit includes selfcapacity formula ESD.Such as figure
Shown in 2, wherein H1, H2, H3, H4 represent track lengths, and H1 ＜ H2 ＜ H3 ＜ H4, C1, C2, C3 are corresponded to represent the first metal respectively
The electric capacity formed between layer and second metal layer, due to track lengths difference, so C1<C2<C3.In second metal layer processing procedure also
It is that electric capacity ESD can act after the completion of source-drain electrode processing procedure.When the long cabling of the first metal layer have accumulated larger electrostatic potential
Less electrostatic potential V1, V2, V3 are accumulated after V4, in second metal layer, then the TFT between V1 and V2, which is opened, discharges, and the first gold medal
Big electrostatic potential V4 also forms big pressure difference between V1, V2, V3 on category layer, so as to be walked in the first metal layer i.e. panel periphery
Electrostatic leakage path is formed between line and second metal layer, so as to protect cross-line or other positions at normal HVA weld pads to deposit
Avoid that damage by static electricity occurs in the region of cross-line.
Referring to Fig. 3, it is schematic diagram of the preferred embodiment after the completion of array process shown in Fig. 2.When array (Array) section
After the completion of processing procedure, the upper and lower base plate of display panel can be typically bonded by conductive frame glue 40, be now placed in the second of edge
Metal routing 21 and the first relative metal routing 10 may be turned on by the gold goal 50 of conductive frame glue 40, but be had no effect on
Electrostatic-proof function is formed between first metal routing 10 and remaining second metal routing 20, action principle is same as shown in Figure 2, profit
Different electric capacity C1, C2 are formed with different length H1, H2 the second metal routing 20, and then produces antistatic protection function.
The utility model prevents panel periphery cabling from the structure of damage by static electricity occurs and only increases by one on original peripheral wiring
Layer metal level, and without new intensifying hood；An electrostatic discharging path is done using accumulation of static electricity difference between double layer of metal cabling.This practicality
In new, after second metal layer film forming, by the second metal layer metal block shaped on itself the first metal layer into an electric capacity, together
When combine TFT devices, then a pressure difference can be differently formed according to static electricity gathered amount to turn on TFT, forms a static power consumption road
Footpath, accomplish antistatic protection function.
To sum up, the structure of the present utility model for preventing panel periphery cabling from damage by static electricity occurs is led on anterior peripheral cabling
Increase layer of metal line is crossed to do ESD protection circuit, reaches anti-static effect；Shorten the detection of process time, reduce production cost,
Improve yield.
It is described above, for the person of ordinary skill of the art, can according to the technical solution of the utility model and
Technical concept makes other various corresponding changes and deformation, and after all these changes and deformation should all belong to the utility model
Attached scope of the claims.
Claims (9)
- A kind of 1. structure for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that including：It is made up of the first metal layer The first metal routing as peripheral wiring, and the metal routing of multistage second made of second metal layer；The multistage Second metal routing and the first metal routing arrange with respect to and along the direction of routing order of the first metal routing up and down, and described the It is provided between two metal routings and the first metal routing and passes through dielectric layer between dielectric layer and adjacent two section of second metal routing Connection；Multiple electric capacity are formed between the metal routing of multistage second and the first metal routing, wherein, in the multiple electric capacity extremely Include unequal two electric capacity of capacitance less.
- 2. the structure as claimed in claim 1 for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that described first Metal level is gate metal layer.
- 3. the structure as claimed in claim 1 for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that described second Metal level is source-drain electrode metal level.
- 4. the structure as claimed in claim 1 for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that the multistage The width of second metal routing is identical, and the length of at least two section second metal routing of the metal routing of multistage second is different.
- 5. the structure as claimed in claim 4 for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that each section second Length sequence's increase of metal routing.
- 6. the structure as claimed in claim 5 for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that including three sections Second metal routing.
- 7. the structure as claimed in claim 1 for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that the dielectric Layer is made up of non-crystalline silicon.
- 8. the structure as claimed in claim 1 for preventing panel periphery cabling from damage by static electricity occurs, it is characterised in that described first Covered with insulating barrier on metal routing.
- 9. the structure as claimed in claim 1 for preventing panel periphery cabling from damage by static electricity occurs, the peripheral wiring is actively Type LCD peripheral wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721474661.3U CN206863403U (en) | 2017-11-07 | 2017-11-07 | Prevent panel periphery cabling from the structure of damage by static electricity occurs |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721474661.3U CN206863403U (en) | 2017-11-07 | 2017-11-07 | Prevent panel periphery cabling from the structure of damage by static electricity occurs |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206863403U true CN206863403U (en) | 2018-01-09 |
Family
ID=60832477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721474661.3U Withdrawn - After Issue CN206863403U (en) | 2017-11-07 | 2017-11-07 | Prevent panel periphery cabling from the structure of damage by static electricity occurs |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206863403U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807467A (en) * | 2017-11-07 | 2018-03-16 | 深圳市华星光电半导体显示技术有限公司 | Prevent panel periphery cabling from the structure of damage by static electricity occurs |
| CN108490707A (en) * | 2018-03-23 | 2018-09-04 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| US10901280B2 (en) | 2018-03-23 | 2021-01-26 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate and display panel |
-
2017
- 2017-11-07 CN CN201721474661.3U patent/CN206863403U/en not_active Withdrawn - After Issue
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807467A (en) * | 2017-11-07 | 2018-03-16 | 深圳市华星光电半导体显示技术有限公司 | Prevent panel periphery cabling from the structure of damage by static electricity occurs |
| WO2019090894A1 (en) * | 2017-11-07 | 2019-05-16 | 深圳市华星光电半导体显示技术有限公司 | Structure for preventing electrostatic damage to peripheral wiring of panel |
| CN107807467B (en) * | 2017-11-07 | 2023-08-22 | 深圳市华星光电半导体显示技术有限公司 | Structure for preventing panel peripheral wiring from electrostatic injury |
| CN108490707A (en) * | 2018-03-23 | 2018-09-04 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| WO2019179151A1 (en) * | 2018-03-23 | 2019-09-26 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN108490707B (en) * | 2018-03-23 | 2020-09-04 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| US10901280B2 (en) | 2018-03-23 | 2021-01-26 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate and display panel |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20180109 Effective date of abandoning: 20230822 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20180109 Effective date of abandoning: 20230822 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |