CN206850886U - A kind of image signal processing apparatus - Google Patents

A kind of image signal processing apparatus Download PDF

Info

Publication number
CN206850886U
CN206850886U CN201720684376.8U CN201720684376U CN206850886U CN 206850886 U CN206850886 U CN 206850886U CN 201720684376 U CN201720684376 U CN 201720684376U CN 206850886 U CN206850886 U CN 206850886U
Authority
CN
China
Prior art keywords
resistance
image
electric capacity
triode
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201720684376.8U
Other languages
Chinese (zh)
Inventor
刁晨
王斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northwest Minzu University
Original Assignee
Northwest Minzu University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northwest Minzu University filed Critical Northwest Minzu University
Priority to CN201720684376.8U priority Critical patent/CN206850886U/en
Application granted granted Critical
Publication of CN206850886U publication Critical patent/CN206850886U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The utility model discloses a kind of image signal processing apparatus, including image acquisition units, image enhancing unit and image-display units;Described image enhancement unit includes image denoising unit and image enhancing unit, described image denoising unit includes input band-pass circuit, input buffer circuit, amplifying circuit and output buffer, the input band-pass circuit connection input buffer circuit, the input buffer circuit connects amplifying circuit, and the amplifying circuit connects output buffer;It is connected after image collection assembly connection image denoising unit with image synthesis chip, as being connected after frame filter device with greyscale transformation device, greyscale transformation device is connected image synthesis chip connection figure by D/A converter with image display unit.A kind of image signal processing apparatus provided by the utility model, strengthened again by carrying out first denoising to image, improve the enhancing effect of image.

Description

A kind of image signal processing apparatus
Technical field
The utility model belongs to technical field of image processing, and in particular to a kind of image signal processing apparatus.
Background technology
With the fast development of semiconductor technology, it leads digital integrated electronic circuit to large-scale, high integration, Gao Fu Miscellaneous degree, the direction of multifunction are developed;Smart machine therein is that human lives bring earth-shaking change, digital picture Processing be used as the important ring in smart machine, just playing indispensable effect, from take pictures make video recording, two-way video exchange, people Face identification waits until virtual reality role-play interaction, all be unable to do without Digital Image Processing;Wherein, imaging sensor is as in image procossing Picture signal sampler vital effect is played to the quality of image procossing.However, existing image processor system System is not satisfactory due to system structure design, and generally existing system architecture complexity, picture lag, picture quality deviation etc. are asked Topic.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of image signal processing apparatus.
To reach above-mentioned purpose, the utility model provides following technical scheme, a kind of image signal processing apparatus, including figure As collecting unit, image enhancing unit and image-display units;
Described image enhancement unit includes image denoising unit and image enhancing unit,
Described image denoising unit includes input band-pass circuit, input buffer circuit, amplifying circuit and output buffer, The input band-pass circuit connection input buffer circuit, the input buffer circuit connect amplifying circuit, and the amplifying circuit connects Connect output buffer;The first order RC circuits and second level RC circuits for inputting band-pass circuit and including being serially connected, and the Two level RC circuits are connected with input buffer circuit;
Described image enhancement unit includes image synthesis chip, image interframe wave filter and greyscale transformation device;
It is connected after described image acquisition component connection image denoising unit with image synthesis chip, described image synthesis chip For connection figure as being connected after frame filter device with greyscale transformation device, the greyscale transformation device passes through D/A converter and image display group Part connects.
Further, the video image synthesis chip uses chip ADV7123.
Further, the greyscale transformation device includes multiplier and adder.
Further, described image acquisition component includes ccd video camera and A/D converter, and the A/D converter is two Individual, the output port of two A/D converters inputs in a parallel fashion is connected to described image enhancing processing component.
Further, the first order RC circuits, which include resistance Rl and electric capacity Cl, the second level RC circuits, includes resistance R2 With electric capacity C10, the first end of the electric capacity Cl is connected with resistance Rl first end, and the of resistance Rl the second end and resistance R2 Two ends are connected, and electric capacity C1 the second end is connected with electric capacity C10 first end, and the of electric capacity C10 the second end and resistance R2 Two ends are all connected with input buffer circuit.
Further, triode Ql, resistance R3, resistance R4, resistance R5 and electric capacity are provided with the input buffer circuit The base stage at C2, the electric capacity C10 the second end the second end with resistance R3, resistance R4 first end and triode Q1 respectively is connected Connect, resistance R3 the second end is connected with triode Q1 colelctor electrode, triode Q1 emitter stage respectively with amplifying circuit and electricity Resistance R5 first end is connected, and institute electric capacity C2 and resistance R5 is in parallel, resistance R4 the second end respectively the second end with resistance R5, Resistance R2 the second end and amplifying circuit are connected.
Further, be provided with the amplifying circuit triode Q2, potentiometer W2, resistance R8, potentiometer W1, electric capacity C4, Resistance R7, electric capacity C5, resistance R9, potentiometer W2 the first fixing end colelctor electrode with triode Ql, the first of resistance R8 respectively End and output buffer are connected, potentiometer W2 the second fixing end connecting triode Q2 colelctor electrode, and the of potentiometer Wl One fixing end connecting triode Ql emitter stage, potentiometer Wl the second fixing end connecting triode Q2 emitter stage, potentiometer Wl adjustable end is connected by electric capacity C4 with triode Q2 emitter stage, triode Q2 emitter stage and resistance R7 first end It is connected, resistance R7 the second end is connected with resistance R5 the second end and output buffer respectively, triode Q2 base stage The second end with resistance R8, electric capacity C5 first end resistance R9 first end are connected respectively, resistance R9 the second end respectively with Electric capacity C5 the second end, resistance R7 the second end and output buffer are connected.
Further, RC band-pass circuits, the RC band logicals are additionally provided between the input buffer circuit and amplifying circuit Circuit includes electric capacity C3 and resistance R6, the electric capacity C3 first end connecting triode Q1 emitter stage, electric capacity C3 the second end It is connected respectively with resistance R6 first end and potentiometer Wl the first fixing end, the second end of the resistance R6 is with resistance R5's Second end is connected.
Further, triode Q3, electric capacity C6, resistance R10, resistance R11, diode are provided with the output buffer D1, resistance 12, resistance R13 and electric capacity C9, the triode Q2 colelctor electrode are connected by electric capacity C6 with triode Q3 base stage Connecing, resistance R10 first end is connected with triode Ql colelctor electrode and triode Q3 colelctor electrode respectively, and the of resistance R10 Two ends are connected by diode Dl with triode Q3 base stage, resistance R10 the second end by resistance R11 respectively with resistance R5 The second end be connected with resistance R12 the second end, the triode Q3 emitter stage first end and resistance with resistance R12 respectively R13 first end is connected, resistance R13 the second end connection electric capacity C9 first end.
The beneficial effects of the utility model are:
A kind of image signal processing apparatus provided by the utility model, strengthened again by carrying out first denoising to image, improved The enhancing effect of image.Processing system hardware of the present utility model is compact, runs relatively reliable, the enhancing effect of video image It is fairly obvious, it can effectively meet the high disposal quality requirement of medical image.
Brief description of the drawings
In order that the purpose of this utility model, technical scheme and beneficial effect are clearer, the utility model provides as follows Accompanying drawing illustrates:
Fig. 1 is theory diagram of the present utility model;
Fig. 2 is the circuit diagram of image denoising unit.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present utility model is described in detail.
As shown in figure 1, a kind of image signal processing apparatus, including image acquisition units, image enhancing unit and image show Show unit;Described image enhancement unit includes image denoising unit and image enhancing unit,
Described image denoising unit includes input band-pass circuit, input buffer circuit, amplifying circuit and output buffer, The input band-pass circuit connection input buffer circuit, the input buffer circuit connect amplifying circuit, and the amplifying circuit connects Connect output buffer;The first order RC circuits and second level RC circuits for inputting band-pass circuit and including being serially connected, and the Two level RC circuits are connected with input buffer circuit;Described image enhancement unit includes image synthesis chip, image frame filter Device and greyscale transformation device;It is connected after described image acquisition component connection image denoising unit with image synthesis chip, described image For synthesis chip connection figure as being connected after frame filter device with greyscale transformation device, the greyscale transformation device passes through D/A converter and figure As display module connects.
In the present embodiment, the video image synthesis chip uses chip ADV7123.Described greyscale transformation device includes Multiplier and adder.General to enter line translation using linear transformation function for greyscale transformation device, i.e. the gray value of original image is first Definite value k is multiplied by after multiplier, then adds definite value b, the gray value after as converting by an adder.
Described image acquisition component includes ccd video camera and A/D converter, and the A/D converter is two, is respectively Video input processor (VIP) SAA7111 the and AD company AD9235 of PHILIPS companies, two A/D converters Output port input in a parallel fashion be connected to described image enhancing processing component.
As shown in Fig. 2 described image denoising unit includes input band-pass circuit, input buffer circuit, amplifying circuit and defeated Go out buffer circuit, the input band-pass circuit connection input buffer circuit, the input buffer circuit connects amplifying circuit, described Amplifying circuit connects output buffer;The input band-pass circuit includes the first order RC circuits and second level RC being serially connected Circuit, and second level RC circuits are connected with input buffer circuit.
The first order RC circuits, which include resistance R1 and electric capacity Cl, the second level RC circuits, includes resistance R2 and electric capacity C10, the first end of the electric capacity Cl are connected with resistance Rl first end, resistance Rl the second end and resistance R2 the second end phase Connection, electric capacity C1 the second end are connected with electric capacity C10 first end, and electric capacity C10 the second end and resistance R2 the second end are all It is connected with input buffer circuit.
Triode Ql, resistance R3, resistance R4, resistance R5 and electric capacity C2, the electricity are provided with the input buffer circuit The base stage for holding C10 the second end the second end with resistance R3, resistance R4 first end and triode Ql respectively is connected, resistance R3 The second end be connected with triode Ql colelctor electrode, triode Ql emitter stage respectively with amplifying circuit and resistance R5 first End is connected, and institute electric capacity C2 and resistance R5 is in parallel, resistance R4 the second end the second end with resistance R5, the of resistance R2 respectively Two ends and amplifying circuit are connected.
Be provided with the amplifying circuit triode Q2, potentiometer W2, resistance R8, potentiometer W1, electric capacity C4, resistance R7, Electric capacity C5, resistance R9, potentiometer W2 the first fixing end colelctor electrode with triode Q1, resistance R8 first end and output respectively Buffer circuit is connected, potentiometer W2 the second fixing end connecting triode Q2 colelctor electrode, potentiometer Wl the first fixing end Connecting triode Ql emitter stage, potentiometer W1 the second fixing end connecting triode Q2 emitter stage, potentiometer Wl's is adjustable End is connected by electric capacity C4 with triode Q2 emitter stage, and triode Q2 emitter stage is connected with resistance R7 first end, Resistance R7 the second end is connected with resistance R5 the second end and output buffer respectively, triode Q2 base stage respectively with electricity Resistance R8 the second end, electric capacity C5 first end resistance R9 first end are connected, and resistance R9 the second end is respectively with electric capacity C5's Second end, resistance R7 the second end and output buffer are connected.
RC band-pass circuits are additionally provided between the input buffer circuit and amplifying circuit, the RC band-pass circuits include electricity Hold C3 and resistance R6, the electric capacity C3 first end connecting triode Ql emitter stage, electric capacity C3 the second end respectively with resistance R6 first end is connected with potentiometer Wl the first fixing end, and the second end of the resistance R6 is connected with resistance R5 the second end Connect.
Triode Q3, electric capacity C6, resistance R10, resistance R11, diode Dl, resistance are provided with the output buffer 12nd, resistance R13 and electric capacity C9, the triode Q2 colelctor electrode are connected by electric capacity C6 with triode Q3 base stage, resistance R10 first end is connected with triode Ql colelctor electrode and triode Q3 colelctor electrode respectively, and resistance R10 the second end passes through Diode D1 is connected with triode Q3 base stage, and resistance R10 the second end passes through resistance R11 the second ends with resistance R5 respectively Be connected with resistance R12 the second end, triode Q3 emitter stage respectively with resistance R12 first end and resistance R13 first End is connected, resistance R13 the second end connection electric capacity C9 first end.
Described image denoising unit also includes power supply circuit, and electric capacity C7, electric capacity C8 and confession are provided with the power supply circuit Power supply VCC, the electric capacity C7 and electric capacity C8 are parallel with one another, and electric capacity C7 after parallel connection and electric capacity C8 one end respectively with power supply electricity Source VCC is connected with triode Q1 colelctor electrode, the other end ground connection of the electric capacity C7 and electric capacity C8 after parallel connection.
The diode D1 uses light emitting diode, and diode Dl negative pole is connected with triode Q3 base stage, Design light emitting diode in output buffer, can effectively monitor output buffer whether operational excellence.
The electric capacity C1 and electric capacity C10 all use electrochemical capacitor, and electric capacity C1 positive pole is connected with electric capacity C10 negative pole Connect, electric capacity C10 positive pole is connected with triode Ql base stage.
Finally illustrate, preferred embodiment above is only unrestricted to illustrate the technical solution of the utility model, to the greatest extent The utility model has been described in detail by above preferred embodiment for pipe, but those skilled in the art should manage Solution, can make various changes, without departing from the utility model claims book institute to it in the form and details The scope of restriction.

Claims (9)

  1. A kind of 1. image signal processing apparatus, it is characterised in that:Shown including image acquisition units, image enhancing unit and image Unit;
    Described image enhancement unit includes image denoising unit and image enhancing unit,
    Described image denoising unit includes input band-pass circuit, input buffer circuit, amplifying circuit and output buffer, described Band-pass circuit connection input buffer circuit is inputted, the input buffer circuit connects amplifying circuit, and the amplifying circuit connection is defeated Go out buffer circuit;The input band-pass circuit includes the first order RC circuits and second level RC circuits being serially connected, and the second level RC circuits are connected with input buffer circuit;
    Described image enhancement unit includes image synthesis chip, image interframe wave filter and greyscale transformation device;
    It is connected after described image acquisition component connection image denoising unit with image synthesis chip, the connection of described image synthesis chip It is connected after image interframe wave filter with greyscale transformation device, the greyscale transformation device is connected by D/A converter and image display unit Connect.
  2. A kind of 2. image signal processing apparatus according to claim 1, it is characterised in that:Described image synthesis chip uses Chip ADV7123.
  3. A kind of 3. image signal processing apparatus according to claim 1, it is characterised in that:The greyscale transformation device includes multiplying Musical instruments used in a Buddhist or Taoist mass and adder.
  4. A kind of 4. image signal processing apparatus according to claim 1, it is characterised in that:Described image acquisition component includes Ccd video camera and A/D converter, and the A/D converter is two, the output port of two A/D converters is with parallel Mode input and be connected to described image enhancement unit.
  5. A kind of 5. image signal processing apparatus according to claim 1, it is characterised in that:The first order RC circuits include Resistance Rl and electric capacity Cl, the second level RC circuits include resistance R2 and electric capacity C10, the electric capacity Cl first end and resistance Rl First end be connected, resistance Rl the second end is connected with resistance R2 the second end, and electric capacity C1 the second end is with electric capacity C10's First end is connected, and electric capacity C10 the second end is all connected with resistance R2 the second end with input buffer circuit.
  6. A kind of 6. image signal processing apparatus according to claim 5, it is characterised in that:In the input buffer circuit Triode Ql, resistance R3, resistance R4, resistance R5 and electric capacity C2, the electric capacity C10 the second end are provided with respectively with resistance R3's The base stage at the second end, resistance R4 first end and triode Q1 is connected, resistance R3 the second end and triode Q1 colelctor electrode It is connected, the first end of triode Q1 emitter stage respectively with amplifying circuit and resistance R5 is connected, institute electric capacity C2 and resistance R5 It is in parallel, the second end with resistance R5, resistance R2 the second end and amplifying circuit are connected respectively at resistance R4 the second end.
  7. A kind of 7. image signal processing apparatus according to claim 6, it is characterised in that:It is provided with the amplifying circuit Triode Q2, potentiometer W2, resistance R8, potentiometer W1, electric capacity C4, resistance R7, electric capacity C5, resistance R9, the first of potentiometer W2 The colelctor electrode with triode Ql, resistance R8 first end and output buffer are connected fixing end respectively, and the of potentiometer W2 Two fixing end connecting triode Q2 colelctor electrode, potentiometer Wl the first fixing end connecting triode Ql emitter stage, potentiometer Wl the second fixing end connecting triode Q2 emitter stage, potentiometer Wl adjustable end pass through electric capacity C4 and triode Q2 transmitting Pole is connected, and triode Q2 emitter stage is connected with resistance R7 first end, and resistance R7 the second end is respectively with resistance R5's Second end is connected with output buffer, triode Q2 base stage the second end with resistance R8, electric capacity C5 first end respectively Resistance R9 first end is connected, resistance R9 the second end the second end with electric capacity C5, resistance R7 the second end and output respectively Buffer circuit is connected.
  8. A kind of 8. image signal processing apparatus according to claim 7, it is characterised in that:The input buffer circuit with RC band-pass circuits are additionally provided between amplifying circuit, the RC band-pass circuits include electric capacity C3 and resistance R6, the electric capacity C3's First end connecting triode Q1 emitter stage, electric capacity C3 the second end respectively with resistance R6 first end and potentiometer Wl first Fixing end is connected, and the second end of the resistance R6 is connected with resistance R5 the second end.
  9. A kind of 9. image signal processing apparatus according to claim 8, it is characterised in that:Set in the output buffer It is equipped with triode Q3, electric capacity C6, resistance R10, resistance R11, diode D1, resistance 12, resistance R13 and electric capacity C9, three pole Pipe Q2 colelctor electrode is connected by electric capacity C6 with triode Q3 base stage, and resistance R10 first end is respectively with triode Ql's Colelctor electrode is connected with triode Q3 colelctor electrode, the base stage phase that resistance R10 the second end passes through diode Dl and triode Q3 Connection, resistance R10 the second end are connected with resistance R5 the second end and resistance R12 the second end respectively by resistance R11, and three Pole pipe Q3 emitter stage is connected with resistance R12 first end and resistance R13 first end respectively, and resistance R13 the second end connects Connect electric capacity C9 first end.
CN201720684376.8U 2017-06-13 2017-06-13 A kind of image signal processing apparatus Expired - Fee Related CN206850886U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201720684376.8U CN206850886U (en) 2017-06-13 2017-06-13 A kind of image signal processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201720684376.8U CN206850886U (en) 2017-06-13 2017-06-13 A kind of image signal processing apparatus

Publications (1)

Publication Number Publication Date
CN206850886U true CN206850886U (en) 2018-01-05

Family

ID=60800078

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201720684376.8U Expired - Fee Related CN206850886U (en) 2017-06-13 2017-06-13 A kind of image signal processing apparatus

Country Status (1)

Country Link
CN (1) CN206850886U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111193840A (en) * 2018-10-29 2020-05-22 格科微电子(上海)有限公司 Method for realizing high-speed image sensor reading circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111193840A (en) * 2018-10-29 2020-05-22 格科微电子(上海)有限公司 Method for realizing high-speed image sensor reading circuit
CN111193840B (en) * 2018-10-29 2021-10-29 格科微电子(上海)有限公司 Method for realizing high-speed image sensor reading circuit

Similar Documents

Publication Publication Date Title
CN106066768A (en) PPT (Power Point) interaction demonstration device and method
CN102881159B (en) Embedded double-DSP (digital signal processing) information data processing device and method
CN206964461U (en) A kind of Intelligent mirror
CN206850886U (en) A kind of image signal processing apparatus
CN110262765A (en) Upright image full screen display process, relevant device and system
Yinli et al. The implementation of embedded image acquisition based on V4L2
CN206489625U (en) A kind of system that Classroom Teaching Quality Assessment is realized by face recognition technology
WO2022111717A1 (en) Image processing method and apparatus, and electronic device
CN107300779A (en) A kind of new medical imaging diagnosis device
CN202103784U (en) Dual stream video meeting system
CN205229072U (en) Target defect detecting device based on X ray
CN111447360A (en) Application program control method and device, storage medium and electronic equipment
CN207910927U (en) A kind of information collection bridge-set and imaging sensor quality automatic checkout equipment
CN202679478U (en) Digital image acquisition and processing platform
CN204636316U (en) A kind of Table top type consultation of doctors terminal system and apply the consultation of doctors terminating machine of this system
CN202142188U (en) Embedded double-DSP information data processing apparatus
CN204086740U (en) A kind of LCD display interface switching device
CN201481436U (en) Auxiliary system for medical CT image diagnosis
CN106791495A (en) Miniaturization infrared imaging device cartridge assemblies based on Soc
CN101904749A (en) Accessory system for medicine CT image diagnosis
CN207264789U (en) Medical information interactive system
CN202160252U (en) Digital television with built-in network terminal interface
CN206077525U (en) It is a kind of have automatically save image high photographing instrument system
CN206657387U (en) A kind of image processing circuit based on FPGA
CN104518516A (en) Control circuit of voltage-source static synchronous compensator

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180105

Termination date: 20180613

CF01 Termination of patent right due to non-payment of annual fee