CN206790805U - Circuit substrate - Google Patents

Abstract

Circuit substrate is the utility model is related to, configuration the 1st, the 2nd conductive pattern in the inside of circuit board, wiring pattern is set on surface.A pair of terminal pads are configured as clipping wiring pattern.Wiring pattern is connected to the 1st conductive pattern by the 1st path, and terminal pad is connected to the 2nd conductive pattern by the 2nd path.The termination capacitor of chip three has the size of the long side direction flat shape longer than the size of width.The 1st terminal is set at the both ends of the long side direction of the termination capacitor of chip three, the 2nd terminal is set at the both ends of width.The termination capacitor of chip three is installed in circuit board with posture of its long side direction along wiring pattern, and the 1st terminal is connected to wiring pattern, and the 2nd terminal is connected to terminal pad.1st path is configured in the position overlapped with the termination capacitor of chip three.

Description

Circuit substrate

Technical field

The utility model sets the circuit substrate for being provided with the termination capacitor of chip three.

Background technology

As the feed-through capacitor of excellent in high-frequency characteristics, what is utilized is the termination capacitor of chip three.Following patent documents 1 In, disclose the circuit that one kind is provided with the termination capacitor of chip three for the reduction for realizing equivalent series inductance (residual inductance) Substrate.

Reference picture 11A and Figure 11 B, the termination capacitor of chip three disclosed in patent document 1 and circuit substrate are entered Row explanation.

The internal structure of the termination capacitor 100 of chip three is represented in Figure 11 A.The termination capacitor 100 of chip three has almost For the profile of cuboid.Multiple insertion internal electrodes 101 and multiple ground connection internal electrodes 102 are alternately laminated.Penetrate internal electrode 101 play a role with ground connection internal electrode 102 as a pair of electrodes of capacitor.Internal electrode 101 is penetrated from the end of chip three One end of the long side direction of sub-capacitor 100 reaches the other end.Insertion internal electrode 101 is connected to one an end respectively Outside terminal 103, another outside terminal 104 is connected in another end.

Be grounded internal electrode 102 has the flat shape of almost crosswise respectively, at a pair orthogonal with width Expose side.Ground connection internal electrode 102 is connected in the part for being exposed to a side with a ground terminal 105, is being exposed to The part of another side is connected with another ground terminal 106.

The termination capacitor 100 of chip three is of virtually 4 terminals.Due to leading for the purpose of reducing equivalent series inductance Three termination capacitors of line type have 3 terminals, therefore in the capacitor by chip, are also habitually designated as " three ends Son ".

Thru passages 107 penetrate the termination capacitor 100 of chip three in a thickness direction.Thru passages 107 with insertion in The crossover location of portion's electrode 101, insertion internal electrode 101 is electrically connected to, by through being arranged at ground connection internal electrode 102 Opening 25, so as to be insulated with ground connection internal electrode 102.

Expression is provided with the stereogram of the conductor part of the circuit substrate of the termination capacitor 100 of chip three in Figure 11 B.In electricity The surface of base board, configure power source wiring line pattern 110,111 and ground connection wiring pattern 120,121.Power source wiring line pattern 110, 111 are configured along 1 imaginary line, and are mutually disconnected.Power source wiring line pattern 111 and the collection for being installed in circuit substrate Power supply terminal into circuit element 130 connects.Be grounded wiring pattern 120,121 along with power source wiring line pattern 110,111 along 1 orthogonal imaginary line of the imaginary line and be configured, in the open position identical with power source wiring line pattern 110,111 Position is mutually disconnected.

Mutually different layer in the inside of circuit substrate, configure voltage plane 115 and ground plane 125.Power-supply wiring figure Case 110,111 is connected to voltage plane 115 via path 116,118 respectively.Wiring pattern 120,121 is grounded respectively via path 122nd, 123 it is connected to ground plane 125.In the open position of power source wiring line pattern 110 and 111, path 117 is configured.Path 117 Extend from voltage plane 115 to surface.

The termination capacitor 100 of chip three is surface mounted in circuit substrate.The outside terminal of the termination capacitor 100 of chip three 103rd, 104 power source wiring line pattern 110,111 is connected to, ground terminal 105,106 is connected to ground connection wiring pattern 120th, 121, thru passages 107 are connected to path 117.

By setting thru passages 107 in the termination capacitor 100 of chip three, can reduce in power source wiring line pattern with connecing The equivalent series inductance formed between stratum.

Citation

Patent document

Patent document 1：Japanese Unexamined Patent Publication 2001-15885 publications

Utility model content

- the utility model problem to be solved-

The termination capacitor of chip three described in patent document 1 has the thru passages extended in the thickness direction thereof.Phase In general chip three termination capacitor to be used without thru passages, to reduce the technology of equivalent series inductance.

The purpose of this utility model is, there is provided one kind can use the termination capacitor of in general chip three, to reduce Imitate the circuit substrate of series inductance.

- the means to solve the problem-

Circuit substrate based on the 1st viewpoint of the present utility model has：

Circuit board, internally it is configured with the 1st conductive pattern and the 2nd conductive pattern；

Wiring pattern, it is arranged at the surface of the circuit board；

The terminal pad of a pair of conductive, on the surface of the circuit board, it is configured as clipping the wiring pattern；

The termination capacitor of chip three, is installed in the circuit board；

1st path of electric conductivity, the wiring pattern is electrically connected to the 1st conductive pattern；With

2nd path, a pair of terminal pads are electrically connected in the 2nd conductive pattern,

The termination capacitor of chip three has the size of the long side direction flat shape longer than the size of width, structure A pair of electrodes into electrostatic capacitance is arranged inside, is set with the 1st terminal being connected among a pair of electrodes In the both ends of the long side direction of the termination capacitor of chip three, it is connected with another among the pair of electrode The 2nd terminal be arranged at the both ends of width,

The termination capacitor of chip three is installed in the cloth with posture of its long side direction along the wiring pattern Line substrate, a pair of the 1st terminals are connected to the wiring pattern, and a pair of the 2nd terminals are connected to a pair of companies Connect disk,

1st path is configured in the position overlapped with the termination capacitor of chip three.

Because the termination capacitor of chip three with its long side direction is installed in circuit board along the posture of wiring pattern, because This wiring pattern is not disconnected in the underface of the termination capacitor of chip three.Therefore, it is possible to reduce the equivalent series of wiring pattern Inductance.

In the circuit substrate based on the 2nd viewpoint of the present utility model, in the composition of the circuit substrate based on the 1st viewpoint On the basis of,

Under vertical view, from by the center of a pair of the 2nd paths imaginary line connected to each other to the center of the 1st path Distance for the termination capacitor of chip three the long side direction size less than 1/2.

Due to the 1st path and the narrower intervals of the 2nd path, thus the magnetic flux based on the electric current flowed through in the 1st path with The magnetic flux flowed through in the opposite direction in 2nd path is offset.Therefore, it is possible to reduce the electric current including the 1st path and the 2nd path The equivalent series inductance in path.

In the circuit substrate based on the 3rd viewpoint of the present utility model, in the circuit substrate based on the 1st or the 2nd viewpoint Composition on the basis of,

Under vertical view, the 1st path and the 2nd path are configured as the center of a pair of the 2nd paths each other The imaginary line of link contacts with the 1st path.

Because the interval of the 1st path and the 2nd path more narrows, therefore can more reduce including the 1st path and the 2nd The equivalent series inductance of the current path of path.

The composition of circuit substrate based on the 4th viewpoint of the present utility model in the circuit substrate based on the 1st to the 3rd viewpoint On the basis of, also the wiring pattern is connected with the 1st conductive pattern with least one 3rd path, the 3rd path, quilt It is configured at and the termination capacitor of chip three coincidence and the position different with the 1st path.

Because wiring pattern and the 1st conductive pattern are connected by the 1st path and the 3rd path, therefore can reduce The equivalent series inductance for the current path that wiring pattern is connected with the 1st conductive pattern.

In the circuit substrate based on the 5th viewpoint of the present utility model, in the circuit substrate based on the 1st to the 4th viewpoint On the basis of composition,

A pair of the 2nd paths are configured in the inner side of the termination capacitor of chip three under vertical view.

Because the interval of the 1st path and the 2nd path more narrows, therefore can more reduce including the 1st path and the 2nd The equivalent series inductance of the current path of path.

In the circuit substrate based on the 6th viewpoint of the present utility model, in the composition of the circuit substrate based on the 5th viewpoint On the basis of, the wiring pattern is in the part clipped by a pair of terminal pads, described in the termination capacitor of chip three The part that the end of long side direction overlaps configures the 1st path compared to attenuating, in the part to attenuate.

Compared with the composition that the entirety of wiring pattern attenuates, the equivalent series inductance of wiring pattern can be reduced.

- utility model effect-

Because the termination capacitor of chip three with its long side direction is installed in circuit board along the posture of wiring pattern, because This wiring pattern is not disconnected in the underface of the termination capacitor of chip three.Therefore, it is possible to reduce the equivalent series of wiring pattern Inductance.

Brief description of the drawings

Fig. 1 is the stereogram of the construction for the conductor part for representing the circuit substrate based on embodiment 1.

Fig. 2A is the stereogram for the termination capacitor of chip three for being installed in the circuit substrate based on embodiment 1, and Fig. 2 B are Represent the in-built stereogram of the termination capacitor of chip three.

Fig. 3 is the top view of the termination capacitor of chip three and circuit board.

Fig. 4 A and Fig. 4 B are the sectional view at Fig. 3 4A of chain-dotted line 4A mono- and 4B-4B respectively.

Fig. 5 is the stereogram of the construction for the conductor part for representing the circuit substrate based on comparative example.

Fig. 6 A are the equivalent circuit diagrams of a part for the circuit substrate based on embodiment 1, and Fig. 6 B are based on the ratio shown in Fig. 5 Compared with the equivalent circuit diagram of a part for the circuit substrate of example.

Fig. 7 is the figure for the analog result for representing the impedance based on electromagnetic field simulator.

Fig. 8 A, Fig. 8 B and Fig. 8 C are to be installed in the circuit base based on embodiment 2, embodiment 3 and embodiment 4 respectively The termination capacitor of chip three of plate and the wiring pattern of circuit substrate, terminal pad, the top view of the 1st path and the 2nd path.

Fig. 9 is the stereogram of the conductor part of the circuit substrate based on embodiment 5.

Figure 10 is to be installed in the termination capacitor of chip three of the circuit substrate based on embodiment 6 and be arranged at circuit The wiring pattern on the surface of substrate, the top view of terminal pad.

Figure 11 A are the in-built stereograms for representing the existing termination capacitor of chip three, and Figure 11 B are to be installed in now The stereogram of the conductor part of the circuit substrate of some termination capacitors of chip three.

Embodiment

Reference picture 1~Fig. 4 B, are illustrated to the composition of the circuit substrate based on embodiment 1.In this manual, by shape Into having for the dielectric base plate of the conductive pattern connected between part to be referred to as into " circuit board ", by circuit board and it is mounted It is referred to as " circuit substrate " in the substrate that the part of the circuit board is formed.

The stereogram of the conductor part of the circuit substrate based on embodiment is represented in Fig. 1.In Fig. 1, dielectric is not represented Part.On the surface of circuit substrate, the termination capacitor 10 of chip three and integrated circuit component 30.In circuit substrate Portion, configure the 1st conductive pattern 21.Than 21 deeper position of the 1st conductive pattern, the 2nd conductive pattern 22 is configured.

On the surface of circuit board, setting extends to linear wiring pattern 23.Wiring pattern 23 connects in its one end Integrated circuit component 30.The terminal pad 24 of a pair of conductive is set on the surface of circuit board, to clip wiring pattern 23.

In the position clipped by a pair of terminal pads 24, the 1st path 26 of electric conductivity is configured.1st path 26 is by wiring pattern 23 are electrically connected to the 1st conductive pattern 21.A pair of terminal pads 24 by the 2nd path 28 of electric conductivity, are electrically connected to the 2nd conductor respectively Pattern 22.2nd path 28 is by through the opening 25 for being arranged at the 1st conductive pattern 21, so as to exhausted with the 1st conductive pattern 21 Edge.Wiring pattern 23 is electrically connected to the 1st by being configured at least one 3rd path 27 of the position different from the 1st path 26 Conductive pattern 21.In the example depicted in figure 1,2 the 3rd paths 27 are configured to clip the 1st path 26.

The termination capacitor 10 of chip three has the size of the long side direction flat shape longer than the size of width.In core The inside of the termination capacitor 10 of piece three sets a pair of electrodes, and electrostatic capacitance is formed by a pair of electrodes.In the terminal of chip three electricity The both ends of the long side direction of container 10, the 1st terminal 11 is set, at the both ends of width, a pair of the 2nd terminals 12 are set.Form One among a pair of electrodes of electrostatic capacitance is connected to the 1st terminal 11, and another is connected to the 2nd terminal 12.Reference picture below 2A and Fig. 2 B illustrate to the detailed configuration of the termination capacitor 10 of chip three.

The termination capacitor 10 of chip three is surface mounted in wiring with posture of its long side direction along wiring pattern 23 Substrate.A pair of the 1st terminals 11 are connected to 1 wiring pattern 23, and a pair of the 2nd terminals 12 are connected to a pair of terminal pads 24.1st Path 26 is configured in the position overlapped with the termination capacitor 10 of chip three.

As an example, the 2nd conductive pattern 22 is reduced to earthing potential, and supply voltage is provided to the 1st conductive pattern 21. Wiring pattern 23 is connected to the power supply terminal of integrated circuit component 30.The termination capacitor 10 of chip three as be inserted into ground wire with Feed-through capacitor (decoupling capacitor) between power-supply wiring and play a role.

The stereogram of the termination capacitor 10 of chip three is represented in Fig. 2A.The termination capacitor 10 of chip three has almost rectangular The profile of body.At the both ends of the long side direction of the termination capacitor 10 of chip three, the 1st terminal 11 is set respectively.1st terminal 11 covers The whole region of a pair of the end faces orthogonal with long side direction, and travel back across near the end of upper surface, bottom surface and side Region.In a pair of the sides orthogonal with width, the 2nd terminal 12 is set.2nd terminal 12 is for the long side direction of side It is configured in approximate centre.Further, the 2nd terminal 12 is travelled back across from the edge of upper surface and bottom surface towards the one of inner side Partial region.

The internal structure of the termination capacitor 10 of chip three is represented in Fig. 2 B.Flat multiple 1st electrodes 13 and multiple 2 Electrode 14 is alternately laminated.Adjacent the 1st electrode 13 and the 2nd electrode 14 are across dielectric layer and mutually insulated.Pass through the 1st electrode 13 With the 2nd electrode 14, electrostatic capacitance is formed.

1st electrode 13 reaches another end face from an end face of the long side direction of the termination capacitor 10 of chip three, and even It is connected to the 1st terminal 11.2nd electrode 14 exposes in a pair of sides orthogonal with width, is connected by the 2nd terminal 12. From the 1st conductive pattern 21 via the 1st path 26, the 3rd path 27 and wiring pattern 23 (Fig. 1), power supply is provided to the 1st electrode 13 Voltage.2nd electrode 14 is reduced to earthing potential via terminal pad 24, the 2nd path 28 and the 2nd conductive pattern 22 (Fig. 1).

The top view of the termination capacitor 10 of chip three and circuit board is represented in Fig. 3.The termination capacitor 10 of chip three with Posture of its long side direction along wiring pattern 23 and be installed in circuit board.Wiring pattern 23 is in the termination capacitor of chip three 10 underface is continuous to another end from an end of long side direction.A pair of terminal pads 24 clip wiring pattern 23.One A pair of the 2nd terminals 12 are connected to terminal pad 24.In the position overlapped respectively with terminal pad 24, the 2nd path 28 is configured. The position overlapped with wiring pattern 23, configure the 1st path 26 and at least one 3rd path 27.1st path 26 be configured as with The center of a pair of the 2nd paths 28 imaginary line connected to each other is contacted.

As an example, the length L of the termination capacitor 10 of chip three is 1.6mm, and width W1 is 0.8mm.Wiring pattern 23 width W2 is 0.4mm, and the diameter D1 of the 1st path 26, the 2nd path 28 and the 3rd path 27 is 0.3mm.Wiring pattern 23 The minimum clearance of design rule is set to the interval G of terminal pad 24.Minimum clearance be, for example, more than 0.1mm and Below 0.2mm scope.

The sectional view at Fig. 3 chain-dotted line 4A-4A is represented in Fig. 4 A.In the table for the circuit board 20 being made up of dielectric Face, wiring pattern 23 is set.In the both sides of wiring pattern 23, terminal pad 24 is set respectively.In the inside of circuit board 20, configuration 1st conductive pattern 21, the 2nd conductive pattern 22 is being configured than its deeper position.Wiring pattern 23 is connected to by the 1st path 26 1 conductive pattern 21.A pair of terminal pads 24 are connected to the 2nd conductive pattern 22 by a pair of the 2nd paths 28 respectively.2nd path 28 is upper Lower section penetrates the opening 25 for being arranged at the 1st conductive pattern 21 upwards.

The termination capacitor 10 of chip three is surface mounted in circuit board 20.A pair of the 2nd terminals 12 are connected to a pair Terminal pad 24.In the inside of the termination capacitor 10 of chip three, multiple 1st electrodes 13 and multiple 2nd electrodes 14 are alternately laminated.2nd Electrode 14 is connected to the 2nd terminal 12 at its both ends respectively.

The sectional view at Fig. 3 chain-dotted line 4B-4B is represented in Fig. 4 B.On the surface of circuit board 20, wiring pattern is set 23.1st terminal 11 of the termination capacitor 10 of chip three is connected to wiring pattern 23.Wiring pattern 23 is in the termination capacitor of chip three 10 underface, through the long side direction of the termination capacitor 10 of chip three.The 1st electrode 13 in the termination capacitor 10 of chip three connects It is connected to the 1st terminal 11.Wiring pattern 23 is connected to the 1st conductive pattern via the 1st path 26 and at least one 3rd path 27 21。

It is next, compared with the conventional example shown in Figure 11 A and Figure 11 B and the comparative example shown in Fig. 5 and right The excellent effect of above-described embodiment 1 illustrates.

The stereogram of the conductor part of the circuit substrate based on comparative example is represented in Fig. 5.In the embodiment 1 shown in Fig. 1, Wiring pattern 23 passes through in the underface of the termination capacitor 10 of chip three on long side direction.In the comparative example shown in Fig. 5, The underface of the termination capacitor 10 of chip three, wiring pattern 23 are disconnected in the longitudinal direction.The wiring pattern 23 being disconnected A part is connected to the 1st terminal 11 of the termination capacitor 10 of chip three, and another part is connected to another the 1st terminal 11. 1st path 26 (Fig. 1) is not set.

The equivalent circuit diagram of a part for the circuit substrate based on embodiment 1 is represented in Fig. 6 A.The termination capacitor of chip three 10 itself have the equivalent series inductance L1 that series connection is inserted into electric capacity.1st path 26 has an equivalent series inductance L2, a pair the 2nd Path 28 has equivalent series inductance L3 respectively.Wiring pattern 23 has equivalent series inductance L4.3rd path 27 respectively have etc. Imitate series inductance L5.Equivalent series inductance L2, L3, L4, L5 deteriorate the electrical characteristics for the electric circuit for being formed at circuit substrate.

The equivalent circuit diagram of a part for the circuit substrate based on the comparative example shown in Fig. 5 is represented in Fig. 6 B.In comparative example In, in the underface of the termination capacitor 10 of chip three, wiring pattern 23 is disconnected.Due to not configuring the 1st path 26, therefore do not deposit At equivalent series inductance L2 (Fig. 6 A).

The electric signal transmitted in wiring pattern 23 is travelled back across in the open position of the underface of the termination capacitor 10 of chip three Equivalent series inductance L1 possessed by equivalent series inductance L5 possessed by 3rd path 27 and the termination capacitor 10 of chip three.Cause This, the electric signal transmitted in wiring pattern 23 is except via equivalent series inductance L4, also via the inductance of circuitous path, i.e. equivalent Series inductance L1 or L5.

In the conventional example shown in Figure 11 B, also in the underface of the termination capacitor 100 of chip three, power source wiring line pattern 110 Mutually disconnected with 111.Therefore, in the same manner as the comparative example shown in Fig. 5, from power source wiring line pattern 110 via 111 and to integrated Circuit element 130 transmit electric signal via circuitous path inductance.

On the other hand, in embodiment 1, as shown in Figure 6A, wiring pattern 23 (Fig. 1) is in the termination capacitor 10 of chip three Underface be not disconnected.The electric signal not transmitted round in wiring pattern 23 is not via equivalent series inductance L1 and L5. Therefore, it is possible to provide integrated circuit component 30 stable power supply.

In the conventional example shown in Figure 11 A and Figure 11 B, as the termination capacitor 100 of chip three, it is necessary to using being provided with The part of the special tectonic of thru passages 107.On the other hand, as the core for being installed in the circuit substrate based on embodiment 1 The termination capacitor 10 of piece three, the common part for being not provided with thru passages 107 (Figure 11 A) can be used.

Further, in the conventional example shown in Figure 11 A and Figure 11 B, in order to be set in the termination capacitor 100 of chip three Thru passages 107 are put, it is unfavorable in terms of the miniaturization of the termination capacitor 100 of chip three.Further, in order to configure thru passages 107, the area of insertion internal electrode 101 part opposed with being grounded internal electrode 102 (Figure 11 A) diminishes.Therefore, in increase electricity It is also unfavorable to hold this respect.On the other hand, due to being installed in the termination capacitor 10 of chip three of the circuit substrate of embodiment 1 In do not configure thru passages 107, it is therefore favourable in the miniaturization of the termination capacitor 10 of chip three and high capacity this respect.

Further, in the circuit substrate based on embodiment 1, as shown in figure 3, the 1st path 26 and the quilt of the 2nd path 28 It is configured to the center of the 2nd path 28 straight contact connected to each other in the 1st path 26.With from by the center of the 2nd path 28 that The situation that this straight line linked discretely configures the 1st path 26 is compared, the narrower intervals of the 1st path 26 and the 2nd path 28.Cause This, the magnetic flux based on the electric current flowed through in the 1st path 26 and the magnetic based on the electric current flowed through in the opposite direction in the 2nd path 28 Flux effectively cancels out.Offset by magnetic flux, equivalent series inductance L2 and L3 combination inductance diminish.Due to based on equivalent The reduction of the performance of series inductance L1, L2 and L3 feed-through capacitor is suppressed, therefore can provide more stable power supply.

The analog result of the impedance based on electromagnetic field simulator is represented in Fig. 7.Analog result is represented from integrated shown in Fig. 1 Impedance when circuit element 30 is to observe mains side.It is simulated under conditions of wiring pattern 23 is terminated into 50 Ω.Fig. 7's Transverse axis represents frequency by unit " MHz ", and the longitudinal axis represents impedance by unit " Ω ".It is heavy line in Fig. 7 curve, thin Dotted line and thick dashed line represent based on the embodiment 1 shown in Fig. 1, the comparative example shown in Fig. 5, the conventional example shown in Figure 11 B respectively Circuit substrate impedance.In the arbitrary circuit substrate of simulated object, shared composition part all is the same size.

In the scope of the frequency less than about 100MHz, due to almost there is not the influence of equivalent series inductance, therefore As frequency rises, impedance reduces.If more than the resonant frequency of equivalent series inductance and electric capacity, the influence of equivalent series inductance Become big, as frequency rises, impedance uprises.

Resonance of the resonant frequency of circuit substrate based on embodiment 1 than the circuit substrate based on the comparative example shown in Fig. 5 Frequency is high.This is due to caused by equivalent series inductance diminishes.In addition, in the scope higher than resonant frequency, based on embodiment 1 Circuit substrate of the impedance ratio of circuit substrate based on the comparative example shown in Fig. 5 impedance it is low.By simplation validation by adopting With the construction of embodiment 1, equivalent series inductance diminishes.

It is if existing to the circuit substrate based on embodiment 1 compared with the circuit substrate of the conventional example shown in Figure 11 B The resonant frequency of the circuit substrate of example is higher.Further, in the scope higher than resonant frequency, the resistance of the circuit substrate of conventional example It is anti-relatively low.However, in the circuit substrate based on conventional example, it is necessary to using with the special of the thru passages 107 shown in Figure 11 A The termination capacitor 100 of chip three of construction.On the other hand, the circuit substrate based on embodiment 1 can use ordinary constitution The termination capacitor 10 (Fig. 2A, Fig. 2 B) of chip three.Circuit substrate based on embodiment 1 can use the common terminal of chip three Capacitor this respect, the circuit substrate than the conventional example shown in Figure 11 B are more excellent.

Next, reference picture 8A~Fig. 8 C, are illustrated to 2~embodiment of embodiment 4.Hereinafter, for embodiment 1 Difference illustrates, and is omitted the description for shared composition.

Expression is installed in the termination capacitor 10 of chip three and circuit base of the circuit substrate based on embodiment 2 in Fig. 8 A The wiring pattern 23 of plate, terminal pad 24, the top view of the 1st path 26 and the 2nd path 28.In order to reduce equivalent series inductance, It is preferred that make the 1st path 26 and the 2nd path 28 close.However, due to the relation with other conductive patterns, there is also be difficult to the 1st Path 26 is configured to the situation of the 1st path 26 and the straight contact through the center of 2 the 2nd paths 28.

In example 2, the 1st path 26 is configured in from the position of the straight line deviation at the center through 2 the 2nd paths 28 Put.But in order that the 1st path 26 and the 2nd path 28 are as far as possible close, the 1st path 26 is configured in and the terminal capacitance of chip three The position that device 10 overlaps.Due to wiring pattern 23 from an end of the long side direction of the termination capacitor 10 of chip three to another End is continuous, therefore compared with the situation that wiring pattern 23 is disconnected, the free degree of the configuration of the 1st path 26 is higher.In order to more Add and subtract small equivalent series inductance, preferably by from the straight line at the center through 2 the 2nd paths 28 to the center of the 1st path 26 away from From less than the 1/4 of the length L that D2 is set to the termination capacitor 10 of chip three.

Expression is installed in the termination capacitor 10 of chip three and circuit base of the circuit substrate based on embodiment 3 in Fig. 8 B The wiring pattern 23 of plate, terminal pad 24, the top view of the 1st path 26 and the 2nd path 28.In example 2, under vertical view, the 2nd Path 28 is configured in the inner side of the termination capacitor 10 of chip three.In order to which the 2nd path 28 is configured at into the termination capacitor of chip three 10 inner side, it is necessary to be set to the insertion depth D3 of the terminal pad 24 from the edge of the termination capacitor 10 of chip three internally at least With the diameter D1 same degrees of the 2nd path 28.

In order to which insertion depth D3 to be set to the diameter D1 same degrees at least with the 2nd path 28, and by wiring pattern 23 The minimum clearance degree based on design rule is set to the interval G of terminal pad 24, there is also must make wiring pattern 23 Situation thinner than the width W1 of the wiring pattern 23 (Fig. 3) of embodiment 1 width W3.As an example, in the terminal of chip three electricity In the case that the width W1 of container 10 is 0.8mm, width W3, the 1st path 26, the 2nd path the 28 and the 3rd of wiring pattern 23 are logical The all 0.2mm of diameter D1 and insertion depth D3 on road 27, interval G are 0.1mm.

In embodiment 3, the 1st path 26 can be made to be more nearly with the 2nd path 28.It is equivalent thereby, it is possible to more reduce Series inductance.

Expression is installed in the termination capacitor 10 of chip three and circuit base of the circuit substrate based on embodiment 4 in Fig. 8 C The wiring pattern 23 of plate, terminal pad 24, the top view of the 1st path 26 and the 2nd path 28.Shown in 2nd path 28 and Fig. 8 B Embodiment 3 similarly, is configured in the inner side of the termination capacitor 10 of chip three.In order between wiring pattern 23 and terminal pad 24 Ensure sufficient gap, the width W3 and the termination capacitor 10 of chip three of the part that the connected disk 24 of wiring pattern 23 clips The width W2 for the part that the both ends of long side direction overlap, which is compared, to attenuate.As an example, width W2 and width W3 are respectively 0.4mm and 0.2mm.1st path 26 is configured in the part to attenuate of wiring pattern 23.

In example 4, wiring pattern 23 can be connected in the case where not limiting the interval of 2 terminal pads 24 The part beyond the part that disk 24 clips is connect to widen.By the way that wiring pattern 23 is widened, the equivalent of wiring pattern 23 can be reduced Series inductance L4 (Fig. 6 A).

Next, reference picture 9, is illustrated to the circuit substrate based on embodiment 5.Hereinafter, for embodiment 1 not Illustrate with point, omitted the description for shared composition.

The stereogram of the conductor part of the circuit substrate based on embodiment 5 is represented in Fig. 9.In the circuit based on embodiment 1 In substrate, integrated circuit component 30 is connected to along the wiring pattern 23 (Fig. 1) of the long side direction of the termination capacitor 10 of chip three. In embodiment 5, a terminal pad 24 is connected to integrated circuit component 30 via wiring pattern 32.Wiring pattern 23 is via 1 path 26 and the 3rd path 27 and be connected to the 2nd conductive pattern 22.A pair of terminal pads 24 respectively via a pair of the 2nd paths 28 and It is connected to the 1st conductive pattern 21.

Wiring pattern 23 is reduced to earthing potential via the 1st path 26, the 3rd path 27 and the 2nd conductive pattern 22.From 1st conductive pattern 21 pays supply voltage via the 2nd path 28 to terminal pad 24.In embodiment 5, the feelings with embodiment 1 Condition on the contrary, be reduced to earthing potential with the 1st electrode 13 (Fig. 2 B) that the 1st terminal 11 of the termination capacitor 10 of chip three is connected, Apply supply voltage to the 2nd electrode 14 (Fig. 2 B) being connected with the 2nd terminal 12.

In embodiment 5, also core can be inserted into by series connection to reduce by making the 1st path 26 and the 2nd path 28 close The equivalent series inductance of the termination capacitor 10 of piece three.Thereby, it is possible to stable power supply is provided to integrated circuit component 30.

Next, reference picture 10, is illustrated to the circuit substrate based on embodiment 6.Hereinafter, for embodiment 1 Difference illustrates, and is omitted the description for shared composition.

Represent to be installed in the termination capacitor 10 of chip three of the circuit substrate based on embodiment 6 in Figure 10 and be set The top view of wiring pattern 23, terminal pad 24 in the surface of circuit substrate.In embodiment 1, as shown in figure 3, in a company Connect disk 24 and connect the 2nd path 28, the 1st path 26 is configured between 2 terminal pads 24.In embodiment 6, such as Figure 10 It is shown, multiple 2nd paths 28 are connected in a terminal pad 24, multiple 1st paths 26 are configured between 2 terminal pads 24.Scheming In example shown in 10,4 the 2nd paths 28 are connected in a terminal pad 24,4 the 1st paths are configured between 2 terminal pads 24 26。

By increasing the number of the 1st path 26 and the 2nd path 28, equivalent series inductance can be reduced.Led to by overstriking Road, it can also reduce equivalent series inductance.But if making the 1st path 26 and the 2nd path 28 thicker than other paths, path Perforate processing order complicate.By increasing the number of the 1st path 26 and the 2nd path 28, the 1st path 26 can be kept And the 2nd path 28 thickness identically with other paths, reduce equivalent series inductance.

In 1~embodiment of above-described embodiment 6, using the 1st electrode the 13 and the 2nd of the termination capacitor 10 of chip three is electric One of pole 14 (Fig. 2 B) is down to earthing potential, and the composition of supply voltage is provided to another.Form as others, also may be used To be down to earthing potential by one of the 1st electrode 13 and the 2nd electrode 14, and to the telecommunications beyond another offer supply voltage Number.

Each embodiment is example, can carry out local displacement or the group of composition shown in different embodiments certainly Close.The identical action effect formed for the identical based on multiple embodiments, is not referred to successively in each example. Further, the utility model is not restricted to the above embodiments.Those skilled in the art should understand for example enter The various changes of row, improvement, combination etc..

- symbol description-

The termination capacitor of 10 chip three

11 the 1st terminals

12 the 2nd terminals

13 the 1st electrodes

14 the 2nd electrodes

20 circuit boards

21 the 1st conductive patterns

22 the 2nd conductive patterns

23 wiring patterns

24 terminal pads

25 openings

26 the 1st paths

27 the 3rd paths

28 the 2nd paths

30 integrated circuit components

32 wiring patterns

The termination capacitor of 100 chip three

101 insertion internal electrodes

102 ground connection internal electrodes

103rd, 104 outside terminal

105th, 106 ground terminal

107 thru passages

110th, 111 power source wiring line pattern

115 voltage planes

116th, 117,118 path

120th, 121 ground connection wiring pattern

122nd, 123 path

130 integrated circuit components

Claims (6)

1. a kind of circuit substrate, has：

Circuit board, internally it is configured with the 1st conductive pattern and the 2nd conductive pattern；

Wiring pattern, it is arranged at the surface of the circuit board；

The terminal pad of a pair of conductive, on the surface of the circuit board, it is configured as clipping the wiring pattern；

The termination capacitor of chip three, is installed in the circuit board；

1st path of electric conductivity, the wiring pattern is electrically connected to the 1st conductive pattern；With

2nd path, a pair of terminal pads are electrically connected in the 2nd conductive pattern,

The termination capacitor of chip three has the size of the long side direction flat shape longer than the size of width, forms quiet A pair of electrodes of electric capacity is arranged inside, and institute is arranged at the 1st terminal being connected among a pair of electrodes The both ends of the long side direction of the termination capacitor of chip three are stated, be connected with another among the pair of electrode 2 terminals are arranged at the both ends of width,

The termination capacitor of chip three is installed in the wiring base with posture of its long side direction along the wiring pattern Plate, a pair of the 1st terminals are connected to the wiring pattern, and a pair of the 2nd terminals are connected to a pair of terminal pads,

1st path is configured in the position overlapped with the termination capacitor of chip three.

2. circuit substrate according to claim 1, wherein,

In the case of vertical view, the imaginary line connected to each other from the center of the 2nd path by a pair is into the 1st path The distance of the heart is less than the 1/2 of the size of the long side direction of the termination capacitor of chip three.

3. circuit substrate according to claim 1 or 2, wherein,

In the case of vertical view, the 1st path and the 2nd path be configured as by the center of a pair of the 2nd paths that This imaginary line linked contacts with the 1st path.

4. circuit substrate according to claim 1 or 2, wherein,

The circuit substrate also has at least one 3rd path, and the 3rd path is by the wiring pattern and the 1st conductor figure Case connects, and is configured in and the termination capacitor of chip three coincidence and the position different with the 1st path.

5. circuit substrate according to claim 1 or 2, wherein,

A pair of the 2nd paths are configured in the inner side of the termination capacitor of chip three in the case of vertical view.

6. circuit substrate according to claim 1 or 2, wherein,

The wiring pattern is in the part clipped by a pair of terminal pads, the long side with the termination capacitor of chip three The part that the end in direction overlaps configures the 1st path compared to attenuating, in the part to attenuate.