CN206790608U - A kind of matrix switcher - Google Patents
A kind of matrix switcher Download PDFInfo
- Publication number
- CN206790608U CN206790608U CN201720707004.2U CN201720707004U CN206790608U CN 206790608 U CN206790608 U CN 206790608U CN 201720707004 U CN201720707004 U CN 201720707004U CN 206790608 U CN206790608 U CN 206790608U
- Authority
- CN
- China
- Prior art keywords
- signal
- chip
- definition
- ultra high
- vision signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Landscapes
- Studio Circuits (AREA)
Abstract
A kind of matrix switcher is disclosed in the utility model embodiment, by carrying out CSC processing and/or DSC processing to ultra high-definition vision signal at transmitting terminal chip, on the premise of ultra high-definition video signal quality is not influenceed, reduce the code check of ultra high-definition vision signal, changed so as to reduce ultra high-definition vision signal, bandwidth required in switching and transmission, with the use of inexpensive performance in general Inverse problem chip, afterwards corresponding DSC data decompression and/or CSC processing are carried out in receiving terminal, recover the performance of ultra high-definition vision signal, above-mentioned matrix switcher disclosed in the utility model, on the premise of ultra high-definition signal quality is ensured, it is switching or the distribution function that ultra high-definition signal can be achieved with the switch or distributor of low cost.
Description
Technical field
It the utility model is related to signal processing technology field, and in particular to a kind of matrix switcher.
Background technology
HDMI (High-Definition Media Interface, HDMI) and DP
(Display Port, fine definition display interface) can transmit ultra high-definition signal, such as 4K signals, 8K signals, this ultra high-definition
Signal has without compression, lossless high-resolution and real-time characteristic, can be that user bring the listening of high-quality, visual impression
By.
This ultra high-definition signal can pass through switch or distributor to meet the needs of different user in transmitting procedure, but
It is that the chip of switch or distributor is made up of in parallel be cascaded of multiple MOS switches again, and this structure causes to switch
The increase of the parasitic capacitance and resistive linearity of device or distributor, and then cause ultra high-definition signal to be decayed rapidly, it can not finally ensure this
The signal of kind of ultra high-definition significantly reduces the use feeling of user without compression, lossless high-resolution and real-time characteristic.
At present, the chip of switch or distributor is fabricated by advanced chip manufacturing process, is switched in every one-level
The chip internal of device or distributor designs CDR (clock data recovery, clock and data recovery) circuits to eliminate bandwidth not
Foot and influence of the noise to signal quality, switching to the signal of ultra high-definition or distribution are realized by way of multi-stage cascade
Function, still, the chip cost of this switch or distributor is high, and power consumption is big.It is more at present to use HDMI in order to save cost
Or the signal of the ultra high-definition of DP agreements unpack after be compressed (e.g., JPEG, H.264 etc.), reconvert passes through into procotol
The switching of the network switch or FPGA (Field Programmable Gate Array, can programming in logic chip) to signal
Or distribution, then the signal after switching or distribution is decompressed, signal of the reconvert into HDMI or DP agreements.But this side
Formula can destroy the quality of ultra high-definition signal, especially in motion picture, or even have the situation of interim card, compress and decompress in addition
Process need long time, for the very high application scenarios of requirement of real-time, such as synchronous relay, seamless switching, trip
Play etc., which can not use.
Therefore, how on the premise of ultra high-definition signal quality is ensured, realized with the switch or distributor of low cost super
The switching of high-definition signal or distribution function, turn into those skilled in the art's technical problem urgently to be resolved hurrily.
Utility model content
In view of this, the utility model embodiment provides a kind of matrix switcher, can ensure ultra high-definition signal quality
On the premise of, realize switching or the distribution function of ultra high-definition signal with the switch or distributor of low cost.
To achieve the above object, the utility model embodiment provides following technical scheme：
A kind of matrix switcher, including：
M transmitting terminal chip, K Inverse problem chip and N number of receiving terminal chip；The M transmitting terminal chip passes through institute
State K Inverse problem chip with N number of receiving terminal chip to be connected, the K Inverse problem chip is used for described M transmission
At least one set of input signal that end chip is sent is forwarded to N number of receiving terminal chip, and described M, K, N are more than or equal to 1
Integer, and M, N value are all higher than K value；
Wherein, the transmitting terminal chip includes：
Signal for receiving ultra high-definition vision signal all the way and to the ultra high-definition vision signal unpack processing connects
Receive circuit；
Color space conversion CSC processing and/or either shallow are carried out for the ultra high-definition vision signal after handling the unpacking
The logic processor of vision signal after digital video bit stream compression DSC processing generation compressions；
For the vision signal after the compression to be sent to institute by 4 universal high speed differential serial interface SERDES
State the signal sending circuit of K Inverse problem chip；
The receiving terminal chip includes：
Believe for receiving the video after the compression exported by the K Inverse problem chip by 4 SERDES
Number signal receiving circuit；
For carrying out DSC data decompression and/or CSC processing generation decompressions to the vision signal after the compression
The logic processor of vision signal after contracting；
For carrying out recovering generation ultra high-definition vision signal and surpassing recovery to the vision signal after the decompression
High-definition video signal is sent to the signal sending circuit of external equipment.
Preferably, the ultra high-definition vision signal includes using HDMI HDMI agreements or high-resolution
Spend the ultra high-definition vision signal of display interface DP agreements.
Preferably, when the ultra high-definition vision signal is the ultra high-definition vision signal using DP agreements, the transmitting terminal
4 SERDES of the signal sending circuit of chip are used to send 4 circuit-switched data signals, when the high-definition video signal is using HDMI
During the ultra high-definition vision signal of agreement, 4 SERDES of the signal sending circuit of the transmitting terminal chip are used to send 3 circuit-switched datas
Signal and 1 tunnel clock signal.
Preferably, the signal sending circuit of the transmitting terminal chip also includes one for sending control signal and auxiliary letter
The two-way auxiliary control channel of breath.
Preferably, the transmitting terminal chip is special chip asic chip or can programming in logic chip fpga chip.
Preferably, the Inverse problem chip is model LT8644 Inverse problem chip.
Preferably, when 4 SERDES of the signal sending circuit of the transmitting terminal chip are used to send 4 circuit-switched data signals
When, 4 SERDES of the signal receiving circuit of the receiving terminal chip are used to receive 4 circuit-switched data signals；When the transmitting terminal core
When 4 SERDES of the signal sending circuit of piece are used to send 3 circuit-switched data signals and 1 tunnel clock signal, the receiving terminal chip
4 SERDES of signal receiving circuit be used to receive 3 circuit-switched data signals and 1 tunnel clock signal.
Preferably, the receiving terminal chip is asic chip or fpga chip.
Preferably, the value of the M is 8, and the value of the K is 2, and the value of the N is 8.
Based on above-mentioned technical proposal, a kind of matrix switcher is disclosed in the utility model embodiment, by transmitting terminal
CSC processing and/or DSC processing are carried out to ultra high-definition vision signal at chip, before ultra high-definition video signal quality is not influenceed
Put, reduce the code check of ultra high-definition vision signal, required for reducing ultra high-definition vision signal in conversion, switching and transmission
Bandwidth, with the use of inexpensive performance in general Inverse problem chip, carry out corresponding DSC data decompression in receiving terminal afterwards
Contracting processing and/or CSC processing, the performance of recovery ultra high-definition vision signal, above-mentioned matrix switcher disclosed in the utility model,
On the premise of ensureing ultra high-definition signal quality, with the switch or distributor of low cost be can be achieved ultra high-definition signal switching or
Distribution function.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only
It is embodiment of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, also
Other accompanying drawings can be obtained according to the accompanying drawing of offer.
Fig. 1 is a kind of structural representation for matrix switcher that the utility model embodiment provides；
Fig. 2 is a kind of structural representation of the transmitting terminal chip for matrix switcher that the utility model embodiment provides；
Fig. 3 is a kind of structural representation of the receiving terminal chip for matrix switcher that the utility model embodiment provides；
Fig. 4 is a kind of structural representation of the specific example for matrix switcher that the utility model embodiment provides；
Fig. 5 (a) to Fig. 5 (j) is that the inside of the switching chip for the model LT8644 that the utility model embodiment provides is patrolled
Collect overall schematic.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belong to the scope of the utility model protection.
One or more ultra high-definition audio-video signal can be transferred to by the matrix structure that matrix switcher forms M × N respectively
One or more display device, i.e., the output for having multichannel in the case where multichannel inputs select, that is to say, that every to export all the way
It can only all connect certain per output all the way from different input signal short circuits and inputs all the way, but certain inputs can all connect simultaneously all the way
Logical different output, its principle is to carry out on and off with closing using the conducting of chip internal circuits, and can pass through level
It is controlled the selection for completing signal.
Accompanying drawing 1 is referred to, Fig. 1 is a kind of structural representation for matrix switcher that the utility model embodiment provides, should
Matrix switcher includes M transmitting terminal chip 100, K Inverse problem chip 200 and N number of receiving terminal chip 300；The M hair
Sending end chip is connected by the K Inverse problem chip with N number of receiving terminal chip, and the K Inverse problem chip is used
N number of receiving terminal chip, described M, K, N are forwarded at least one set of input signal for sending the M transmitting terminal chip
It is the integer more than or equal to 1, and generally, M, N value are all higher than K value.That is, the utility model embodiment
The matrix switcher of offer can be 4x4,8x8 matrix or 4x2,10x16 etc. matrix, on the other hand, the utility model
Do not do any restrictions.The transmitting terminal chip be ASIC (Application Specific Integrated Circuit, specially
With chip) chip or FPGA (Field Programmable Gate Array, can programming in logic chip) chip.It is described to connect
Receiving end chip is asic chip or fpga chip.Inverse problem chip is generally multichannel input and the signal of multiple-channel output is free
Switching switch, signal way is more, and the parasitic load that it is carried is bigger, and the decay of signal is more serious.It should be noted that only
The chip for possessing Inverse problem function can be employed as Inverse problem chip of the present utility model, such as, model LT8644's
Inverse problem chip.
Accompanying drawing 2 is referred to, Fig. 2 is a kind of knot of the transmitting terminal chip for matrix switcher that the utility model embodiment provides
Structure schematic diagram, the transmitting terminal chip include：
Signal for receiving ultra high-definition vision signal and to the ultra high-definition vision signal unpack processing receives electricity
Road 1001；It should be noted that in the present embodiment, the ultra high-definition vision signal includes using HDMI agreements or DP agreements
Ultra high-definition vision signal.
CSC (Color Space Conversion, color are carried out for the ultra high-definition vision signal after handling the unpacking
Color space change) processing and/or either shallow digital video bit stream compression DSC (Digitial Stream Compression, either shallow
Digital video bit stream compresses) handle the logic processor 1002 for generating the vision signal after compressing；
For the vision signal after the compression to be sent to institute by 4 universal high speed differential serial interface SERDES
State the signal sending circuit 1003 of K Inverse problem chip.
It should be noted that when the ultra high-definition vision signal is the ultra high-definition vision signal using DP agreements, it is described
4 SERDES of the signal sending circuit of transmitting terminal chip are used to send 4 circuit-switched data signals, when the high-definition video signal is to adopt
During with the ultra high-definition vision signals of HDMI agreements, 4 SERDES of the signal sending circuit of the transmitting terminal chip are used to send 3
Circuit-switched data signal and 1 tunnel clock signal.
Explanation is needed further exist for, the signal sending circuit of the transmitting terminal chip also includes one and is used to send control
The two-way auxiliary control channel of signal and auxiliary information.Wherein, control signal generally refers to transmitting terminal chip and receiving terminal core
Piece realizes the control information of connection, including whether signal amplitude, training complete, if training etc. again again.Its
His auxiliary information includes the audio frequency and video form that external equipment such as display is supported, if supports the letter such as signal encryption, cryptographic handshake
Breath.
Accompanying drawing 3 is referred to, Fig. 3 is a kind of knot of the receiving terminal chip for matrix switcher that the utility model embodiment provides
Structure schematic diagram, the receiving terminal chip include：
Believe for receiving the video after the compression exported by the K Inverse problem chip by 4 SERDES
Number signal receiving circuit 3001；
It should be noted that when 4 SERDES of the signal sending circuit of the transmitting terminal chip are used to send 4 circuit-switched datas
During signal, 4 SERDES of the signal receiving circuit of the receiving terminal chip are used to receive 4 circuit-switched data signals；When the transmission
When holding 4 SERDES of the signal sending circuit of chip to be used to send 3 circuit-switched data signals and 1 tunnel clock signal, the receiving terminal
4 SERDES of the signal receiving circuit of chip are used to receive 3 circuit-switched data signals and 1 tunnel clock signal.
For carrying out DSC data decompression and/or CSC processing generation decompressions to the vision signal after the compression
The logic processor 3002 of vision signal after contracting；
For carrying out recovering generation ultra high-definition vision signal and surpassing recovery to the vision signal after the decompression
High-definition video signal is sent to the signal sending circuit 3003 of external equipment.
Accompanying drawing 4 is referred to, Fig. 4 is a kind of structure of the specific example for matrix switcher that the utility model embodiment provides
Schematic diagram, the matrix switcher provided in the example include 8 transmitting terminal chips (being LT86121TX shown in figure), 2 matrixes
Switch chip (being LT8644 shown in figure) and 8 receiving terminal chips (being LT86121RX shown in figure), 8 transmitting terminals
Chip is connected by 2 Inverse problem chips with 8 receiving terminal chips, and 2 Inverse problem chips are used for will
At least one set of input signal that 8 transmitting terminal chips are sent is forwarded to 8 receiving terminal chips.There is provided in this example
Matrix switcher can support 8 × 8 Inverse problem of ultra high-definition vision signal, i.e., maximum to support 8 road ultra high-definition vision signals
Enter, 8 road ultra high-definition vision signals go out.In this example, 2 Inverse problem chips are model LT8644 Inverse problem core
Piece, the Inverse problem chip of the model is simple 16 passage cross-point switch, and its internal logic overall schematic is such as
Shown in Fig. 5 (a) to Fig. 5 (j).Wherein, Fig. 5 (a) to Fig. 5 (d) combinations are LT8644 internal logic overall schematic, in order to
Specific internal logic is clearly showed that, Fig. 5 (e) to Fig. 5 (j) is the partial schematic diagram of LT8644 internal logic.
In this example, can be by 2 to 8 times of the ultra high-definition video signal compression of high bandwidth, specifically using CSC and DSC
, the ultra high-definition video that can be received according to the resolution requirement of external equipment, the way of matrix switcher, transmitting terminal chip
The video format that signal is supported, choose whether to use 4 in CSC：4:4-4:2:2, or 4：4:4-4:2:0 conversion, so as to drop
The bandwidth of low data, on this basis, it can also continue to select DSC compression ratio (1,2,3,4), further to reduce ultra high-definition
The bandwidth of vision signal code stream, while ensure higher image quality.Once it is determined that transmitting terminal chip CSC conversion mechanism and
DSC compression ratio, it just must be provided with configuring with transmitting terminal chip identical in receiving terminal chip, make the code of ultra high-definition vision signal
Stream is correctly recovered and played.The matrix of low order or higher order, it can analogize according to this structure.
It should be noted that in example shown in Fig. 4,8 road ultra high-definition video matrixes switchings can be achieved, less than 8 tunnels
Or the matrix more than 8 tunnels, the connected mode between transmitting terminal chip, Inverse problem chip and receiving terminal chip can basis
The connected mode of the model reference picture 4 of Inverse problem chip is realized.Specifically how to connect the utility model embodiment part no longer
Repeat.
In summary：
A kind of matrix switcher is disclosed in the utility model embodiment, by transmitting terminal chip to ultra high-definition video
Signal carries out CSC processing and/or DSC processing, on the premise of ultra high-definition video signal quality is not influenceed, reduces ultra high-definition video
The code check of signal, so as to reduce ultra high-definition vision signal conversion, switching and transmission in required for bandwidth, with the use of it is low into
This performance in general Inverse problem chip, corresponding DSC data decompression and/or CSC processing are carried out in receiving terminal afterwards,
Recover the performance of ultra high-definition vision signal, above-mentioned matrix switcher disclosed in the utility model, ensure ultra high-definition signal quality
On the premise of, it is switching or the distribution function that ultra high-definition signal can be achieved with the switch or distributor of low cost.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.For device disclosed in embodiment
For, because it is corresponded to the method disclosed in Example, so description is fairly simple, related part is said referring to method part
It is bright.
Professional further appreciates that, with reference to the unit of each example of the embodiments described herein description
And algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software, the composition and step of each example are generally described according to function in the above description.These
Function is performed with hardware or software mode actually, application-specific and design constraint depending on technical scheme.Specialty
Technical staff can realize described function using distinct methods to each specific application, but this realization should not
Think to exceed the scope of the utility model.
Directly it can be held with reference to the step of method or algorithm that the embodiments described herein describes with hardware, processor
Capable software module, or the two combination are implemented.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or new using this practicality
Type.A variety of modifications to these embodiments will be apparent for those skilled in the art, determine herein
The General Principle of justice can be realized in other embodiments in the case where not departing from spirit or scope of the present utility model.Cause
This, the utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The most wide scope consistent with features of novelty.
Claims (9)
- A kind of 1. matrix switcher, it is characterised in that including：M transmitting terminal chip, K Inverse problem chip and N number of receiving terminal chip；The M transmitting terminal chip passes through the K Inverse problem chip is connected with N number of receiving terminal chip, and the K Inverse problem chip is used for the M transmitting terminal core At least one set of input signal that piece is sent is forwarded to N number of receiving terminal chip, and described M, K, N are the integer more than or equal to 1, And M, N value are all higher than K value；Wherein, the transmitting terminal chip includes：For receiving ultra high-definition vision signal and to the ultra high-definition vision signal unpack the signal receiving circuit of processing；Color space conversion CSC processing and/or either shallow numeral are carried out for the ultra high-definition vision signal after handling the unpacking The logic processor of vision signal after video code flow compression DSC processing generation compressions；For the vision signal after the compression to be sent to the K by 4 universal high speed differential serial interface SERDES The signal sending circuit of individual Inverse problem chip；The receiving terminal chip includes：For receiving the vision signal after the compression exported by the K Inverse problem chip by 4 SERDES Signal receiving circuit；Decompression is generated for carrying out DSC data decompression and/or CSC processing to the vision signal after the compression The logic processor of vision signal afterwards；For carrying out recovering generation ultra high-definition vision signal and by the ultra high-definition of recovery to the vision signal after the decompression Vision signal is sent to the signal sending circuit of external equipment.
- 2. matrix switcher according to claim 1, it is characterised in that the ultra high-definition vision signal includes using high definition The ultra high-definition vision signal of clear degree multimedia interface HDMI agreements or fine definition display interface DP agreements.
- 3. matrix switcher according to claim 2, it is characterised in that when the ultra high-definition vision signal is to be assisted using DP During the ultra high-definition vision signal of view, 4 SERDES of the signal sending circuit of the transmitting terminal chip be used to send 4 ways it is believed that Number, when the high-definition video signal is the ultra high-definition vision signal using HDMI agreements, the signal hair of the transmitting terminal chip 4 SERDES on power transmission road are used to send 3 circuit-switched data signals and 1 tunnel clock signal.
- 4. matrix switcher according to claim 1, it is characterised in that the signal sending circuit of the transmitting terminal chip is also Including a two-way auxiliary control channel for being used to send control signal and auxiliary information.
- 5. matrix switcher according to claim 1, it is characterised in that the transmitting terminal chip is special chip ASIC cores Piece can programming in logic chip fpga chip.
- 6. matrix switcher according to claim 1, it is characterised in that the Inverse problem chip is model LT8644 Inverse problem chip.
- 7. matrix switcher according to claim 3, it is characterised in that when the signal sending circuit of the transmitting terminal chip 4 SERDES be used for send 4 circuit-switched data signal when, 4 SERDES of the signal receiving circuit of the receiving terminal chip are used for Receive 4 circuit-switched data signals；When 4 SERDES of the signal sending circuit of the transmitting terminal chip are used to send 3 circuit-switched data signals During with 1 tunnel clock signal, 4 SERDES of the signal receiving circuit of the receiving terminal chip are used to receive 3 circuit-switched data signals and 1 Road clock signal.
- 8. matrix switcher according to claim 1, it is characterised in that the receiving terminal chip be asic chip or Fpga chip.
- 9. matrix switcher as claimed in any of claims 1 to 8, it is characterised in that the value of the M is 8, described K value is 2, and the value of the N is 8.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720707004.2U CN206790608U (en) | 2017-06-16 | 2017-06-16 | A kind of matrix switcher |
| TW106124702A TWI632813B (en) | 2017-06-16 | 2017-07-24 | A matrix switcher |
| US16/007,321 US10397517B2 (en) | 2017-06-16 | 2018-06-13 | Matrix switcher |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720707004.2U CN206790608U (en) | 2017-06-16 | 2017-06-16 | A kind of matrix switcher |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206790608U true CN206790608U (en) | 2017-12-22 |
Family
ID=60717974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720707004.2U Withdrawn - After Issue CN206790608U (en) | 2017-06-16 | 2017-06-16 | A kind of matrix switcher |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206790608U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107707841A (en) * | 2017-06-16 | 2018-02-16 | 深圳朗田亩半导体科技有限公司 | A kind of matrix switcher |
| CN108540734A (en) * | 2018-05-16 | 2018-09-14 | 中央电视台 | A kind of switching method, device, system and the electronic equipment of 4K video/audio signals |
| CN109831671A (en) * | 2018-12-30 | 2019-05-31 | 东莞市爱协生智能科技有限公司 | The display stream compression coding module and display interface interactive device of computer readable storage medium and the application medium |
| CN110557581A (en) * | 2019-09-04 | 2019-12-10 | 南京图格医疗科技有限公司 | system for converting multiple interfaces into multiple interfaces under ultrahigh definition resolution and compatible method thereof |
| CN111343479A (en) * | 2020-03-04 | 2020-06-26 | 深圳市朗强科技有限公司 | Method and equipment for sending and receiving audio and video data in long-distance transmission scene |
-
2017
- 2017-06-16 CN CN201720707004.2U patent/CN206790608U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107707841A (en) * | 2017-06-16 | 2018-02-16 | 深圳朗田亩半导体科技有限公司 | A kind of matrix switcher |
| CN107707841B (en) * | 2017-06-16 | 2023-09-19 | 深圳朗田亩半导体科技有限公司 | Matrix switcher |
| CN108540734A (en) * | 2018-05-16 | 2018-09-14 | 中央电视台 | A kind of switching method, device, system and the electronic equipment of 4K video/audio signals |
| CN108540734B (en) * | 2018-05-16 | 2021-02-02 | 中央电视台 | Switching method, device and system of 4K video and audio signals and electronic equipment |
| CN109831671A (en) * | 2018-12-30 | 2019-05-31 | 东莞市爱协生智能科技有限公司 | The display stream compression coding module and display interface interactive device of computer readable storage medium and the application medium |
| CN109831671B (en) * | 2018-12-30 | 2021-05-18 | 深圳市爱协生科技有限公司 | Computer readable storage medium and display stream compression decoding module and display interface interaction device using same |
| CN110557581A (en) * | 2019-09-04 | 2019-12-10 | 南京图格医疗科技有限公司 | system for converting multiple interfaces into multiple interfaces under ultrahigh definition resolution and compatible method thereof |
| CN111343479A (en) * | 2020-03-04 | 2020-06-26 | 深圳市朗强科技有限公司 | Method and equipment for sending and receiving audio and video data in long-distance transmission scene |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206790608U (en) | A kind of matrix switcher | |
| CN107707841A (en) | A kind of matrix switcher | |
| US10169286B2 (en) | Devices and methods for providing reduced bandwidth DisplayPort communication | |
| TW201223290A (en) | Image data compression and decompression methods and display driving device using the same | |
| TW200820787A (en) | Method and system for performing two-dimensional transform on data value array with reduced power consumption | |
| TWI662837B (en) | Transmitting device, receiving device and non-transitory computer readable medium for compressed blanking period transfer over a multimedia link | |
| CN103118257A (en) | Data transmission integrated interface in high-definition video format | |
| CN102447867A (en) | Signal extender system and signal extender thereof | |
| CN105120184A (en) | High-definition video seamless matrix based on FPGA (field programmable gate array) | |
| CN103888844A (en) | High integration density wireless video transmission method and system | |
| CN205356397U (en) | Instant video player of 8K and broadcast system thereof | |
| CN106303582A (en) | A kind of Joint Source Channel decoding method and system | |
| CN108345559B (en) | Virtual reality data input device and virtual reality equipment | |
| CN206472189U (en) | A kind of ultra high-definition VR solid time delayers based on fpga chip module | |
| CN211557374U (en) | 4K ultra-high definition video control device | |
| CN207067943U (en) | A kind of device that the switching of KVM switcher flicker free is realized based on FPGA | |
| CN110474867A (en) | A kind of transmission method of multi-medium data, system and equipment | |
| CN103607553A (en) | Method for realizing 4k2k display based on frame sequence 3D format | |
| US10397517B2 (en) | Matrix switcher | |
| CN105828082A (en) | Video image rapid compression system and method | |
| Costa et al. | Wall screen: An ultra-high definition video-card for the internet of things | |
| CN112995675A (en) | Video acquisition compression and data encapsulation method suitable for airborne downloading | |
| CN213279882U (en) | Video compression coding service terminal | |
| CN103580673B (en) | The framework of high speed serialization transmitter | |
| CN209330259U (en) | Embedded video processing unit and multimedia equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20171222 Effective date of abandoning: 20230919 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20171222 Effective date of abandoning: 20230919 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |