CN106303582A - A kind of Joint Source Channel decoding method and system - Google Patents
A kind of Joint Source Channel decoding method and system Download PDFInfo
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- 238000013459 approach Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
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- 238000007689 inspection Methods 0.000 description 1
- 230000004899 motility Effects 0.000 description 1
- 238000011002 quantification Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
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- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
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Abstract
The invention provides a kind of Joint Source Channel decoding method and system, described method includes: transmitting terminal FPGA carries out pre-processing image data；Transmitting terminal DSP carries out compression of images, RS coding and the Joint Source/channel Coding Design interweaved；Receiving terminal DSP is deinterleaved, RS decodes and image decompressor operation；Receiving terminal FPGA carries out view data reduction and output.The such scheme that the present invention provides, for the real-time video transmission under complicated wireless channel, add RS coding by compression of images and add the Joint Source/channel Coding Design of intertexture, it is possible to successfully solve image transmission problem under interference channel, thus improve the quality of service of transmission of video.
Description
Technical field
The invention belongs to field of multimedia communication, especially relate to a kind of Joint Source Channel decoding method and system.
Background technology
Along with developing rapidly of digital communication, computer network and multimedia technology, multimedia communication has become as one
Inevitably trend.Data can be divided into process for multimedia communication and data transmit two parts, corresponding to Video Applications system, and one
As be source coding and channel coding.Source coding and channel coding is separately considered by traditional Shannon separation principle, but
Current research shows, the mode of this absolute separation is unable to reach high efficient and reliable transmission multimedia number under the present art
According to purpose, it is therefore desirable to combine consideration message sink coding and chnnel coding, it is achieved Joint Source/channel Coding Design.
Joint Source/channel Coding Design technology can be divided three classes by the tightness degree according to source-channel coding coupling:
The most tightly coupled combined signal source-chnnel coding, this technology source coding and channel coding is joined together consider,
Propose chnnel coding or the message sink coding scheduling algorithm of channel optimization that information source controls.Set yet with this kind of combined coding mode
Meter gets up excessively complicated, and therefore must limit based on source encoder and channel encoder known to certain characteristic
Its range of application, is not the most the emphasis of research；
2. the unequal protection source-channel coding of loose coupling, this technology is by adjusting the protection granularity of chnnel coding
Protect the data of the different severity levels that information source exports.The application of this kind of combined coding technology is more, and existing part is practical.
But trace sth. to its source still without departing from traditional Shannon information theory, simply improve chnnel coding adapting to the output code flow of message sink coding
?；
3. the source-channel coding that the parametric joint between the above two optimizes, the information source that oneself is known by this technology is compiled
Code device and channel encoder level link up, and keep the independence between two encoders, but their coding of combined optimization is joined
Number, to realize the purpose of combined coding.
Currently, the 3rd class combined coding technology is the main flow direction of Joint Source/channel Coding Design.Many for unreliable channel
Channel status in media communication, by the transmission bandwidth between reasonable distribution original multimedia data and protection data, it is achieved
Information source and the reasonable distribution of channel redundancy degree, and then realize the signal source and channel system that parametric joint optimizes.This information source is believed
On the one hand road combined coding technology can reduce the implementation complexity of system, simultaneously can be by the speed between information source and channel
Distribution realizes the purpose of combined coding, is a kind of compromise and efficient coding mode.
But, the wireless channel in wartime is constantly present the various impacts such as noise, interference, multipath fading, transmission letter
The bandwidth occupancy in road is big, and image transmitted noise under interference channel is serious, causes the second-rate of the business such as real-time video, no
Business demand can be met.
Summary of the invention
Present invention aim at providing a kind of Joint Source Channel decoding method and system, to solve prior art passes
The bandwidth occupancy of defeated channel is big, image transmitted noise under interference channel is serious, causes the quality of the business such as real-time video relatively
The technical problem of difference, thus improve the quality of service of transmission of video.
The technical scheme provided for this present invention is as follows:
A kind of Joint Source Channel decoding method, including:
Transmitting terminal FPGA carries out pre-processing image data；
Transmitting terminal DSP carries out compression of images, RS coding and the Joint Source/channel Coding Design interweaved；
Receiving terminal DSP is deinterleaved, RS decodes and image decompressor operation；
Receiving terminal FPGA carries out view data reduction and output.
Described transmitting terminal FPGA carries out pre-processing image data, including:
Frame synchronizing signal in monitoring view data, determines that video initiates；
Carry out down-sampled and format change process.
Described receiving terminal FPGA carries out view data reduction and output, including:
The frame synchronizing signal of monitoring view data, determines that video initiates；
Carry out liter sampling and format change processes.
The described Joint Source/channel Coding Design being interleaved, including:
Channels with memory are converted to random memoryless channel by Design of Signal by definition coded frame structure.
Corresponding to said method, present invention also offers a kind of Joint Source Channel coding/decoding system, including:
Transmitting terminal FPGA, is used for carrying out pre-processing image data；
Transmitting terminal DSP, for carrying out compression of images, RS coding and the Joint Source/channel Coding Design interweaved；
Receiving terminal DSP, is used for being deinterleaved, RS decoding and image decompressor operation；
Receiving terminal FPGA, is used for carrying out view data reduction and output.
Described transmitting terminal FPGA includes:
First detector unit, for monitoring the frame synchronizing signal in view data, determines that video initiates；
Down-sampled unit, is used for carrying out down-sampled；
First formatting unit, is used for carrying out format change process.
Described receiving terminal FPGA includes:
Second detector unit, for monitoring the frame synchronizing signal in view data, determines that video initiates；
Rise sampling unit, be used for carrying out a liter sampling；
Second formatting unit, is used for carrying out format change process.
Described transmitting terminal DSP includes:
Image compression unit, for being compressed processing to the view data of transmitting terminal FPGA output；
RS coding unit, is used for carrying out RS chnnel coding；
Interleave unit, processes for block interleaving.
Described transmitting terminal DSP includes:
Deinterleave unit, for being deinterleaved processing according to the interleave depth of interleave unit；
RS decoding unit, for carrying out channel decoding according to the RS channel of RS coding unit；
Image decompressor unit, is used for carrying out image decompressor process, recovers view data.
The present invention compared with prior art provides the benefit that:
The such scheme that the application provides, for the real-time video transmission under complicated wireless channel, is added by compression of images
RS coding adds the Joint Source/channel Coding Design of intertexture, it is possible to successfully solves image transmission problem under interference channel, thus carries
The quality of service of high transmission of video.
The program uses forward error correction coding to carry out non-uniform FDTD grids, considers that increasing forward error correction coding takies additionally simultaneously
The channel width impact on information source transmission code rate, using unified Joint Source/channel Coding Design statistics rate-distortion model as constraint,
Optimized distribution signal source and channel code check, thus improve the quality of service of transmission of video.
Meanwhile, program interleaving technology introduces associating encoding and decoding, and custom coding frame structure, by Design of Signal by original
Belong to the channels with memory of burst error, be transformed into the random memoryless channel of approximation independent error, in image delivering system
Meet reality and apply anti-error code demand, particularly improve the error burst ability that anti-multipath effect attracts, be effectively increased connection
Compile in collaboration with the error correcting capability of decoding system.
Accompanying drawing explanation
Fig. 1 is a kind of Joint Source Channel decoding method schematic flow sheet that the present invention provides；
Fig. 2 is the control flow chart of the transmitting terminal FPGA that the present invention provides；
Fig. 3 is the compression of images control flow chart of the transmitting terminal DSP that the present invention provides；
Fig. 4 is the RS coding-control flow chart of the transmitting terminal DSP that the present invention provides；
Fig. 5 is the decoding flow chart of the RS of the receiving terminal DSP that the present invention provides；
Fig. 6 is the image decompressor control flow chart of the receiving terminal DSP that the present invention provides；
Fig. 7 is the image output flow chart of the receiving terminal FPGA that the present invention provides；
Fig. 8 is a kind of Joint Source Channel coding/decoding system configuration diagram that the present invention provides.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
Embodiment one:
Present embodiments provide a kind of Joint Source Channel decoding method, as it is shown in figure 1, be a kind of flow process of the method
Schematic diagram, specifically includes following steps:
Step S101, transmitting terminal FPGA carries out pre-processing image data；
In the real time video signals processing system of the present embodiment application, the data volume of the Signal Pretreatment algorithm process of low layer
Greatly, the requirement to processing speed is high, but operating structure is relatively simple, is suitable to carry out hardware realization with FPGA, so can be same
Time take into account speed and motility.
Wherein, the process of described pretreatment can include following sub-step:
S101a, the frame synchronizing signal in monitoring view data, determine that video initiates；
After system powers up, first have to configure video decoding chip ADV7180；ADV7180 decoding chip is that one comprehensively regards
Frequently decoder, it can automatically detect the ABB video signal of compatible international standard NTS C, PAL and SECAM, and by it
Be converted to the video data of compatible 8 ITU-R BT.656 interface standards.
The analog picture signal of outside pal mode, after ADV7180 chip is sampled, is quantified as 720x576 size, YUV
8 bit digital picture signals of form, this image (720x576) Frame is defined as follows:
The most each data frame length 480 byte, all has synchronous head；
B. frame structure: synchronous head 3 byte；Identifying+index 1 byte, the highest 4 is image identifier, and 0x0 represents the 1st
Road, 0xF represents the 2nd tunnel, and low 4 is index count；Data 476 byte.
Introduce state machine mechanism and receive Digital Image Data, monitor frame synchronizing signal, determine that a frame video initiates, specifically
For: location search is set and stably receives two states；After system powers up, start sequential caching 3 byte image data, first enter
Enter location search state, judge data cached whether to meet synchronous head byte in each clock cycle, as do not met, continue to position
Search, as met, is defined as a frame video original position, arranges frame synchronizing signal effectively (high level is effective), and effective time is
One clock cycle, simultaneously enter stable reception state；When stable reception state, counters count output word joint number is set, when arriving
When reaching frame synchronization head position, still to judge data cached whether to meet synchronous head byte, as met, continue to stay and stably connect
Receiving state, arrange frame synchronizing signal effective, as do not met, be defined as frame synchronization losing lock, frame synchronizing signal is invalid, and restoring to normal position is searched
Rope state；So conditional jump, moves in circles.
S101b, carries out down-sampled and format change process.
After frame synchronization determines a frame video original position, the same employing state machine mechanism row and column difference to image
Carry out down-sampling, only retain the pixel in even row and even column, and delete the pixel in strange row and odd column, thus be transformed to standard
CIF form (Common Intermediate Format, 352 × 288 pixels) view data, particularly as follows: arrange frame synchronization inspection
Rope and two states of down-sampled process；After system powers up, initially enter frame synchronization retrieval state, same at retrieval of each clock cycle frame
Step signal is the most effective, otherwise continues to stay frame synchronization retrieval state, the most then enters down-sampled process state；In down-sampled process state
Time, it is respectively provided with image data lines, column counter, in each clock cycle, during as judged count value as even row and even column, output
The image pixel value of present clock period；When judging count value as even row and odd column, keep the even column figure of previous clock cycle
As pixel value, the most do not export the image pixel value of current odd column；Judge when row count value is strange row, do not export all figures of this journey
As pixel value；Frame synchronization retrieval state is returned at the end of counting statistics to a frame video；So conditional jump, moves in circles.
Native system uses EMIF based on DSP (External Memory Interface, external memory interface) to pass through
EDMA moving data realizes the parallel transmission of data between FPGA, considerably increases the reliability of system.EMIF is one
The exented memory interface of 64bit. maximum bus speed is 133M, can support that four sheets select space, by activating difference storage
The enable in space realizes the access to different spaces.FPGA is regarded as a plug-in memorizer of DSP, EMIF implementation
Mainly having two kinds: one, according to actual needs by modifying the sequential carrying module, this method for designing seems ratio
Relatively simple, but the program normally transparent degree designed by this method is poor, flexibility ratio is the highest, limits the use of this method；
Its two, use user from the program write, FPGA to be controlled, this method seems more complicated than first method, but compares
Relatively flexible, versatility is higher. and transplantability is relatively good.Native system uses latter approach to realize the DSP access to FPGA RAM district.
Simultaneously take account of the asynchronous behavior of EMIF, in FPGA, have employed ping-pang cache structure, be provided with ping and pong two caching
District, particularly as follows: after program brings into operation, DSP sends to FPGA and starts control instruction, and FPGA system is started working；FPGA time
That opens ping caching under the control of clock signal writes enable, and the view data after down-sampled is write the ping caching in FPGA
In；When ping caching write full after, close ping caching and write enable, open pong caching write enable send simultaneously interrupt signal to
DSP；DSP has no progeny in receiving, and the data that ping is filled with by startup EDMA are once moved in the caching in DSP.When in FPGA
After pong caching is write completely, close pong caching and write enable, open ping caching and write enable, send out interruption to DSP simultaneously；DSP receives
In have no progeny. start to start data-moving that pong is filled with by EDMA in DSP inner buffer；So go round and begin again and realize FPGA and arrive
The caching of DSP data and moving.
Step S102, transmitting terminal DSP carries out compression of images, RS coding and the Joint Source/channel Coding Design interweaved；
In above-mentioned real time video signals processing system, the feature of high-rise Processing Algorithm is that handled data volume lower level is calculated
Method is few, but the control structure of algorithm is complicated, is suitable to the dsp chip that arithmetic speed is high, addressing system is flexible, communication mechanism is powerful
Realize.
In this step, transmitting terminal DSP first passes through configuration EMIF interface, makes DSP produce and reads clock, reading enable signal, connects
Receive the frame interruption of FPGA output, row interrupt signal, thus receive parallel raw digital image data, then start compression of images,
Exporting compression of images code stream with constant bit rate to FPGA by synchronous serial interface after compression, control flow is as shown in Figure 3.
Wherein image compression module uses hybrid coding scheme based on block prediction, pre-in have employed the frame of many predictive modes
Survey coding techniques, fine inter prediction encoding technology, integer transform and quantification technique, scene adaptive variable length code
Technology, loop filter deblocking distortion effect technology, fully improve picture compression efficiency.
For specific DSP platform in image compression module Project Realization, on the one hand use video input sampling and pressure
Contracting concurrent technique, within being hidden in video sampling input time by a part of video compression coding time；On the one hand use special
SIMD instruction level optimize, improve coding and decoding video arithmetic speed, thus reduce encoding and decoding time delay.
Secondly, RS chnnel coding is carried out at dsp processor.For the real-time video transmission under complicated wireless channel, use
FEC (Forward Error Correction, forward error correction coding) carries out non-uniform FDTD grids, considers to increase FEC coding simultaneously
Take the impact on information source transmission code rate of the extra channel bandwidth, make with unified Joint Source/channel Coding Design statistics rate-distortion model
For retraining, optimized distribution signal source and channel code check, thus improve the quality of service of transmission of video.
Wherein chnnel coding can be chosen as RS (255,239) or RS (255,223), as a example by RS (255,239), and ginseng
Number is defined as follows:
Territory generator polynomial is F (x)=x8+x4+x3+x2+ 1, GF (2)；
Code generator polynomial is g (x)=(x+ α) (x+ α2)(x+α3)…(x+α15)(x+α16), GF (28)；
RS coding circuit uses division circuit to realize coding.First input data are divided into the code character that code length is 239 bytes,
Then each code character carries out shifting the computing of rear mold g (x), after finally exporting the coding with 16 check information bytes
Data.
The major part of coding circuit is one group of linear feedback shift register (LFSR), as shown in Figure 4.Circuit is worked
Journey is as follows:
First, all of shifting memory is clearly 0, and gate circuit is connected, and A end got to by on-off circuit.Then start to input data,
Shift, the most directly output of input data, be on the other hand automatically multiplied by xn-kG (x) division circuit is entered after secondary, thus
Complete xn-kThe effect of m (x).
2. after k displacement, m (x) all sends into circuit, completes division effect, now saves residue r in shifting memory
X the coefficient of (), verifies unit in the case of binary exactly.
The most now gate circuit is closed, and B end got to by on-off circuit, then after n-k time shifts, complete for the verification unit of shifting memory
Portion exports, with code word C (x) that original k position information word constitutes an a length of n.
4. gate circuit is again switched on, and A end got to by on-off circuit, sends into second group of information group and repeats said process.
Finally, carrying out block interleaving process at dsp processor, interleave depth is optional.Interleaving treatment can self-defined be compiled
Channels with memory are converted to random memoryless channel by Design of Signal by code frame structure.
In order to the incidence rate making burst error that decoder exports is minimum, reduce the dependency of mismark in RS code word,
Prevent from exceeding the error correcting capability of RS decoder, use the way interweaved；At DSP transmitting terminal, coded sequence is sending into transmission
First pass through one " intertexture register matrix " before.List entries is stored in line by line register matrix, after being filled with, secondary by arrange
Sequence is taken out, and is re-fed into transmission channel.
Interleaving technology is introduced associating encoding and decoding by this step, can be with custom coding frame structure, by Design of Signal by former
Belong to the channels with memory of burst error, be transformed into the random memoryless channel of approximation independent error, at image delivering system
In disclosure satisfy that actual application anti-error code demand, particularly improve the error burst ability that anti-multipath effect attracts, Ke Yiyou
Effect improves the error correcting capability of associating coding/decoding system.
Step S103, receiving terminal DSP is deinterleaved, RS decodes and image decompressor operation；
This step is corresponding with step S102, is the inverse process of step S102, and the data that receiving terminal DSP receives after interweaving are carried out
Joint source channel decoding；
Specifically include following steps:
First, being deinterleaved processing at dsp processor, corresponding transmitting terminal DSP design interleave depth is optional.
After receiving terminal DSP receives data, first sequence is stored to one with the intertexture register matrix making a start identical, but with send out
The order contrast of end access, is stored in by the order of row, after being filled with, takes out by the order of row, is then sent through RS decoder.
Therefore the sequence being sent into RS decoder is identical with the sequence order that RS encoder exports, and friendship do not felt by RS decoder at all
Knit the presence or absence of matrix.
Secondly, RS channel decoding, corresponding transmitting terminal DSP design RS (255,239) or RS are carried out at dsp processor
(255,223) are optional, and control flow is as shown in Figure 5.Decoding algorithm based on syndrome is a kind of effective calculation realizing RS decoding
Method.It is a kind of iterative algorithm, it is easy to dsp program realizes.This algorithm includes following four step:
A, according to receive code word seek syndrome S；
B, determine error location polynomial Λ (x) by iterative method；
C, Yong Qianshi searching algorithm determines the root of error location polynomial Λ (x), i.e. errors present number；
D, seek improper value with width Buddhist nun (Forney) algorithm, and correct mistake.
Finally, carry out image decompressor process at dsp processor, revert to standard CIF form (Common
Intermediate Format, 352 × 288 pixels) view data, control flow is as shown in Figure 6.
Wherein image decompressor module is the inverse process of image compression module, except using length-changeable decoding technology, inverse
Change the technology such as inverse transformation and recover outside image, also use video decompression to export concurrent technique with outer simultaneous display, a part is regarded
Frequently, within the decompression time is hidden in signal output time, reduces video decoding delay largely and outer synchronization waits time delay.
Step S104, receiving terminal FPGA carries out view data reduction and output.
Wherein, this step is corresponding with the described pretreatment of step S101, and the process carrying out view data reduction can include
Following sub-step:
Step S104a, receives the view data after decompressing by EMIF, determines that video initiates；
Receiving terminal FPGA receives the CIF format picture data after the decompression of DSP output by EMIF, is equally based on asynchronous
The consideration of data exchange have employed ping-pang cache structure in FPGA, is provided with two buffer areas of ping and pong, particularly as follows: journey
After sequence brings into operation, DSP sends to FPGA and starts control instruction, and FPGA system is started working；FPGA is in the control of clock signal
Lower closedown ping caching is read to enable, and opens pong caching and reads to enable, and sending during interrupt signal receives to DSP, DSP has no progeny simultaneously opens
Move in the ping caching moving FPGA the caching in DSP of the view data after EDMA will decompress；When ping caching is write
Man Hou, close pong caching read enable, open ping caching read enable, delta frame synchronizing signal, simultaneously send interrupt signal to
DSP, DSP have no progeny in receiving and start the pong moving FPGA the caching in DSP of the view data after EDMA will decompress
In caching；After pong caching is write completely, closedown ping caches and reads to enable, and opens pong and caches reading enable, delta frame synchronizing signal；
So go round and begin again and realize DSP and to the caching of FPGA data and move.
Step S104b, carries out liter sampling and format change processes.
Concrete application example is as follows:
After determining a frame video original position, use state machine mechanism that the row and column of image carries out a liter sampling respectively, protect
Stay CIF form (352 × 288 pixel) image pixel received, on strange row and odd column position, insert image pixel simultaneously, from
And revert to the view data of 720 × 576 forms, particularly as follows: frame synchronization retrieval is set and rises two states of sampling processing；System
After powering up, initially enter frame synchronization retrieval state, the most effective in retrieval of each clock cycle frame synchronizing signal, otherwise continue to stay
Frame synchronization retrieval state, the most then enter and rise sampling processing state；When liter sampling processing state, it is respectively provided with view data row, column meter
Number device, row, column count maximum is respectively 720,576, and in each clock cycle, as judged, row count value is as even row, column count
When value is for even column, the image pixel value of output present clock period, when column counter value is odd column, export adjacent 2 idols of current line
Row image pixel value is added the image pixel value obtained after being averaged；Simultaneously need to the institute of the adjacent 2 row idol row after caching interpolation
There is image pixel value；Judge when row count value is strange row, by 2 row that this strange row that image pixel value is caching of row output is adjacent
The image pixel value of even row respective column is added the image pixel value obtained after being averaged；At the end of counting statistics to a frame video
Return frame synchronization retrieval state；So conditional jump, moves in circles.
After receiving terminal system powers up, first have to configure video coding chip ADV7393；ADV7393 is a low-power consumption, height
The video encoder of quality.It has 3 high-quality 10 digital video DAC, can be by the mould of CVBS, S-Video, YPrPb/RGB
Intend video signal with high definition (HD) standard output.Rise 720 × 576 format picture data after sampling by ADV7393 number
After mould conversion, output is to video terminal.
Control flow is as shown in Figure 7.
The said method that the present embodiment provides, for the real-time video transmission under complicated wireless channel, passes through compression of images
Add RS coding and add the Joint Source/channel Coding Design of intertexture, it is possible to successfully solve image transmission problem under interference channel, thus
Improve the quality of service of transmission of video.
The program uses forward error correction coding to carry out non-uniform FDTD grids, considers that increasing forward error correction coding takies additionally simultaneously
The channel width impact on information source transmission code rate, using unified Joint Source/channel Coding Design statistics rate-distortion model as constraint,
Optimized distribution signal source and channel code check, thus improve the quality of service of transmission of video.Meanwhile, program interleaving technology introduces connection
Compile in collaboration with decoding, custom coding frame structure, will originally belong to the channels with memory of burst error by Design of Signal, be transformed near
Like the random memoryless channel of independent error, apply anti-error code demand on the full border of image delivering system fullness in the epigastrium and abdomen, particularly promote
The error burst ability that anti-multipath effect attracts, is effectively increased the error correcting capability of associating coding/decoding system.
Embodiment two
Corresponding to said method, the present embodiment additionally provides a kind of Joint Source Channel coding/decoding system, as Fig. 8 provides
System architecture schematic diagram, specifically includes a lower module:
Transmitting terminal FPGA 801, is used for carrying out pre-processing image data；
Transmitting terminal DSP 802, for carrying out compression of images, RS coding and the Joint Source/channel Coding Design interweaved；
Receiving terminal DSP 803, is used for being deinterleaved, RS decoding and image decompressor operation；
Receiving terminal FPGA 804, is used for carrying out view data reduction and output.
Wherein, described transmitting terminal FPGA 801 includes:
First detector unit, for monitoring the frame synchronizing signal in view data, determines that video initiates；
Concrete, the first detector unit receives 720 × 576 pixel image datas from video AD conversion chip, monitoring
Frame synchronizing signal, determines that a frame video initiates.
Down-sampled unit, is used for carrying out down-sampled；Specifically can carry out 2 times of down-sampled process.
First formatting unit, is used for carrying out format change process, is wherein transformed to standard CIF form (Common
Intermediate Format, 352 × 288 pixels) view data, by EMIF (External Memory Interface,
External memory interface) export transmitting terminal DSP.
Corresponding transmitting terminal, described receiving terminal FPGA includes:
Second detector unit, for monitoring the frame synchronizing signal in view data, determines that video initiates；
Rise sampling unit, be used for carrying out a liter sampling；
Second formatting unit, is used for carrying out format change process.
Specifically, receiving terminal FPGA receives the decompression of DSP output and recovers view data, and the second detector unit monitoring frame is same
Step signal, after determining that a frame video is initial, liter sampling unit carries out 2 times and rises sampling processing, and the second formatting unit is by a liter sampling
The data processed revert to 720 × 576 format picture data and export to DA conversion chip.
Meanwhile, described transmitting terminal DSP 802 specifically may include that
Image compression unit, for being compressed processing to the view data of transmitting terminal FPGA output；Data transfer rate after compression
457kbps can be chosen as；
RS coding unit, is used for carrying out RS chnnel coding；For the real-time video transmission under complicated wireless channel, use
FEC (Forward Error Correction, forward error correction coding) carries out non-uniform FDTD grids, considers to increase FEC coding simultaneously
Take the impact on information source transmission code rate of the extra channel bandwidth, make with unified Joint Source/channel Coding Design statistics rate-distortion model
For retraining, optimized distribution signal source and channel code check, thus improve the quality of service of transmission of video.
Wherein chnnel coding can be chosen as RS (255,239) or RS (255,223)；
Interleave unit, processes for block interleaving.Wherein interleave depth is optional.Can be with custom coding frame in interleaving treatment
Channels with memory are converted to random memoryless channel by Design of Signal by structure.
Corresponding with transmitting terminal DSP 802, described transmitting terminal DSP 803 specifically may include that
Deinterleave unit, for being deinterleaved processing according to the interleave depth of interleave unit；
RS decoding unit, for carrying out channel decoding according to the RS channel of RS coding unit, wherein RS (255,239) or
RS (255,223) is optional
Image decompressor unit, is used for carrying out image decompressor process, recovers view data.
The said system that the present embodiment provides, for the real-time video transmission under complicated wireless channel, passes through compression of images
Add RS coding and add the Joint Source/channel Coding Design of intertexture, it is possible to successfully solve image transmission problem under interference channel, thus
Improve the quality of service of transmission of video.
This system uses the hardware structure of FPGA+DSP, and FPGA is responsible for the pretreatment of original video data, and DSP is responsible for pre-place
The Joint Source Channel encoding and decoding of the video data after reason.This system has and processes structure flexibly, the application to different demands
There is stronger adaptation ability, be especially suitable for quick video compress and process task, for how design processes software and hardware
Relation provides a preferable solution.
In this specification, each embodiment uses the mode gone forward one by one to describe, and what each embodiment stressed is and other
The difference of embodiment.The present embodiment is the system embodiment of embodiment of the method one, two and three correspondence, wherein modules merit
The implementation of energy may refer to said method embodiment, and its similar part cross-reference repeats no more.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention.
Multiple amendment to these embodiments will be apparent from for those skilled in the art, as defined herein
General Principle can realize without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein and features of novelty phase one
The widest scope caused.
The present invention applies specific embodiment principle and the embodiment of the present invention are set forth, above example
Explanation be only intended to help to understand method and the core concept thereof of the present invention；Simultaneously for one of ordinary skill in the art,
According to the thought of the present invention, the most all will change, in sum, in this specification
Hold and should not be construed as limitation of the present invention.
Claims (9)
1. a Joint Source Channel decoding method, it is characterised in that including:
Transmitting terminal FPGA carries out pre-processing image data；
Transmitting terminal DSP carries out compression of images, RS coding and the Joint Source/channel Coding Design interweaved；
Receiving terminal DSP is deinterleaved, RS decodes and image decompressor operation；
Receiving terminal FPGA carries out view data reduction and output.
2. want the method described in 1 according to right, it is characterised in that described transmitting terminal FPGA carries out pre-processing image data, including:
Frame synchronizing signal in monitoring view data, determines that video initiates；
Carry out down-sampled and format change process.
3. want the method described in 2 according to right, it is characterised in that described receiving terminal FPGA carries out view data reduction and output,
Including:
The frame synchronizing signal of monitoring view data, determines that video initiates；
Carry out liter sampling and format change processes.
4. want the method described in 1 according to right, it is characterised in that the Joint Source/channel Coding Design being interleaved, including:
Channels with memory are converted to random memoryless channel by Design of Signal by definition coded frame structure.
5. a Joint Source Channel coding/decoding system, it is characterised in that including:
Transmitting terminal FPGA, is used for carrying out pre-processing image data；
Transmitting terminal DSP, for carrying out compression of images, RS coding and the Joint Source/channel Coding Design interweaved；
Receiving terminal DSP, is used for being deinterleaved, RS decoding and image decompressor operation；
Receiving terminal FPGA, is used for carrying out view data reduction and output.
6. want the system described in 5 according to right, it is characterised in that described transmitting terminal FPGA includes:
First detector unit, for monitoring the frame synchronizing signal in view data, determines that video initiates；
Down-sampled unit, is used for carrying out down-sampled；
First formatting unit, is used for carrying out format change process.
7. want the system described in 6 according to right, it is characterised in that described receiving terminal FPGA includes: the second detector unit, is used for supervising
Frame synchronizing signal in altimetric image data, determines that video initiates；Rise sampling unit, be used for carrying out a liter sampling；
Second formatting unit, is used for carrying out format change process.
8. want the system described in 5 according to right, it is characterised in that described transmitting terminal DSP includes: image compression unit, for right
The view data of transmitting terminal FPGA output is compressed processing；RS coding unit, is used for carrying out RS chnnel coding；
Interleave unit, processes for block interleaving.
9. want the system described in 8 according to right, it is characterised in that described transmitting terminal DSP includes: deinterleave unit, for basis
The interleave depth of interleave unit is deinterleaved processing；
RS decoding unit, for carrying out channel decoding according to the RS channel of RS coding unit；
Image decompressor unit, is used for carrying out image decompressor process, recovers view data.
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