CN206657816U - Back-illuminated type high-speed photodiode reception chip - Google Patents

Abstract

The utility model proposes a kind of back-illuminated type high-speed photodiode reception chip, including：Epitaxial layer, including p-type table top, N-type table top, InP substrate；P-type table top includes indium GaAs absorbed layer, gallium arsenide phosphide indium graded bedding, speculum surface layer, indium phosphide top layer, indium gaas contact layer；N-type table top includes indium phosphide cushion；Wherein, indium phosphide cushion, indium GaAs absorbed layer, gallium arsenide phosphide indium graded bedding, speculum surface layer, indium phosphide top layer, indium gaas contact layer are grown on InP substrate successively；Integral micro-lens, are arranged at the side of InP substrate, and integral micro-lens and indium phosphide cushion are in the not homonymy of InP substrate.In the case that the utility model can keep constant ensuring chip diffusion source region area, the light absorbs area of extended chip, solve the problems, such as that the small caused coupling efficiency of chip diffusion source region area is low, and adding speculum surface layer can be improved the quantum efficiency of chip.

Description

Back-illuminated type high-speed photodiode reception chip

Technical field

Chip technology field is the utility model is related to, is received in particular to a kind of back-illuminated type high-speed photodiode Chip.

Background technology

With fiber entering household HTTP popularization and the construction of 5G base stations, to the demand of high-speed photodiode light-receiving chip Also it is increasingly urgent.10G high-speed photodiodes reception chip has become the main product of present technology application at present, 25G, 100G, 400G photodiode reception chip demand are also at the ascent stage of high speed development.

The speed of photodiode reception chip, which depends primarily on two aspects, to be influenceed：First, floated by chip photo-generated carrier Move the transition time that speed is determined, such as formulaIt is shown, wherein υ be photo-generated carrier drift velocity, base It is 6 × 106cm/s of definite value in sheet, the length of InGaAs absorbed layers of the L designed by chip epitaxial structure, usually 1 μm to 3 μ m.The key factor that another part influences chip rate is the RC time constants determined by chip capacity, such as formulaShown, wherein R is chip-resistance, is substantially also that definite value 60 Ω, C are chip junction capacity.So in order to Chip rate is improved as far as possible, must just reduce InGaAs absorbed layers in chip capacity and chip epitaxial structure as far as possible Length, and according to the calculation formula of chip capacityUnderstand in the case where chip material dielectric coefficient ε is certain, chip Electric capacity depends primarily on the diffusion source region area of chip and the length of chip I nGaAs absorbed layers.The length of InGaAs absorbed layers is got over Long, electric capacity can be smaller, but the transition time of chip can be longer, f_3dB-TTIt can become big, so, reception chip speed is generally improved at present The most direct method of rate is to need to spread source region area by reducing chip, to realize reduction chip capacity, improves chip rate Purpose.

Calculated according to theory, in order to reach more than 20GHz speed, it usually needs chip is spread to the diameter control of source region To less than 20 μm, to reduce chip capacity, while need to control the InGaAs absorbed layers length of chip at 1 μm to 1.5 μm, with Shorten the carrier transit time of chip.But this also simultaneously results in both sides defect：(1) too small chip spreads source region Area, by the serious coupling efficiency influenceed during chip use with input optical fibre, when chip source region diameter is less than 20 μm, Coupling efficiency during chip use will decline about 50%；(2) short chip I nGaAs absorbed layers length will cause chip light Raw carrier quantum efficiency η is reduced, and is to absorb according to calculation formula η=1-exp (- α L) of chip quantum efficiency, wherein α Number, determined by the material and reception wavelength of chip I nGaAs absorbed layers, essentially definite value, therefore InGaAs absorbed layer length is smaller, Photoproduction quantum efficiency will be lower, and according to calculating, when InGaAs absorbed layers length is less than 1.5 μm, InGaAs materials are directed to The photo-generated carrier quantum efficiency of 1310nm and 1550nm wavelength will be less than 70%.

The light-receiving chip generally use chip structure for just entering light mode as shown in Figure 1 in the prior art, InP substrate 102 ', InP cushion 104 ', InGaAs absorbed layers 106 ', InP top layers 108 ', passivating film 110 ', anti-reflection film 112 ', spread source Area 114 ', chip positive electrode 116 ', chip negative electrode 118 ', incident light generally enter core shooting from chip diffusion source region 114 ' upper surface Piece, but in order that chip rate is higher than 20GHz, the diameter D of the diffusion source region 114 ' are commonly designed both less than 20 μm, and chip The length L of InGaAs absorbed layers 106 ' is typically designed to 1 μm to 1.5 μm, so, the high-speed chip of usual this structure is generally deposited In the applied defect such as coupling efficiency is low, quantum efficiency is low.

Utility model content

The utility model is intended at least solve one of technical problem present in prior art or correlation technique.

Therefore, a purpose of the present utility model is to propose a kind of back-illuminated type high-speed photodiode reception chip.

In view of this, according to a purpose of the present utility model, it is proposed that a kind of back-illuminated type high-speed photodiode receives Chip, including：Epitaxial layer, including p-type table top, N-type table top, InP substrate；P-type table top includes indium GaAs absorbed layer, phosphorus Gallium indium arsenide graded bedding, speculum surface layer, indium phosphide top layer, indium gaas contact layer；N-type table top includes indium phosphide cushion； Wherein, indium phosphide cushion, indium GaAs absorbed layer, gallium arsenide phosphide indium graded bedding, speculum are grown on InP substrate successively Surface layer, indium phosphide top layer, indium gaas contact layer；Integral micro-lens, it is arranged at the side of InP substrate, and integral micro-lens With indium phosphide cushion InP substrate not homonymy.

Back-illuminated type high-speed photodiode reception chip provided by the utility model, by designing p-type table top, N-type table top The distributed constant of chip is reduced, so as to reach the purpose of lifting chip bandwidth, by using in chip back integral micro-lens, In the case of ensuring that chip diffusion source region area keeps constant, the light absorbs area of extended chip, solves existing high speed light-receiving The problem of coupling efficiency caused by chip diffusion source region area existing for chip is small is low.Section length is absorbed in the original design of chip In the case of keeping constant, the speculum being made up of p-type AlGaAs multi-quantum pit structures is added in the design of chip epitaxial layer Surface layer, designed by special quantum well structure, epitaxial layer is reached more than 99% to the reflectivity of incident light, so that incident When light incides this layer, approximation total reflection is produced, is carried so as to absorb generation photoproduction again in the progress of chip indium GaAs absorbed layer Stream, equivalent in the case where not changing original indium GaAs absorber thickness, nearly one has been expanded by the absorption length of chip Times, so that the quantum efficiency of chip is improved.Indium phosphide top layer is added in the design of chip epitaxial layer, passes through indium phosphide top layer Contacted with chip positive electrode, Ohmic contact is formed by rapid alloying technique, substantially reduces the contact resistance of chip electrode.Anti- Increase gallium arsenide phosphide indium graded bedding between specular layer and indium GaAs absorbed layer is penetrated, chip photo-generated carrier can be obviously reduced and exist The carrier accumulation time between indium GaAs absorbed layer and speculum surface layer caused by energy gap difference, so as to reduce core The transmission time of piece photo-generated carrier.

According to above-mentioned back-illuminated type high-speed photodiode reception chip of the present utility model, there can also be following technology special Sign：

In the above-mentioned technical solutions, it is preferable that also include：Anti-reflection film, be arranged at integral micro-lens and InP substrate it Between；Wherein, the thickness of anti-reflection film isExtremely

In the technical scheme, anti-reflection film, it is arranged between integral micro-lens and InP substrate, and the thickness of anti-reflection film ForExtremelyAnti-reflection effect, refractive index 1.94 can be played to the incident light of 1310nm and 1550nm wavelength To 1.98.

In any of the above-described technical scheme, it is preferable that also include：Chip positive electrode, it is arranged on p-type table top, with indium arsenic Change gallium contact layer to be connected；Chip negative electrode, it is arranged on N-type table top, is connected with indium phosphide cushion.

In the technical scheme, chip positive electrode is arranged on p-type table top, is connected with indium gaas contact layer, chip Negative electrode is arranged on N-type table top, is connected with indium phosphide cushion, chip positive electrode generally use Ti/Pt/Au membrane system structures Into wherein Ti thicknessExtremelyPt thicknessExtremelyAu thickness is more thanChip negative electrode leads to Formed frequently with Au, thickness requirement is more than

In any of the above-described technical scheme, it is preferable that also include：Protect deielectric-coating, be arranged at p-type table top side wall and The side wall of N-type table top, and between the side wall and the side wall and chip positive electrode of N-type table top positioned at p-type table top；Wherein, protect The thickness of deielectric-coating is more than 4 μm.

In the technical scheme, in the protection deielectric-coating that chip p-type table top and N-type mesa side walls make, in order to reduce core Chip capacitor, the deielectric-coating generally use polyimides (PI) or the protection of benzocyclobutene (BCB) glued membrane, polyimides (PI) and benzene And cyclobutane (BCB) has relatively low material dielectric constant, chip capacity can be reduced to greatest extent, and film thickness requirement is big In 4 μm.

In any of the above-described technical scheme, it is preferable that also include：Source region is spread, spreads the range of scatter of source region by indium arsenic Change gallium contact layer to indium GaAs absorbed layer；Wherein, a diameter of 15 μm to 25 μm of source region are spread.Preferably, diffusion source region exists Diffusion depth on indium GaAs absorbed layer is 0.1 μm ± 0.05 μm.

In the technical scheme, the diffusion depth requirement of diffusion source region is formed using Zn diffusions can enter chip indium arsenic Gallium absorbed layer, and it is 0.1 μm ± 0.05 μm to enter depth, between the diametric requirements of the diffusion source region are 15 μm to 25 μm, and then Chip junction capacity is reduced, diffused surface concentration requirement is more than 3 × 10¹⁸/cm^-3。

In any of the above-described technical scheme, it is preferable that the center of circle of integral micro-lens is centrally located at same with diffusion source region Vertical centred position.Preferably, the radius of integral micro-lens is 40 μm to 80 μm.

In the technical scheme, it is micro- that the integrated chip that radius is 40 μm to 80 μm is integrated on chip InP substrate Mirror, the integral micro-lens can use ICP-RIE etchings or the method for lithographic wet corrosion to be made, and the center of the integral micro-lens Point needs to spread source region central point on same vertical center line with chip, and error is less than ± 5 μm.

In the above-mentioned technical solutions, it is preferable that the height of p-type table top is 3.9 μm to 8.4 μm；And the height of N-type table top For 0.5 μm to 4 μm.Preferably, the diameter of N-type table top is at least bigger 10 μm than the diameter of p-type table top；And the diameter of p-type table top Diameter than spreading source region is at least big 5 μm.

In the technical scheme, p-type table surface height is more than 3.9 μm and less than 8.4 μm.The diameter of N platforms is bigger than P platforms diameter extremely It is few 10 μm, 0.5 μm to 4 μm of N platforms height, it is desirable to which the diameter of p-type table top is bigger at least 5 μm than chip diffusion source region diameter.

Additional aspect and advantage of the present utility model will become obvious in following description section, or new by this practicality The practice of type is recognized.

Brief description of the drawings

Of the present utility model above-mentioned and/or additional aspect and advantage will in the description from combination accompanying drawings below to embodiment Become obvious and be readily appreciated that, wherein：

Fig. 1 shows the chip structure schematic diagram for just entering light mode in the prior art；

Fig. 2 shows that the structure of the back-illuminated type high-speed photodiode reception chip of one embodiment of the present utility model is cutd open Depending on schematic diagram；

Fig. 3 is showing the structure of the back-illuminated type high-speed photodiode reception chip of one embodiment of the present utility model just Depending on schematic diagram.

Wherein, the corresponding relation in Fig. 1 between reference and component names is：

102 ' InP substrates, 104 ' InP cushions, 106 ' InGaAs absorbed layers, 108 ' InP top layers, 110 ' passivating films, 112 ' anti-reflection films, 114 ' diffusion source regions, 116 ' chip positive electrodes, 118 ' chip negative electrodes；

Wherein, the corresponding relation in Fig. 2 and Fig. 3 between reference and component names is：

102InP substrates, 104InP cushions, 106InGaAs absorbed layers, 108InP top layers, 110 passivating films, 112 is anti-reflection Film, 114 diffusion source regions, 116 chip positive electrodes, 118 chip negative electrodes, 120 protection deielectric-coating, 122 integral micro-lens, 124InGaAsP graded bedding, 126 speculum surface layers, 128InGaAs contact layers.

Embodiment

In order to be more clearly understood that above-mentioned purpose of the present utility model, feature and advantage, below in conjunction with the accompanying drawings and tool The utility model is further described in detail body embodiment.It should be noted that in the case where not conflicting, this Shen The feature in embodiment and embodiment please can be mutually combined.

Many details are elaborated in the following description in order to fully understand the utility model, still, this practicality New to be different from other modes described here using other to implement, therefore, the scope of protection of the utility model is simultaneously It is not limited to the limitation of following public specific embodiment.

The utility model proposes a kind of back-illuminated type high-speed photodiode reception chip, Fig. 2 shows of the present utility model The structure schematic cross-sectional view of the back-illuminated type high-speed photodiode reception chip of one embodiment, Fig. 3 show the utility model One embodiment back-illuminated type high-speed photodiode reception chip structure schematic elevation view, retouched referring to Fig. 2 and Fig. 3 State according to the back-illuminated type high-speed photodiode reception chip described in the utility model some embodiments.

In one embodiment of the present utility model, using the method in chip back integral micro-lens 122, core is being ensured In the case that piece diffusion source region 114 area keeps constant, the light absorbs area of extended chip.The feature of integral micro-lens 122 exists In：

(1) integral micro-lens 122 are made as directly in chip back InP substrate 102 using Photoresist reflow adding ICP-RIE is etched, or the method for lithographic wet corrosion makes；

(2) the radius R of integral micro-lens 122 is 40 μm to 80 μm, so may insure chip back diameter 80 μm to 160 Incident light in μm region, the InGaAs absorbed layers 106 of chip can be converged to, so as to make to expand not changing chip In the case of the area for dissipating source region 114, the incident light beam strikes diameter range that receives of chip is set to have increased to 80 μm to 160 μm, The coupling efficiency of chip is set to have brought up at least more than 95%；

(3) center of circle O ' of integral micro-lens 122, same vertical centre position is in the chip diffusion central point O of source region 114 Put, relative horizontal position difference is less than ± 5 μm, solves chip existing for existing high speed light-receiving chip and spreads the area of source region 114 The problem of coupling efficiency caused by small is low.

In another embodiment of the present utility model, constant situation is kept in the length L of chip I nGaAs absorbed layers 106 Under, the speculum surface layer 126 being made up of p-type AlGaAs multi-quantum pit structures is added in the design of chip epitaxial structure.Pass through Special quantum well structure design, makes speculum surface layer 126 reach more than 99% to the reflectivity of incident light, so that incident light When inciding speculum surface layer 126, approximate total reflection is produced, so as to be absorbed production again in chip I nGaAs absorbed layers 106 Raw photo-generated carrier, thus equivalent in the case where not changing the thickness L of InGaAs absorbed layers 106, the absorption of chip is grown Degree has been expanded by about one time, so that the quantum efficiency of chip is improved.The structural design features of speculum surface layer 126 are：

(1) material of this layer is by Al_0.12Ga_0.88As/Al_0.9Ga_0.1The multi-quantum pit structure of As materials composition is formed；

(2) structure uses 20/30 couple of Al_0.12Ga_0.88As/Al_0.9Ga_0.1As quantum well constitutions, in each pair quantum well structure Al_0.12Ga_0.88As thickness is 40nm to 70nm, Al_0.9Ga_0.1As thickness is 50nm to 80nm；

(3) doping concentration is (1~5) × 10¹⁸/cm^-3；

(4) the SQW speculum surface layer 126 is between epitaxial wafer InP top layers 108 and InGaAsP graded beddings 124.

In further embodiment of the present utility model, in order to realize at least more than 20GHz light-receiving speed, the chip Epitaxial structure is employed such as the structure design in table 1：

Table 1

In order to improve the receiving velocity of chip in the design of chip epitaxial structure, InGaAs contact layers 128 are added, are passed through InGaAs contact layers 128 contact with chip positive electrode 116, form Ohmic contact by rapid alloying technique, can substantially reduce The contact resistance of chip electrode.In addition, the utility model by speculum surface layer 126 and chip I nGaAs absorbed layers 106 it Between increase InGaAsP graded bedding 124, chip photo-generated carrier can be obviously reduced in InGaAs absorbed layers 106 and speculum The carrier accumulation time between surface layer 126 caused by energy gap difference, so as to reduce the transmission of chip photo-generated carrier Time.

In another embodiment of the present utility model, in chip structure design, in order to reduce posting for chip as far as possible Raw parameter effects and chip capacity, the utility model employs mesa structure chip design as shown in Figure 2, wherein main sets Meter is characterised by：

(1) two concentric boss are formed in chip surface using the technique of lithographic wet corrosion or dry etching, one is By InGaAs contact layers 128, InP top layers 108, p-type Al_0.12Ga_0.88As/Al_0.9Ga_0.1As speculums surface layer 126, InGaAsP are gradually The p-type table top that change layer 124 and InGaAs absorbed layers 106 are formed, p-type table top needs and chip diffusion source region 114 are concentric, and The diameter D ' of p-type table top needs bigger at least 5 μm than the diameter D of chip diffusion source region 114.Another table top is by InP cushions The 104 N-type table tops formed.The purpose of design of the two table tops is primarily to reduce the distributed constant of chip, so as to reach Lift the purpose of chip bandwidth；

(2) in order to reduce chip junction capacity, chip rate is made to be more than 20GHz, the diameter D of chip diffusion source region 114 needs Less than 30 μm；

(3) the sidewall protecting film layer 120 of chip p-type table top and N-type table top is using polyimides (PI) or benzocyclobutene (BCB) glued membrane is protected, and polyimides (PI) and benzocyclobutene (BCB) have relatively low material dielectric constant, can be with maximum limit The reduction chip capacity of degree.

(4) chip p-type chip positive electrode 116 is made using Ti/Pt/Au metal material membrane system, wherein Au thickness degree is big In 1 μm, chip N-type chip negative electrode 118 is made using Au, wherein Au thickness degree is more than 1 μm.

In another embodiment of the present utility model, as shown in Fig. 2 the utility model is related to chip product mainly by such as Lower part forms：

(1) the high-speed chip epitaxial wafer of InGaAs/InP particular designs is used, the structure of the epitaxial wafer is included in 350 μ m-thicks Mix Fe³⁺In InP substrate 102, deposit growth doping concentration successively using MOCVD and be more than 1 × 10¹⁷/cm^-3, 0.5 μm to 4 of thickness μm chip I nP cushions 104；Doping concentration is less than 1 × 10¹⁵/cm^-3, thickness is 1 μm to 2 μm of chip I nGaAs absorbed layers 106；Doping concentration is less than 5 × 10¹⁶/cm^-3, thickness is 0.02 μm to 0.1 μm of chip I nGaAsP graded bedding 124；Doping Concentration (1~5) × 10¹⁸/cm^-3, thickness Al_0.12Ga_0.88As：(40~70) nm × 20, Al_0.9Ga_0.1As：(50~80) nm × 30 chip p-type Al_0.12Ga_0.88As/Al_0.9Ga_0.1As speculums surface layer 126；Doping concentration is less than 5 × 10¹⁶/cm^-3, thickness is 0.5 μm to 2 μm of InP top layers 108；Doping concentration is less than 5 × 10¹⁶/cm^-3, thickness is 0.1 μm to 0.5 μm of chip I nGaAs Contact layer 128；

(2) the integrated chip lenticule 122 that radius R is 40 μm to 80 μm is integrated on chip I nP substrates 102, this is integrated Lenticule 122 can use ICP-RIE etchings or the method for lithographic wet corrosion to be made, and the central point O ' of the lens needs and core For piece diffusion region central point O on same vertical center line, error is less than ± 5 μm；

(3) the chip bench-type structure made using the method for ICP-RIE etchings or lithographic wet corrosion, the bench-type structure bag Include by InGaAs contact layers 128, InP top layers 108, p-type Al_0.12Ga_0.88As/Al_0.9Ga_0.1As speculums surface layer 126, InGaAsP Chip p-type table top that graded bedding 124 and InGaAs absorbed layers 106 are formed and the chip N-type platform being made up of InP cushions 104 Face.It is required that the diameter D ' of p-type table top is needed than at least 5 μm greatly of chip source region diameter D, the requirement of p-type table surface height is more than 3.9 μm, Less than 8.4 μm, the diameter D " of N platforms needs, N platform height 0.5 μm to 4 μm bigger at least 10 μm than P platform diameters D '.Chip positive electrode 116 contact positions are located on chip p-type table top, are connected with chip I nGaAs contact layers 128, and the position of chip negative electrode 118 is located at On chip N-type table top, it is connected with chip I nP cushions 104；

(4) deielectric-coating 120 is protected in the table top that chip p-type table top and N-type mesa side walls make using photoetching coating processes. In order to reduce chip capacity, the generally use polyimides (PI) of protection deielectric-coating 120 or benzocyclobutene (BCB) glued membrane, glue Film thickness requirement is more than 4 μm；

(5) formed chip diffusion source region 114 is spread using Zn, the diffusion depth requirement of the diffusion source region 114 can enter Enter chip I nGaAs absorbed layers 116, and it is 0.1 ± 0.05 μm to enter depth, 15 μm of the diameter D requirements of the diffusion source region 114<D< 25 μm, diffused surface concentration requirement is more than 3 × 10¹⁸/cm^-3；

(6) the chip positive electrode 116 and chip negative electrode made using evaporation or sputtering technology and lithographic wet technique 118, the generally use Ti/Pt/Au membrane systems of chip positive electrode 116 are formed, wherein Ti thicknessExtremelyPt thickness ExtremelyAu thickness is more thanThe generally use Au of chip negative electrode 118 is formed, and thickness requirement is more than

(7) the chip anti-reflection film 112 made using PEVCD deposit growths, can be to the incidence of 1310nm and 1550nm wavelength Light plays anti-reflection effect, it is desirable to which the thickness of deposit anti-reflection film 112 isExtremelyRefractive index is 1.94~1.98.

In the description of this specification, the description of term " one embodiment ", " some embodiments ", " specific embodiment " etc. Mean that combining specific features, structure, material or feature that the embodiment or example describe is contained in of the present utility model at least one In individual embodiment or example.In this manual, identical embodiment is not necessarily referring to the schematic representation of above-mentioned term Or example.Moreover, specific features, structure, material or the feature of description can be in any one or more embodiments or example In combine in an appropriate manner.

Preferred embodiment of the present utility model is the foregoing is only, is not limited to the utility model, for this For the technical staff in field, the utility model can have various modifications and variations.It is all in the spirit and principles of the utility model Within, any modification, equivalent substitution and improvements made etc., it should be included within the scope of protection of the utility model.

Claims (10)

1. A kind of 1. back-illuminated type high-speed photodiode reception chip, it is characterised in that including：

   Epitaxial layer, including p-type table top, N-type table top, InP substrate；

   The p-type table top includes indium GaAs absorbed layer, gallium arsenide phosphide indium graded bedding, speculum surface layer, indium phosphide top layer, indium arsenic Change gallium contact layer；

   The N-type table top includes indium phosphide cushion；

   Wherein, the indium phosphide cushion, the indium GaAs absorbed layer, the phosphorus arsenic are grown on the InP substrate successively Change gallium indium graded bedding, the speculum surface layer, the indium phosphide top layer, the indium gaas contact layer；

   Integral micro-lens, it is arranged at the side of the InP substrate, and the integral micro-lens and the indium phosphide cushion In the not homonymy of the InP substrate.
2. 2. back-illuminated type high-speed photodiode reception chip according to claim 1, it is characterised in that also include：

   Anti-reflection film, it is arranged between the integral micro-lens and the InP substrate；

   Wherein, the thickness of the anti-reflection film isExtremely
3. 3. back-illuminated type high-speed photodiode reception chip according to claim 1, it is characterised in that also include：

   Chip positive electrode, it is arranged on the p-type table top, is connected with the indium gaas contact layer；

   Chip negative electrode, it is arranged on the N-type table top, is connected with the indium phosphide cushion.
4. 4. back-illuminated type high-speed photodiode reception chip according to claim 1, it is characterised in that also include：

   Deielectric-coating is protected, is arranged at the side wall of the p-type table top and the side wall of the N-type table top, and be located at the p-type table top Side wall and the side wall of the N-type table top and the chip positive electrode between；

   Wherein, the thickness of the protection deielectric-coating is more than 4 μm.
5. 5. back-illuminated type high-speed photodiode reception chip according to claim 1, it is characterised in that also include：

   Source region is spread, the range of scatter of the diffusion source region is by the indium gaas contact layer to the indium GaAs absorbed layer；

   Wherein, a diameter of 15 μm to 25 μm of the diffusion source region.
6. 6. back-illuminated type high-speed photodiode reception chip according to claim 5, it is characterised in that

   Diffusion depth of the diffusion source region on the indium GaAs absorbed layer is 0.1 μm ± 0.05 μm.
7. 7. back-illuminated type high-speed photodiode reception chip according to claim 5, it is characterised in that

   The center of circle of the integral micro-lens is centrally located at same vertical centred position with the diffusion source region.
8. 8. back-illuminated type high-speed photodiode reception chip according to any one of claim 1 to 6, it is characterised in that

   The radius of the integral micro-lens is 40 μm to 80 μm.
9. 9. back-illuminated type high-speed photodiode reception chip according to any one of claim 1 to 6, it is characterised in that

   The height of the p-type table top is 3.9 μm to 8.4 μm；

   The height of the N-type table top is 0.5 μm to 4 μm.
10. 10. back-illuminated type high-speed photodiode reception chip according to claim 5, it is characterised in that

    The diameter of the N-type table top is at least bigger 10 μm than the diameter of the p-type table top；And

    The diameter of the p-type table top is at least bigger 5 μm than the diameter of the diffusion source region.