CN206657641U - Image element circuit and display device - Google Patents
Image element circuit and display device Download PDFInfo
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- CN206657641U CN206657641U CN201720282744.6U CN201720282744U CN206657641U CN 206657641 U CN206657641 U CN 206657641U CN 201720282744 U CN201720282744 U CN 201720282744U CN 206657641 U CN206657641 U CN 206657641U
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Abstract
The utility model discloses a kind of image element circuit and display device.The image element circuit includes：First control unit, driver element, memory cell, the second control unit and luminescence unit；First control unit is connected to first node and data wire；The driver element is connected to the first node, section point and the first power supply；The memory cell is connected to the first node and the section point；Second control unit is connected to the section point and data wire；The luminescence unit is connected to the section point and second source.There is electric current process in luminescence unit when 0 GTG is shown by setting the second control unit to avoid in the utility model, lighted so as to avoid luminescence unit when 0 GTG is shown.
Description
Technical field
Display technology field is the utility model is related to, more particularly to a kind of image element circuit and display device.
Background technology
At present, Organic Light Emitting Diode (Organic Light-Emitting Diode, abbreviation：OLED) image element circuit
In, threshold voltage vt h can be loaded on data wire when 0 GTG is shown, the driving tube in OLED pixel circuit can be made in theory
TFT ends, so that not having electric current process in OLED.
But due to TFT manufacturing process the problem of, the Vth meetings in the case of illumination or electrical pressure (stress)
Drift about.If negative drift occurs in Vth, the voltage loaded on data wire can be more than Vth so that have electric current warp in luminous tube OLED
Cross, so as to cause OLED to be lighted when 0 GTG is shown.
Utility model content
The utility model provides a kind of image element circuit and display device, for avoiding luminescence unit from being sent out when 0 GTG is shown
Light.
To achieve the above object, the utility model provides a kind of image element circuit, including：First control unit, driving are single
Member, memory cell, the second control unit and luminescence unit；
First control unit is connected to first node and data wire；
The driver element is connected to the first node, section point and the first power supply；
The memory cell is connected to the first node and the section point；
Second control unit is connected to the section point and data wire；
The luminescence unit is connected to the section point and second source.
Alternatively, the driver element includes first switch pipe；
The control pole of the first switch pipe is connected to the first node, and the first pole of the first switch pipe is connected to
First power supply, the second pole of the first switch pipe are connected to the section point.
Alternatively, first control unit includes second switch pipe；
The control pole of the second switch pipe is connected to the first grid line, and the first pole of the second switch pipe is connected to described
Data wire, the second pole of the second switch pipe are connected to the first node.
Alternatively, the memory cell includes electric capacity；
The first end of the electric capacity is connected to the first node, and the second end of the electric capacity is connected to section point.
Alternatively, second control unit includes the 4th switching tube；
The control pole of 4th switching tube is connected to scan line, and the first pole of the 4th switching tube is connected to the number
According to line, the second pole of the 4th switching tube is connected to the section point.
Alternatively, in addition to reading unit；
The reading unit is connected to section point and sense wire.
Alternatively, the reading unit includes the 3rd switching tube；
The control pole of 3rd switching tube is connected to the second grid line, and the first pole of the 3rd switching tube is connected to described
Section point, the second pole of the 3rd switching tube are connected to the sense wire.
Alternatively, the luminescent device includes light emitting diode；
First pole of the light emitting diode is connected to the section point, and the second pole of the light emitting diode is connected to
The second source.
To achieve the above object, the utility model provides a kind of display device, including above-mentioned image element circuit.
The utility model has the advantages that：
In image element circuit provided by the utility model, the first control unit is connected to first node and data wire, and driving is single
Member is connected to first node, section point and the first power supply, and memory cell is connected to first node and the second section.Second control is single
Member is connected to section point and data wire, and luminescence unit is connected to section point and second source, by setting in the utility model
Putting the second control unit and avoiding has electric current process when 0 GTG is shown in luminescence unit, so as to avoid luminescence unit in 0 ash
Rank lights when showing.
Brief description of the drawings
Fig. 1 is a kind of structural representation for image element circuit that the utility model embodiment one provides；
Fig. 2 is a kind of structural representation for image element circuit that the utility model embodiment two provides；
Fig. 3 is the signal timing diagram of the image element circuit in embodiment two.
Embodiment
To make those skilled in the art more fully understand the technical solution of the utility model, below in conjunction with the accompanying drawings to this reality
It is described in detail with the image element circuit and display device of new offer.
Fig. 1 is a kind of structural representation for image element circuit that the utility model embodiment one provides, as shown in figure 1, the picture
Plain circuit includes：First control unit 1, driver element 2, memory cell 3, the second control unit 4 and luminescence unit 5.First control
Unit 1 processed is connected to first node A and data wire；Driver element 2 is connected to first node A, section point B and the first power supply；
Memory cell 3 is connected to first node A and section point B；Second control unit 1 is connected to section point B and data wire；It is luminous
Unit 5 is connected to section point B and second source.
In the image element circuit that the present embodiment provides, the first control unit is connected to first node and data wire, driver element
First node, section point and the first power supply are connected to, memory cell is connected to first node and the second section.Second control unit
It is connected to section point and data wire, luminescence unit is connected to section point and second source, by setting the in the present embodiment
Two control units avoid has electric current process when 0 GTG is shown in luminescence unit, shows so as to avoid luminescence unit in 0 GTG
Lighted when showing.
Fig. 2 is a kind of structural representation for image element circuit that the utility model embodiment two provides, as shown in Fig. 2 the picture
Plain circuit includes：First control unit 1, driver element 2, memory cell 3, the second control unit 4 and luminescence unit 5.First control
Unit 1 processed is connected to first node A and data wire Data；Driver element 2 is connected to first node A, section point B and the first electricity
Source Vdd；Memory cell 3 is connected to first node A and section point B；Second control unit 1 is connected to section point B and data
Line Data；Luminescence unit 5 is connected to section point B and second source Vss.
Driver element 2 includes first switch pipe T1.First switch pipe T1 control pole is connected to first node A, and first opens
The first pole for closing pipe T1 is connected to the first power supply Vdd, and first switch pipe T1 the second pole is connected to section point B.
First control unit 1 includes second switch pipe T2.Second switch pipe T2 control pole is connected to the first grid line G1, the
First pole of two switch transistor Ts 2 is connected to data wire Data, and second switch pipe T2 the second pole is connected to first node A.
Memory cell 3 includes electric capacity C.Electric capacity C first end is connected to first node A, and electric capacity C the second end is connected to
Two node B.
Second control unit 4 includes the 4th switch transistor T 4.The control pole of 4th switch transistor T 4 is connected to scan line Scan, the
First pole of four switch transistor Ts 4 is connected to data wire Data, and the second pole of the 4th switch transistor T 4 is connected to section point A.
Further, the image element circuit also includes reading unit 6.Reading unit 6 is connected to section point B and sense wire
Sense.Specifically, reading unit 6 includes the 3rd switch transistor T 3, and the control pole of the 3rd switch transistor T 3 is connected to the second grid line G2,
First pole of the 3rd switch transistor T 3 is connected to section point B, and the second pole of the 3rd switch transistor T 3 is connected to sense wire Sense.
Luminescent device 6 includes light emitting diode OLED.Light emitting diode OLED the first pole is connected to section point B, hair
Optical diode OLED the second pole is connected to second source Vss.
Fig. 3 is the signal timing diagram of the image element circuit in embodiment two.Below by combination Fig. 2 and Fig. 3 to the present embodiment
The course of work of the image element circuit of offer is described in detail.
The first control signal is loaded in pre-charging stage, the first grid line G1 so that second switch pipe T2 unlatchings, now should
First control signal is high level signal.Data-signal, and T2 pairs of second switch pipe for passing through unlatching are loaded on data wire Data
Electric capacity C is charged, and data-signal is high level signal.The second control signal is loaded on second grid line G2 so that the 5th switching tube
T5 is closed, and now second control signal is low level signal.
The first control signal is loaded in the stage of reading, on the first grid line G1 so that second switch pipe T2 is opened, now, first
Control signal is high level.The second control signal is loaded on second grid line G2 so that the 3rd switch transistor T 3 is opened, now the second control
Signal processed is high level signal.Because first node A voltage is first switch pipe T1 grid g voltage Vg, second saves
Point B voltage is first switch pipe T1 the second pole s voltage Vs, and now, sense wire Sense is in hanging (Floating)
State, because second switch pipe T2 is kept it turned on, therefore Vg (first node A) voltage keeps constant.First switch pipe T1 exists
Open under Vg control, and constantly sense wire Sense is charged so that Vs (section point B) the continuous lifting of voltage, work as Vg-
When Vs voltage is equal to Vth, first switch pipe T1 cut-offs, now detects that the voltage on sense wire Sense is Vs, pass through formula
Vg-Vs calculates the Vth values that can obtain each pixel.
The first control signal is loaded in data write phase, the first grid line G1 so that second switch pipe T2 is opened, now
First control signal is high level signal.Load data-signal on data wire Data, data wire Data pass through unlatching second
Data-signal is write first node A so that first node A voltage changes by switch transistor T 2.Is loaded on second grid line G2
Two control signals are so that the 5th switch transistor T 5 is opened, and now second control signal is high level signal, but this stage sense wire
Sense is closed.
In glow phase, second switch pipe T2 is kept it turned on.Controls of the first switch pipe T1 in first node A voltage
System is lower to open, and loads high level signal on the first power supply Vdd, low level signal is loaded on second source Vss, therefore have electric current stream
Through OLED, so that OLED lights.Loaded if image element circuit carries out the display of 0 GTG, on scan line Scan scanning signal with
Open the 4th switch transistor T 4, now the scanning signal is high level signal, the first switch pipe when the 4th switch transistor T 4 is opened
Opened between T1 grid (i.e. first node A) and the second pole (i.e. section point B) by the second switch pipe T2 of unlatching and the 4th
Pipe T4 conductings, therefore the voltage Vs of second poles of the voltage Vg of first switch pipe T1 grid equal to first switch pipe T1 are closed, i.e.,
The voltage loaded on Vgs=Vg-Vs=0, such data wire Data is equivalent to 0V, so even if drift occurs in Vth, first opens
Cut-off state can be also in by closing pipe T1, and OLED will not light, so as to avoid the problem of OLED is luminous when 0 GTG is shown.If
Scanning signal is loaded when image element circuit carries out other displays outside 0 GTG, on scan line Scan so that the 4th switch transistor T 4 is closed
Close, now the scanning signal is low level signal, and the 4th switch transistor T 4 does not interfere with the normal display of image element circuit when closing.
In the image element circuit that the present embodiment provides, the first control unit is connected to first node and data wire, driver element
First node, section point and the first power supply are connected to, memory cell is connected to first node and the second section.Second control unit
It is connected to section point and data wire, luminescence unit is connected to section point and second source, by setting the in the present embodiment
Two control units avoid has electric current process when 0 GTG is shown in luminescence unit, shows so as to avoid luminescence unit in 0 GTG
Lighted when showing.
The utility model embodiment three provides a kind of display device, and the display device includes above-described embodiment one or implemented
The image element circuit that example two provides.
In the display device that the present embodiment provides, the first control unit is connected to first node and data wire, driver element
First node, section point and the first power supply are connected to, memory cell is connected to first node and the second section.Second control unit
It is connected to section point and data wire, luminescence unit is connected to section point and second source, by setting the in the present embodiment
Two control units avoid has electric current process when 0 GTG is shown in luminescence unit, shows so as to avoid luminescence unit in 0 GTG
Lighted when showing.
It is understood that embodiment of above is merely to illustrate that principle of the present utility model and used exemplary
Embodiment, but the utility model is not limited thereto.For those skilled in the art, this is not being departed from
In the case of the spirit and essence of utility model, various changes and modifications can be made therein, and these variations and modifications are also considered as this reality
With new protection domain.
Claims (9)
- A kind of 1. image element circuit, it is characterised in that including：First control unit, driver element, memory cell, the second control are single Member and luminescence unit；First control unit is connected to first node and data wire；The driver element is connected to the first node, section point and the first power supply；The memory cell is connected to the first node and the section point；Second control unit is connected to the section point and data wire；The luminescence unit is connected to the section point and second source.
- 2. image element circuit according to claim 1, it is characterised in that the driver element includes first switch pipe；The control pole of the first switch pipe is connected to the first node, and the first pole of the first switch pipe is connected to described First power supply, the second pole of the first switch pipe are connected to the section point.
- 3. image element circuit according to claim 1, it is characterised in that first control unit includes second switch pipe；The control pole of the second switch pipe is connected to the first grid line, and the first pole of the second switch pipe is connected to the data Line, the second pole of the second switch pipe are connected to the first node.
- 4. image element circuit according to claim 1, it is characterised in that the memory cell includes electric capacity；The first end of the electric capacity is connected to the first node, and the second end of the electric capacity is connected to section point.
- 5. image element circuit according to claim 1, it is characterised in that second control unit includes the 4th switching tube；The control pole of 4th switching tube is connected to scan line, and the first pole of the 4th switching tube is connected to the data Line, the second pole of the 4th switching tube are connected to the section point.
- 6. image element circuit according to claim 1, it is characterised in that also including reading unit；The reading unit is connected to section point and sense wire.
- 7. image element circuit according to claim 6, it is characterised in that the reading unit includes the 3rd switching tube；The control pole of 3rd switching tube is connected to the second grid line, and the first pole of the 3rd switching tube is connected to described second Node, the second pole of the 3rd switching tube are connected to the sense wire.
- 8. image element circuit according to claim 1, it is characterised in that the luminescent device includes light emitting diode；First pole of the light emitting diode is connected to the section point, and the second pole of the light emitting diode is connected to described Second source.
- 9. a kind of display device, it is characterised in that including any described image element circuit of claim 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720282744.6U CN206657641U (en) | 2017-03-22 | 2017-03-22 | Image element circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720282744.6U CN206657641U (en) | 2017-03-22 | 2017-03-22 | Image element circuit and display device |
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| Publication Number | Publication Date |
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| CN206657641U true CN206657641U (en) | 2017-11-21 |
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| CN201720282744.6U Active CN206657641U (en) | 2017-03-22 | 2017-03-22 | Image element circuit and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107978279A (en) * | 2018-01-25 | 2018-05-01 | 京东方科技集团股份有限公司 | Data voltage compensation method, compensation device and the display system of image element circuit |
| CN108877650A (en) * | 2017-05-12 | 2018-11-23 | 京东方科技集团股份有限公司 | Pixel-driving circuit, driving compensation method, display base plate and display device |
-
2017
- 2017-03-22 CN CN201720282744.6U patent/CN206657641U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108877650A (en) * | 2017-05-12 | 2018-11-23 | 京东方科技集团股份有限公司 | Pixel-driving circuit, driving compensation method, display base plate and display device |
| US11011118B2 (en) | 2017-05-12 | 2021-05-18 | Boe Technology Group Co., Ltd. | Pixel-driving circuit and a compensation method thereof, a display panel, and a display apparatus |
| CN107978279A (en) * | 2018-01-25 | 2018-05-01 | 京东方科技集团股份有限公司 | Data voltage compensation method, compensation device and the display system of image element circuit |
| CN107978279B (en) * | 2018-01-25 | 2020-01-31 | 京东方科技集团股份有限公司 | Data voltage compensation method and device of pixel circuit and display system |
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