CN206595985U - Clock and data recovery device - Google Patents
Clock and data recovery device Download PDFInfo
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- CN206595985U CN206595985U CN201720236753.1U CN201720236753U CN206595985U CN 206595985 U CN206595985 U CN 206595985U CN 201720236753 U CN201720236753 U CN 201720236753U CN 206595985 U CN206595985 U CN 206595985U
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- 238000011084 recovery Methods 0.000 title abstract description 11
- 239000000284 extract Substances 0.000 claims abstract description 12
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 34
- 239000000203 mixture Substances 0.000 claims description 28
- 230000008030 elimination Effects 0.000 claims description 9
- 238000003379 elimination reaction Methods 0.000 claims description 9
- 238000012549 training Methods 0.000 claims description 8
- 238000012360 testing method Methods 0.000 claims description 6
- 238000012216 screening Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 19
- 101100219315 Arabidopsis thaliana CYP83A1 gene Proteins 0.000 description 15
- 101000806846 Homo sapiens DNA-(apurinic or apyrimidinic site) endonuclease Proteins 0.000 description 15
- 101000835083 Homo sapiens Tissue factor pathway inhibitor 2 Proteins 0.000 description 15
- 101100269674 Mus musculus Alyref2 gene Proteins 0.000 description 15
- 101100140580 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) REF2 gene Proteins 0.000 description 15
- 102100026134 Tissue factor pathway inhibitor 2 Human genes 0.000 description 15
- 230000005611 electricity Effects 0.000 description 11
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 108010076504 Protein Sorting Signals Proteins 0.000 description 4
- 230000018199 S phase Effects 0.000 description 2
- 210000001367 artery Anatomy 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 210000003462 vein Anatomy 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005314 correlation function Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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Abstract
The utility model provides a clock pulse and data recovery device, it includes phase-locked loop, mask signal generating circuit, first clock pulse extractor and second clock pulse extractor. The masking signal generating circuit receives at least one of a plurality of output clock signals of the phase locked loop to generate a masking signal. The first clock extractor extracts a clock component from the data signal as a reference clock signal of the phase-locked loop according to mask control of the mask signal. The second clock extractor extracts a corresponding clock component from a corresponding output clock signal among the output clock signals as a feedback clock signal of the phase-locked loop according to mask control of the mask signal.
Description
Technical field
The utility model is related to a kind of electronic circuit, and more particularly to a kind of clock pulse and data recovery (clock and
Data recovery, CDR) device.
Background technology
Periodicity embedded clock coding (Periodically-Embedded Clock Encoding, PECE) system can
So that clock signal is embedded in data-signal.Sender can would be embedded with the data signal transmission of clock pulse composition to recipient.
Clock signal is embedded with by recipient using clock pulse and data recovery (clock and data recovery, CDR) device from described
Taken out in the data-signal of clock pulse composition.According to the clock signal through taking-up, clock pulse can be from the number with return apparatus
It is believed that number data component correctly sample/reply data.
Utility model content
The utility model provides a kind of clock pulse and data recovery (clock and data recovery, CDR) device, uses
Clock signal is referred to be extracted from data-signal, and multiple output clock pulse letters are produced with reference to clock signal according to this
Number.
A kind of clock pulse of the present utility model and return apparatus include phase-locked loop circuit, matte signal generation circuit,
First clock pulse extractor and the second clock pulse extractor.Phase-locked loop circuit is to detect with reference to clock signal and feedback clock pulse letter
Number phase relation, and adjust multiple output clock signals according to testing result.Matte signal generation circuit is coupled to described
Phase-locked loop circuit, to receive at least one among the multiple output clock signal.Matte signal generation circuit is to produce
Raw matte signal.The data input pin of first clock pulse extractor receives data-signal.The control end coupling of first clock pulse extractor
To matte signal generation circuit, to receive the matte signal.First clock pulse extractor is according to the shade control of the matte signal
System, and clock pulse composition is extracted from the data-signal and is used as the reference clock signal.The output end of first clock pulse extractor
The reference clock signal is provided to phase-locked loop circuit.The clock input of second clock pulse extractor is coupled to phase-locked loop electricity
Road, to receive a correspondence output clock signal among the multiple output clock signal.The control of second clock pulse extractor
End is coupled to matte signal generation circuit, to receive the matte signal.Second clock pulse extractor is according to the matte signal
Shade controls and extracts correspondence clock pulse composition from the correspondence output clock signal and be used as the feedback clock signal.When second
The output end of arteries and veins extractor provides the feedback clock signal to phase-locked loop circuit.
In an embodiment of the present utility model, above-mentioned matte signal generation circuit includes frequency eliminating circuit.Frequency eliminating circuit
Phase-locked loop circuit is coupled to, to receive a first corresponding clock signal among the multiple output clock signal.Frequency elimination
Circuit to the described first correspondence clock signal to carry out frequency elimination, to obtain matte signal, and provides the matte signal to the
One clock pulse extractor and the second clock pulse extractor.
In an embodiment of the present utility model, the first above-mentioned clock pulse extractor includes shade circuit and multiplexing
Device.The input of shade circuit is to receive the data-signal.The control end of shade circuit is coupled to matte signal and produces electricity
Road, to receive the matte signal.When shade circuit is controlled according to the shade of the matte signal and extracted from data-signal
Arteries and veins composition is as through shade clock signal.The first input end of multiplexer is coupled to shade circuit, described through hiding to receive
Cover clock signal.Second input of multiplexer is to receive data-signal.The output end of multiplexer provides described
With reference to clock signal to phase-locked loop circuit.
In an embodiment of the present utility model, during the training period, the second input of multiplexer is electrically connected
To the output end of multiplexer.During locking, the first input end of multiplexer is electrically connected to multiplexer
Output end.
In an embodiment of the present utility model, above-mentioned shade circuit includes double edge triggers.Double edge triggers it is defeated
Enter end and be coupled to system voltage.The positive triggering end of double edge triggers receives the positive data-signal of data-signal.Double edge triggers
Anti- triggering end receive data-signal anti-phase data signal.The bob-weight of double edge triggers puts end and is coupled to matte signal generation electricity
Road, to receive the matte signal.The output ends of double edge triggers provide it is described through shade clock signal to multiplexer
First input end.
In an embodiment of the present utility model, above-mentioned shade circuit includes trigger.The input coupling of trigger
To system voltage.The triggering end of trigger receives data-signal.The bob-weight of trigger puts end and is coupled to matte signal generation circuit,
To receive the matte signal.The output end of trigger provides first input through shade clock signal to multiplexer
End.
In an embodiment of the present utility model, above-mentioned the second clock pulse extractor include shade circuit, frequency eliminating circuit with
And multiplexer.The input of shade circuit is coupled to phase-locked loop circuit, to receive the correspondence output clock signal.Hide
The control end of cover circuit is coupled to matte signal generation circuit, to receive the matte signal.Shade circuit is according to the shade
The shade of signal controls and extracts correspondence clock pulse composition as through shade clock signal from the correspondence output clock signal.Remove
Frequency circuit is coupled to phase-locked loop circuit, to receive one first correspondence clock pulse letter among the multiple output clock signal
Number.Frequency eliminating circuit to the described first correspondence clock signal to carry out frequency elimination, to obtain feedback signal.The first of multiplexer
Input is coupled to shade circuit, described through shade clock signal to receive.Second input of multiplexer, which is coupled to, to be removed
The output end of frequency circuit, to receive the feedback signal.The output end of multiplexer provides the feedback clock signal to lock
Phase loop circuit.
In an embodiment of the present utility model, during the training period, the second input of multiplexer is electrically connected
To the output end of multiplexer.During locking, the first input end of multiplexer is electrically connected to multiplexer
Output end.
In an embodiment of the present utility model, above-mentioned shade circuit includes double edge triggers.Double edge triggers it is defeated
Enter end and be coupled to system voltage.The positive triggering end of double edge triggers is coupled to phase-locked loop circuit, is exported with receiving the correspondence
Clock signal.The anti-triggering end of double edge triggers is coupled to phase-locked loop circuit, is worked as with receiving the multiple output clock signal
In a 3rd corresponding clock signal, wherein it is described correspondence output clock signal and the 3rd corresponding clock signal it is anti-each other
Phase.The bob-weight of double edge triggers puts end and is coupled to matte signal generation circuit, to receive the matte signal.Double edge triggers
Output end provides the first input end through shade clock signal to multiplexer.
In an embodiment of the present utility model, above-mentioned shade circuit includes trigger.The input coupling of trigger
To system voltage.The triggering end of trigger is coupled to phase-locked loop circuit, to receive the correspondence output clock signal.Trigger
Bob-weight put end and be coupled to matte signal generation circuit, to receive the matte signal.The output end of trigger provides the warp
First input end of the shade clock signal to multiplexer.
Based on above-mentioned, clock pulse described in all embodiments of the present utility model with return apparatus there are two clock pulses to extract
Device, the two clock pulse extractors are configured in the reference clock signal path and feedback clock signal road of phase-locked loop circuit respectively
In footpath, to improve timing offset (clock skew).
For features described above of the present utility model and advantage can be become apparent, special embodiment below, and coordinate appended
Accompanying drawing is described in detail below.
Brief description of the drawings
Figure 1A is circuit box (circuit block) signal for the embodiment for illustrating clock pulse and return apparatus
Figure.
Figure 1B is the circuit box schematic diagram for another embodiment for illustrating clock pulse and return apparatus.
Fig. 2 is according to a kind of clock pulse and the circuit box of return apparatus shown by another embodiment of the utility model
Schematic diagram.
Fig. 3 be according to the embodiment of the utility model one illustrate the first clock pulse extractor shown in Fig. 2, the second clock pulse extractor with
The circuit box schematic diagram of matte signal generation circuit.
Fig. 4 is the signal sequence schematic diagram for illustrating circuit shown in Fig. 3 according to the embodiment of the utility model one.
Fig. 5 is the signal sequence schematic diagram for illustrating circuit shown in Fig. 3 according to the embodiment of the utility model one.
Fig. 6 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 according to the embodiment of the utility model one.
Fig. 7 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 according to another embodiment of the utility model.
Fig. 8 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 according to the embodiment of the utility model one.
Fig. 9 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 according to another embodiment of the utility model.
Description of reference numerals：
10、100、200：Clock pulse and return apparatus；
13：Delay locked loop circuit；
110：Clock pulse extractor；
130、230：Phase-locked loop circuit；
131：Phase detecting circuit；
132：Voltage-controlled oscillator；
150、250：Sample circuit；
210：First clock pulse extractor；
211：Shade circuit；
212：Multiplexer；
220：Second clock pulse extractor；
221：Shade circuit；
222：Frequency eliminating circuit；
224：Multiplexer；
240：Matte signal generation circuit；
241：Frequency eliminating circuit；
610、810：Double edge triggers；
710、910：Trigger；
CK[1]、CK[2]、CK[3]、CK[4]、CK[5]、CK[6]、CK[n]：Export clock signal；
CK[6]’：Through shade clock signal；
D_N：Anti-phase data signal；
D_P：Positive data-signal；
Dc：Clock pulse composition；
Dd：Data component；
Din：Data-signal；
Din’：Through shade clock signal；
Dout：Through replying data；
FB1、FB2：Feed back clock signal；
REF1、REF2：With reference to clock signal；
Sfb：Feedback signal；
Sm1、Sm2：Matte signal.
Embodiment
" coupling (or connection) " word used in this case specification in full (including claim), which can refer to, appoints
What direct or indirect connection means.For example, if first device coupling (or connection), should in second device described in text
This is construed as the first device and can be directly connected to the second device, or the first device can by other devices or
Certain connection means and be coupled indirectly to the second device.In addition, all possible parts, using identical in drawings and Examples
Element/component/step of label represents same or like part.Identical label is not used in be the same as Example or identical term is used
Element/component/step can be with cross-referenced related description.
Figure 1A is the embodiment for illustrating clock pulse and data recovery (clock and data recovery, CDR) device
Circuit box (circuit block) schematic diagram.Data-signal Din shown in Figure 1A is to meet periodicity embedded clock coding
The signal of (Periodically-Embedded Clock Encoding, PECE) system.That is, sender can believe clock pulse
Embedding data signal Din is ceased, then outputting data signals Din is to recipient.Recipient utilizes clock pulse and return apparatus 100
Taking-up/recovered clock signal (as clock signal REF1 is referred to) from data-signal Din, and taken from data-signal Din
Go out/reply data component as through replying data Dout.
Clock pulse shown in Figure 1A includes clock pulse extractor (clock extractor) 110, delay with return apparatus 10 and locked
Determine loop (delay-locked loop, DLL) circuit 13 and sample circuit 150.Delay locked loop circuit 13 can produce many
Individual output clock signal CK [1]~CK [n].These output clock signal CK [1]~CK [n] each have out of phase.Clock pulse
The control end of extractor 110 is coupled to delay locked loop circuit 13, to receive these output clock signal CK [1]~CK [n]
One of them (as matte signal Sm1).The data input pin of clock pulse extractor 110 receives the data letter for being embedded with clock pulse composition
Number Din.Clock pulse extractor 110 extracts clock pulse composition from data-signal Din and made according to the control of the matte signal Sm1
To refer to clock signal REF1.The output end of clock pulse extractor 110 is provided gives delay locked loop electricity with reference to clock signal REF1
Road 13.
Delay locked loop circuit 13 can be existing delay locked loop, therefore repeat no more.Delay locked loop electricity
These output clock signals produced by the voltage controlled delay line (voltage-controlled delay line, VCDL) on road 13
One of them of CK [1]~CK [n] can be as feedback clock signal FB1, and this feedback clock signal FB1 is transferred to delay
The phase detecting circuit of locked loop circuit 13.The phase detecting circuit of delay locked loop circuit 13, which can be detected, refers to clock pulse
Signal REF1 and feedback clock signal FB1 phase relation, and control delay locked loop circuit 13 according to testing result
Voltage controlled delay line, to adjust these output clock signal CK [1]~CK [n] phase.According to these output clock signals CK
[1]~CK [n] phase, sample circuit 150 can be sampled out from data-signal Din data component through replying data
Dout。
As described above, clock pulse extractor 110 is extracted from data-signal Din with reference to clock signal REF1.However, clock pulse
Extractor 110 will postpone to refer to clock signal REF1, cause timing offset (clockskew).Then, with reference to clock signal
Phase relation between REF1 and feedback clock signal FB1 may distortion.Circuit has used delay locked loop shown in Figure 1A
Circuit 13, therefore the problem of have timing offset.Delay locked loop circuit 13 is easily influenceed by process variation, causes electricity
Bottleneck in dataway operation speed.
Figure 1B is the circuit box schematic diagram for another embodiment for illustrating clock pulse and return apparatus.Data shown in Figure 1B
Signal Din is to meet the signal that periodicity embedded clock encodes (PECE) system.Clock pulse shown in Figure 1B and return apparatus
100 include clock pulse extractor (clock extractor) 110, phase-locked loop (phase lock loop, PLL) circuit 130 with
Sample circuit 150.Phase-locked loop circuit 130 can produce multiple output clock signal CK [1]~CK [n].These output clock pulses
Signal CK [1]~CK [n] each has out of phase.The control end of clock pulse extractor 110 is coupled to phase-locked loop circuit 130,
One of them (as matte signal Sm1) to receive these output clock signal CK [1]~CK [n].Clock pulse extractor 110
Data input pin receives the data-signal Din for being embedded with clock pulse composition.Clock pulse extractor 110 is according to the control of the matte signal Sm1
System, and clock pulse composition is extracted from data-signal Din as with reference to clock signal REF1.The output end of clock pulse extractor 110 is carried
Clock signal REF1 is to phase-locked loop circuit 130 for reference.
One of them of these output clock signal CK [1]~CK [n] produced by phase-locked loop circuit 130 can conduct
Clock signal FB1 is fed back, and this feedback clock signal FB1 is transferred to phase-locked loop circuit 130.Phase-locked loop circuit 130 can
To detect the phase relation with reference to clock signal REF1 and feedback clock signal FB1, and it is defeated to adjust these according to testing result
Go out clock signal CK [1]~CK [n].According to these output clock signal CK [1]~CK [n] phase, sample circuit 150 can be with
Sampled out from data-signal Din data component through replying data Dout.
Phase-locked loop circuit 130 shown in Figure 1B includes phase detecting circuit 131 and voltage-controlled oscillator 132.According to
Design requirement, phase detecting circuit 131 can have phase detectors (phase detector), charge pump (charge
) and/or be loop filter (loop filter) pump.Phase-locked loop circuit 130, phase detecting circuit 131 and/or be electricity
Voltage-controlled oscillator 132 can be available circuit/element, therefore repeat no more.Phase detecting circuit 131, which can be detected, refers to clock pulse
Signal REF1 and feedback clock signal FB1 phase relation, and testing result is exported to voltage-controlled oscillator 132.According to inspection
Result is surveyed, voltage-controlled oscillator 132 can produce and adjust output clock signal CK [1]~CK [n].These output clock pulse letters
One of them of number CK [1]~CK [n] can be as feedback clock signal FB1, and this feedback clock signal FB1 is transferred to phase
Position detection circuit 131.
As described above, clock pulse extractor 110 is extracted from data-signal Din with reference to clock signal REF1.However, clock pulse
Extractor 110 will postpone to refer to clock signal REF1, cause timing offset (clock skew).Then, with reference to clock signal
Phase relation between REF1 and feedback clock signal FB1 may distortion.
Fig. 2 is the circuit according to a kind of clock pulse shown by another embodiment of the utility model and return apparatus 200
Block schematic diagram.Clock pulse shown in Fig. 2 includes the first clock pulse extractor 210, the second clock pulse extractor with return apparatus 200
220th, phase-locked loop circuit 230, matte signal generation circuit 240 and sample circuit 250.Clock pulse shown in Fig. 2 and data recovery
Device 200, phase-locked loop circuit 230 and sample circuit 250 be referred to clock pulse shown in Figure 1B and return apparatus 100,
The related description of phase-locked loop circuit 130 and sample circuit 150 is analogized, therefore repeats no more.
Fig. 2 is refer to, phase-locked loop circuit 230 can be detected with reference to clock signal REF2 with feedback clock signal FB2's
Phase relation, and produce and adjust multiple output clock signal CK [1]~CK [n] according to testing result.The coupling of sample circuit 250
Phase-locked loop circuit 230 is connected to, to receive output clock signal CK [1]~CK [n].According to these output clock signal CK [1]
~CK [n] phase, sample circuit 250 can be sampled out from data-signal Din data component through replying data Dout.
Matte signal generation circuit 240 is coupled to phase-locked loop circuit 230, to receive these output clock signal CK [1]
At least one among~CK [n].According among these output clock signal CK [1]~CK [n] it is described at least one, shade
Signal generating circuit 240 can produce matte signal Sm2 to the first clock pulse extractor 210 and the second clock pulse extractor 220.
The data input pin of first clock pulse extractor 210 receives the data-signal Din with clock pulse composition.First clock pulse is carried
The control end of device 210 is taken to be coupled to matte signal generation circuit 240, to receive matte signal Sm2.According to matte signal Sm2's
Shade is controlled, and the first clock pulse extractor 210 can extract clock pulse composition as the reference clock signal from data-signal Din
REF2.The output end of first clock pulse extractor 210 provides the reference clock signal REF2 to phase-locked loop circuit 230.
The clock input of second clock pulse extractor 220 is coupled to phase-locked loop circuit 230, to receive the output clock pulse
A correspondence output clock signal among signal CK [1]~CK [n].The control end of second clock pulse extractor 220 is coupled to screening
Cover signal generating circuit 240, to receive the matte signal Sm2.Controlled according to matte signal Sm2 shade, the second clock pulse is carried
Device 220 is taken to extract correspondence clock pulse composition from the correspondence output clock signal as feedback clock signal FB2.Second
The output end of clock pulse extractor 220 provides feedback clock signal FB2 to phase-locked loop circuit 230.
First clock pulse extractor 210 described in Fig. 2 and the second clock pulse extractor 220 are referred to clock pulse extractor described in Figure 1B
110 related description.First clock pulse extractor 210 is extracted from data-signal Din with reference to clock signal REF2.Second clock pulse
Extractor 220 extracts feedback clock pulse from a correspondence output clock signal among output clock signal CK [1]~CK [n]
Signal FB2.Although the first clock pulse extractor 210 can be delayed with reference to clock signal REF2, the second clock pulse extractor 220 also can
Delay feedback clock signal FB2.That is, the timing offset with reference to clock signal REF2 can be fit to feedback clock pulse letter
Number FB2 timing offset.
Fig. 3 is to illustrate that the first clock pulse extractor 210 shown in Fig. 2, the second clock pulse are extracted according to the embodiment of the utility model one
The circuit box schematic diagram of device 220 and matte signal generation circuit 240.Output clock pulse letter produced by phase-locked loop circuit 230
Number CK [1]~CK [n] quantity is n, and this n can be determined depending on design requirement.For convenience of explanation, phaselocked loop shown in Fig. 3
Road circuit 230 produces 6 output clock signal CK [1]~CK [6].Export the phase between clock signal CK [1]~CK [6]
About slightly 60 ° of potential difference.
Fig. 4 is the signal sequence schematic diagram for illustrating circuit shown in Fig. 3 according to the embodiment of the utility model one.It is horizontal shown in Fig. 4
Axle represents the time.Phase-locked loop circuit 230 produces 6 output clock signal CK [1]~CK [6], wherein output clock signal CK
[1] about slightly 60 ° of the phase difference between~CK [6].It is assumed herein that, when phase-locked loop circuit 230 is locked, namely when anti-
When presenting the clock signal FB2 identical reference clock signal REF2 of phase phase, output clock signal CK [6] phase is rough right
The neat phase with reference to clock signal REF2.
It refer to Fig. 3 and Fig. 4.Matte signal generation circuit 240 includes frequency eliminating circuit 241.Frequency eliminating circuit 241 is coupled to lock
Phase loop circuit 230, to receive (referred to here as first correspondence clock pulse a letter among output clock signal CK [1]~CK [6]
Number, e.g. export clock signal CK [5] or other output clock signals).Frequency eliminating circuit 241 can be to first correspondence
Clock signal CK [5] carries out frequency elimination, to obtain the clock signal after frequency elimination, namely matte signal Sm2.For example (but not
It is limited to this), frequency eliminating circuit 241 can be by the frequency of the described first corresponding clock signal CK [5] divided by 3 (or other real numbers, by setting
Meter demand is determined), to obtain matte signal Sm2 (as shown in Figure 4).The present embodiment is not intended to limit the implementation of frequency eliminating circuit 241
Mode.According to design requirement, frequency eliminating circuit 241 can be existing frequency eliminating circuit or other frequency eliminating circuits.Frequency eliminating circuit 241
Output end to provide matte signal Sm2 (as shown in Figure 4) to the first clock pulse extractor 210 and the second clock pulse extractor 220.
First clock pulse extractor 210 includes shade circuit 211 and multiplexer 212.The input of shade circuit 211
Receive data-signal Din.The control end of shade circuit 211 is coupled to matte signal generation circuit 240, to receive matte signal
Sm2.Shade circuit 211 is controlled according to matte signal Sm2 shade, and clock pulse composition is extracted from data-signal Din and is used as warp
Shade clock signal Din '.
Fig. 5 is the signal sequence schematic diagram for illustrating circuit shown in Fig. 3 according to the embodiment of the utility model one.It is horizontal shown in Fig. 5
Axle represents the time.Data-signal Din includes clock pulse composition Dc and data component Dd.It is assumed herein that, when phase-locked loop circuit 230
During locking, output clock signal CK [6] the rough align data signal Din of phase includes clock pulse composition Dc phase.Shade
Circuit 211 is controlled by matte signal Sm2.When matte signal Sm2 is the first logical states (such as low logic voltage), shade circuit
211 can shade data-signal Din (namely not making data-signal Din pass through shade circuit 211).Therefore, through shade clock signal
Din ' voltage quasi position is low logic voltage.When matte signal Sm2 is the second logical states (such as high logic voltage), shade electricity
Road 211 will not shade data-signal Din (namely allowing data-signal Din to pass through shade circuit 211).It is the in matte signal Sm2
During two logical states, the waveform through shade clock signal Din ' is data-signal Din waveform.Therefore, believed according to shade
Number Sm2 shade control, shade circuit 211 can extract clock pulse composition Dc as through shade clock pulse letter from data-signal Din
Number Din '.
Fig. 6 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 211 according to the embodiment of the utility model one.
This assumes that data-signal Din is differential wave.In the embodiment shown in fig. 6, shade circuit 211 includes a double edge trigger
(double-edge triggered flip-flop)610.The input D of double edge triggers 610 is coupled to system voltage VDD.
The positive triggering end of double edge triggers 610 receives data-signal Din positive data-signal D_P.The anti-triggering of double edge triggers 610
End receives data-signal Din anti-phase data signal D_N.The bob-weight of double edge triggers 610 puts end RSTB and is coupled to matte signal
Generation circuit 240, to receive matte signal Sm2.The output end Q of double edge triggers 610 is provided and given through shade clock signal Din '
The first input end of multiplexer 212.
In the embodiment shown in fig. 6, double edge triggers 610 can extract data-signal Din periodicity insertion clock pulse (i.e.
For clock pulse composition) positive edge.In many different cycles embedded clocks coding (PECE) agreement, data-signal Din week
Phase property insertion clock pulse not necessarily positive edge clock pulse.PECE cryptoprinciple is：Fixed several binary digits necessarily occur one
Individual clock-edge (clock edge, as clock pulse composition), to allow receiving terminal (such as clock pulse and return apparatus 200) can
With recovered clock again and data.However, in many different cycles embedded clocks coding (PECE) agreement, this clock pulse
The clock-edge of composition is probably positive edge, it may be possible to negative edge, or is probably that positive edge and negative edge have.Double edge triggers 610 can
To be reached an agreement on suitable for a variety of PECE.For example, in other PECE agreements, periodically embedded clock pulse is also possible to
It is positive edge negative edge once in a while once in a while.In other embodiments, data-signal Din can be single-ended signal, and data-signal Din can
To be transferred into the positive triggering end and anti-triggering end of double edge triggers 610 simultaneously, therefore double edge triggers 610 can extract data
Signal Din periodicity is embedded in the positive edge and/or negative edge of clock pulse.Double edge triggers 610 go for this special PECE associations
It is fixed.Consequently, it is possible to when the first clock pulse extractor 210 can be extracted for positive edge, the negative edge of the embedded clock pulse of periodicity, clock pulse
All types of periodicity embedded clock coding (PECE) systems can be applied to return apparatus 200.
Fig. 7 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 211 according to another embodiment of the utility model.
It is assumed herein that data-signal Din is single-ended signal.In the embodiment shown in fig. 7, shade circuit 211 includes a trigger 710.
The input D of trigger 710 is coupled to system voltage VDD.The triggering end of trigger 710 receives data-signal Din.Trigger
710 bob-weight puts end RSTB and is coupled to matte signal generation circuit 240, to receive matte signal Sm2.The output of trigger 710
Q is held to provide the first input end through shade clock signal Din ' to multiplexer 212.
Fig. 3 and Fig. 4 are refer to, the output end of multiplexer 212 is provided gives phase-locked loop electricity with reference to clock signal REF2
Road 230.Second input of multiplexer 212 is to receive data-signal Din.During the training period (before locking), multichannel
Second input of multiplexer 212 is electrically connected to the output end of multiplexer 212, therefore multiplexer 212 can be with
Outputting data signals Din is as with reference to clock signal REF2 during the training period.The first input end of multiplexer 212 is coupled to
Shade circuit 211, to receive through shade clock signal Din '.During locking, the first input end of multiplexer 212 is electric
Property be connected to the output end of multiplexer 212, therefore multiplexer 212 can be exported during locking and believed through shade clock pulse
Number Din ' is as with reference to clock signal REF2.
Second clock pulse extractor 220 includes shade circuit 221, frequency eliminating circuit 222 and multiplexer 224.Shade electricity
The input on road 221 is coupled to phase-locked loop circuit 230, and (clock pulse letter is for example exported to receive the correspondence output clock signal
Output clock signal CK [6] or other output clock signals among number CK [1]~CK [6]).The control of shade circuit 221
End is coupled to matte signal generation circuit 240, to receive matte signal Sm2.Controlled according to matte signal Sm2 shade, shade
Circuit 221 can extract correspondence clock pulse composition as through shade clock signal CK from the correspondence output clock signal CK [6]
[6]’.Shade circuit 221 can export the first input end to multiplexer 224 through shade clock signal CK [6] '.Shade
The details of circuit 221 is referred to the related description of shade circuit 211 to analogize, therefore repeats no more.
Fig. 8 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 221 according to the embodiment of the utility model one.In
In embodiment illustrated in fig. 8, shade circuit 221 includes a double edge trigger 810.The input D of double edge triggers 810 is coupled to
System voltage VDD.The positive triggering end of double edge triggers 810 is coupled to phase-locked loop circuit 230, to receive correspondence output clock pulse letter
Number CK [6].The anti-triggering end of double edge triggers 810 is coupled to phase-locked loop circuit 230, to receive output clock signal CK [1]
Another correspondence clock signal (for example exporting clock signal CK [3] or other output clock signals) among~CK [6].Its
In, the correspondence output clock signal CK [6] and another described corresponding clock signal CK [3] are anti-phase each other.Double edge triggers
810 bob-weight puts end RSTB and is coupled to matte signal generation circuit 240, to receive matte signal Sm2.Double edge triggers 810
Output end Q provides the first input end to multiplexer 224 through shade clock signal CK [6] '.
Fig. 9 is the circuit box schematic diagram for illustrating shade circuit shown in Fig. 3 221 according to another embodiment of the utility model.
In the embodiment shown in fig. 9, shade circuit 221 includes a trigger 910.The input D of trigger 910 is coupled to system electricity
Press VDD.The triggering end of trigger 910 is coupled to phase-locked loop circuit 230, to receive correspondence output clock signal CK [6].Triggering
The bob-weight of device 910 puts end RSTB and is coupled to matte signal generation circuit 240, to receive matte signal Sm2.Trigger 910 it is defeated
Go out to hold Q to provide the first input end through shade clock signal CK [6] ' to multiplexer 224.
Fig. 3 and Fig. 4 are refer to, frequency eliminating circuit 222 is coupled to phase-locked loop circuit 230, to receive output clock signal CK
[1] among~CK [6] one (referred to here as the first corresponding clock signal, e.g. export clock signal CK [6] or other
Export clock signal).Frequency eliminating circuit 222 can corresponding to described first clock signal CK [6] carry out frequency elimination, to obtain through frequency elimination
Clock signal afterwards, namely feedback signal Sfb.For example (but not limited to), frequency eliminating circuit 222 can be by described first pair
Clock signal CK [6] frequency divided by 3 (or other real numbers, determined by design requirement) is answered, to obtain feedback signal Sfb (such as
Shown in Fig. 4).The present embodiment is not intended to limit the embodiment of frequency eliminating circuit 222.According to design requirement, frequency eliminating circuit 222 can be
Existing frequency eliminating circuit or other frequency eliminating circuits.The output end of frequency eliminating circuit 222 provides feedback signal Sfb (as shown in Figure 4)
The second input to multiplexer 224.
It refer to Fig. 3.The output end of multiplexer 224 provides feedback clock signal FB2 to phase-locked loop circuit 230.
Second input of multiplexer 224 is coupled to the output end of frequency eliminating circuit 222, to receive feedback signal Sfb.In training period
Between (before locking), the second input of multiplexer 224 is electrically connected to the output end of multiplexer 224, therefore
Multiplexer 224 can be used as feedback clock signal FB2 by output feedback signal Sfb during the training period.Multiplexer 224
First input end is coupled to shade circuit 221, to receive through shade clock signal CK [6] '.During locking, multiplexer
224 first input end is electrically connected to the output end of multiplexer 224, therefore multiplexer 224 can be in locking
Period output is used as feedback clock signal FB2 through shade clock signal CK [6] '.
It refer to Fig. 3 and Fig. 5.Clock signal CK [6] turns into through shade clock signal via the delay of shade circuit 221
CK[6]’.Data-signal Din clock pulse composition turns into through shade clock signal Din ' via the delay of shade circuit 211.By
There is the circuit structure of similar (or identical), therefore the delay of shade circuit 211 with shade circuit 221 in shade circuit 211
The delay of (or identical) shade circuit 221 can be similar to.After loop-locking, data-signal Din clock pulse composition is by hiding
The delay of cover circuit 211 and multiplexer 212 and as referring to clock signal REF2, and clock signal CK [6] passes through shade
The delay of circuit 221 and multiplexer 224 and as feedback clock signal FB2.Because with reference to clock signal REF2 and feedback
Clock signal FB2 has the delay of similar (or identical), therefore with reference to clock signal REF2 with feedback clock signal FB2's
Phase still can stably align.
It is worth noting that, in different application situations, the first clock pulse extractor 210, the second clock pulse extractor 220
And/or the correlation function of matte signal generation circuit 240 can utilize general hardware description language (hardware
Description languages, such as Verilog HDL or VHDL) or other suitable programming languages realize.It is described hard
Part description language, which can be arranged to any of computer, can access media (computer-accessible medias),
For example tape (magnetic tapes), semiconductor (semiconductors) memory, disk (magnetic disks) or
CD (compact disks, such as CD-ROM or DVD-ROM), or internet (Internet), wire communication can be passed through
(wired communication), radio communication (wireless communication) or the transmission of other communication medias are described
Hardware description language.The hardware description language can be stored in the accessing in media of computer, in order to by computer
Processor come access/perform the hardware description language programming code (programming codes).In addition, this practicality is new
The device of type can be realized by the combination of hardware and software.
In summary, clock pulse described in all embodiments of the present utility model with return apparatus there are two clock pulses to extract
Device.The two clock pulse extractors are configured in the reference clock signal path and feedback clock signal road of phase-locked loop circuit respectively
In footpath, to improve timing offset (clock skew).
Although the utility model is disclosed as above with embodiment, so it is not limited to the utility model, any affiliated
Technical staff in technical field, is not departing from spirit and scope of the present utility model, when can make a little change and retouching, therefore
Protection domain of the present utility model is worked as to be defined depending on those as defined in claim.
Claims (10)
1. a kind of clock pulse and return apparatus, it is characterised in that the clock pulse includes with return apparatus：
Phase-locked loop circuit, to detect the phase relation with reference to clock signal and feedback clock signal, and according to testing result
To adjust multiple output clock signals；
Matte signal generation circuit, is coupled to the phase-locked loop circuit to receive among the multiple output clock signal extremely
It is few one, to produce matte signal；
First clock pulse extractor, with data input pin, control end and output end, wherein the data input pin receives data letter
Number, the control end of the first clock pulse extractor is coupled to the matte signal generation circuit and believed with receiving the shade
Number, the first clock pulse extractor controls according to the shade of the matte signal and clock pulse composition is extracted from the data-signal
As the reference clock signal, and the first clock pulse extractor the output end provide the reference clock signal to
The phase-locked loop circuit；And
Second clock pulse extractor, with clock input, control end and output end, wherein the clock input be coupled to it is described
Phase-locked loop circuit exports clock signal, second clock pulse to receive a correspondence among the multiple output clock signal
The control end of extractor is coupled to the matte signal generation circuit to receive the matte signal, and second clock pulse is carried
Device is taken to be controlled according to the shade of the matte signal and extract correspondence clock pulse composition conduct from the correspondence output clock signal
The feedback clock signal, and the output end of the second clock pulse extractor provide the feedback clock signal to described
Phase-locked loop circuit.
2. clock pulse according to claim 1 and return apparatus, it is characterised in that the matte signal generation circuit bag
Include：
Frequency eliminating circuit, is coupled to the phase-locked loop circuit to receive one first pair among the multiple output clock signal
Clock signal is answered, to carry out frequency elimination to the described first correspondence clock signal to obtain the matte signal, and the screening is provided
Cover signal is to the first clock pulse extractor and the second clock pulse extractor.
3. clock pulse according to claim 1 and return apparatus, it is characterised in that the first clock pulse extractor bag
Include：
Shade circuit, with input, control end and output end, wherein the input of the shade circuit is to receive
Data-signal is stated, the control end of the shade circuit is coupled to the matte signal generation circuit and believed to receive the shade
Number, the shade circuit controls according to the shade of the matte signal and clock pulse composition is extracted from the data-signal and is used as warp
Shade clock signal；And
Multiplexer, with first input end, the second input and output end, wherein described the first of the multiplexer
It is described through shade clock signal, second input of the multiplexer to receive that input is coupled to the shade circuit
End provides the reference clock signal to the lock to receive the data-signal, the output end of the multiplexer
Phase loop circuit.
4. clock pulse according to claim 3 and return apparatus, it is characterised in that the multiplexing during the training period
Second input of device is electrically connected to the output end of the multiplexer, and during locking it is described many
The first input end of path multiplexer is electrically connected to the output end of the multiplexer.
5. clock pulse according to claim 3 and return apparatus, it is characterised in that the shade circuit includes double edge and touched
Device is sent out, there is described pair of edge trigger input, positive triggering end, anti-triggering end, bob-weight to put end and output end, described pair of edge triggering
The input of device is coupled to system voltage, and the positive triggering end receives the positive data-signal of the data-signal, described
Anti- triggering end receives the anti-phase data signal of the data-signal, and the bob-weight puts end and is coupled to the matte signal generation circuit
To receive the matte signal, and described pair of edge trigger the output end provide it is described through shade clock signal to described
The first input end of multiplexer.
6. clock pulse according to claim 3 and return apparatus, it is characterised in that the shade circuit includes triggering
There is device, the trigger input, triggering end, bob-weight to put end and output end, and the input of the trigger is coupled to
System voltage, the triggering end receives the data-signal, the bob-weight put end be coupled to the matte signal generation circuit with
The matte signal is received, and the output end of the trigger provides described multiple to the multichannel through shade clock signal
With the first input end of device.
7. clock pulse according to claim 1 and return apparatus, it is characterised in that the second clock pulse extractor bag
Include：
Shade circuit, with input, control end and output end, wherein the input of the shade circuit be coupled to it is described
Phase-locked loop circuit is to receive the correspondence output clock signal, and the control end of the shade circuit is coupled to the shade
Signal generating circuit is to receive the matte signal, and the shade circuit is according to the control of the shade of the matte signal from described
Correspondence clock pulse composition is extracted in correspondence output clock signal as through shade clock signal；
Frequency eliminating circuit, is coupled to the phase-locked loop circuit to receive one first pair among the multiple output clock signal
Clock signal is answered, to obtain feedback signal to the described first correspondence clock signal progress frequency elimination；And
Multiplexer, with first input end, the second input and output end, wherein described the first of the multiplexer
It is described through shade clock signal, second input of the multiplexer to receive that input is coupled to the shade circuit
End is coupled to the output end of the frequency eliminating circuit to receive the feedback signal, and the output end of the multiplexer is provided
The feedback clock signal gives the phase-locked loop circuit.
8. clock pulse according to claim 7 and return apparatus, it is characterised in that the multiplexing during the training period
Second input of device is electrically connected to the output end of the multiplexer, and during locking it is described many
The first input end of path multiplexer is electrically connected to the output end of the multiplexer.
9. clock pulse according to claim 7 and return apparatus, it is characterised in that the shade circuit includes double edge and touched
Device is sent out, there is described pair of edge trigger input, positive triggering end, anti-triggering end, bob-weight to put end and output end, described pair of edge triggering
The input of device is coupled to system voltage, and the positive triggering end is coupled to the phase-locked loop circuit to receive the correspondence
Clock signal is exported, the anti-triggering end is coupled to the phase-locked loop circuit to receive among the multiple output clock signal
The a 3rd corresponding clock signal, it is described correspondence output clock signal and the 3rd corresponding clock signal it is anti-phase each other, institute
State bob-weight and put end and be coupled to the matte signal generation circuit to receive the matte signal, and described pair of edge trigger institute
State output end and the first input end through shade clock signal to the multiplexer is provided.
10. clock pulse according to claim 7 and return apparatus, it is characterised in that the shade circuit includes triggering
There is device, the trigger input, triggering end, bob-weight to put end and output end, and the input of the trigger is coupled to
System voltage, the triggering end is coupled to the phase-locked loop circuit to receive the correspondence output clock signal, the bob-weight
End is put to be coupled to the matte signal generation circuit to receive the matte signal, and the output end of the trigger is carried
For the first input end through shade clock signal to the multiplexer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106200064U TWM540371U (en) | 2017-01-04 | 2017-01-04 | Clock and data recovery apparatus |
| TW106200064 | 2017-01-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206595985U true CN206595985U (en) | 2017-10-27 |
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ID=59255128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720236753.1U Active CN206595985U (en) | 2017-01-04 | 2017-03-10 | Clock and data recovery device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN206595985U (en) |
| TW (1) | TWM540371U (en) |
-
2017
- 2017-01-04 TW TW106200064U patent/TWM540371U/en unknown
- 2017-03-10 CN CN201720236753.1U patent/CN206595985U/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWM540371U (en) | 2017-04-21 |
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