CN206442294U - A kind of charge pump and charge pump circuit - Google Patents
A kind of charge pump and charge pump circuit Download PDFInfo
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- CN206442294U CN206442294U CN201621468106.5U CN201621468106U CN206442294U CN 206442294 U CN206442294 U CN 206442294U CN 201621468106 U CN201621468106 U CN 201621468106U CN 206442294 U CN206442294 U CN 206442294U
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- nmos tube
- clock signal
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- charge pump
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Abstract
The utility model provides a kind of charge pump and charge pump circuit, and charge pump includes：First electric capacity receives the first clock signal, and the second electric capacity receives second clock signal；Clock signal generating module is boosted to the 3rd clock signal and the 4th clock signal, and the 5th and the 6th clock signal is generated with correspondence；First to fourth clock signal is non-overlapping；The drain terminal of first NMOS tube and the drain terminal of the second NMOS tube provide end with input voltage and are connected；3rd NMOS tube, grid end receives the 6th clock signal, and drain terminal is connected with the source of the first NMOS tube, and the source of drain terminal and the first NMOS tube is connected with the other end of the first electric capacity and the grid end of the second NMOS tube respectively；4th NMOS tube, drain terminal is connected with the source of the second NMOS tube, grid end the 5th clock signal of reception, and the source of drain terminal and the second NMOS tube is connected with the other end of the second electric capacity and the grid end of the first NMOS tube respectively.The utility model can effectively reduce output ripple.
Description
Technical field
The utility model is related to technical field of integrated circuits, more particularly to a kind of charge pump and a kind of charge pump circuit.
Background technology
The design architecture of traditional 4V charge pump circuits is as shown in Figure 1.Wherein, Vref ' is the input voltage of charge pump circuit,
VCC ' is the supply voltage of charge pump circuit, and V4V ' is the output voltage of charge pump circuit, and CLKA ' is the input of charge pump circuit
Clock, n type field effect transistor N1 ' is the controlling switch of charge pump circuit.Controlling switch N1 ', which is received, enables control signal
The voltage VDIV ' and input voltage Vref ' of ENABLE ', output voltage V4V ' after resistance 3R ' and resistance R ' partial pressures are connected to and compared
Device COMP ' input, comparator COMP ' output signal DIFOUT ' and input clock CLKA ' are connected to be carried out with grasping with door
Make, come the switch of the clock signal that controls charge pump circuit, charge pump 1 ' is connected to the output signal CLK ' of door.
The design architecture of traditional 4V charge pump circuits has the following disadvantages：By controlling the switch of clock signal to control electricity
The output voltage V4V ' of lotus pump circuit, is substantially the frequency for adjusting clock signal so that output voltage V4V ' ripples are larger.
Utility model content
In view of the above problems, the purpose of the utility model embodiment is to provide a kind of charge pump and charge pump circuit, with
Solve the problem of tradition 4V charge pump circuit output voltage ripples are big.
In order to solve the above problems, the utility model embodiment discloses a kind of charge pump, including：First electric capacity and second
Electric capacity, one end of first electric capacity receives the first clock signal, and one end of second electric capacity receives second clock signal；When
Clock signal generator module, the clock signal generating module is boosted to the 3rd clock signal and the 4th clock signal, with right
The 5th clock signal and the 6th clock signal should be generated；When first clock signal, the second clock signal, the described 3rd
Clock signal and the 4th clock signal are non-overlapping；First NMOS tube and the second NMOS tube, the drain terminal of first NMOS tube
End is provided with the drain terminal of second NMOS tube with the input voltage of charge pump respectively to be connected；
3rd NMOS tube, the drain terminal of the 3rd NMOS tube is connected with the source of first NMOS tube, and the described 3rd
The grid end of NMOS tube receives the 6th clock signal, the drain terminal of the 3rd NMOS tube and the source of first NMOS tube it
Between have first node, the other end and the grid end phase of second NMOS tube of the first node respectively with first electric capacity
Even；4th NMOS tube, the drain terminal of the 4th NMOS tube is connected with the source of second NMOS tube, the 4th NMOS tube
Grid end receives the 5th clock signal, has the between the drain terminal of the 4th NMOS tube and the source of second NMOS tube
Two nodes, the Section Point is connected with the other end of second electric capacity and the grid end of first NMOS tube respectively, described
The source of the source of 4th NMOS tube and the 3rd NMOS tube as the charge pump output end.
Alternatively, the clock signal generating module includes：5th NMOS tube, the drain terminal and power supply of the 5th NMOS tube
It is connected；6th NMOS tube, the drain terminal of the 6th NMOS tube is connected with the power supply；3rd electric capacity, the one of the 3rd electric capacity
End receives the 4th clock signal；First PMOS, the source of the source of first PMOS and the 5th NMOS tube
It is connected, there is the 3rd node, the 3rd node between the source of the source of first PMOS and the 5th NMOS tube
It is connected with the other end of the 3rd electric capacity；4th electric capacity, one end of the 4th electric capacity receives the 3rd clock signal；The
Two PMOSs, the grid end of second PMOS is connected with the 3rd node, the source of second PMOS and described the
The source of six NMOS tubes is connected, and has Section four between the source of the source of second PMOS and the 6th NMOS tube
Point, the fourth node is connected with the other end of the 4th electric capacity and the grid end of first PMOS respectively；7th NMOS
Pipe, the grid end of the 7th NMOS tube receives the 3rd clock signal, the source ground connection of the 7th NMOS tube, the described 7th
The drain terminal of NMOS tube is connected with the drain terminal of first PMOS, the drain terminal of the 7th NMOS tube and first PMOS
Drain terminal exports the 5th clock signal；8th NMOS tube, the grid end of the 8th NMOS tube receives the 4th clock signal,
The source ground connection of 8th NMOS tube, the drain terminal of the 8th NMOS tube is connected with the drain terminal of second PMOS, described
The drain terminal of 8th NMOS tube and the drain terminal of second PMOS export the 6th clock signal.
Alternatively, the 5th NMOS tube and the 6th NMOS tube are Low threshold high pressure NMOS pipe.
Alternatively, first PMOS and second PMOS are high voltage PMOS pipe.
Alternatively, the 7th NMOS tube and the 8th NMOS tube are high pressure NMOS pipe.
Alternatively, the clock signal generating module also includes：First drive module, the input of first drive module
End receives the 3rd clock signal, and the power end of first drive module is connected with the power supply, the first driving mould
The output end of block is connected with the grid end of the 4th electric capacity and the 7th NMOS tube；Second drive module, second driving
The input of module receives the 4th clock signal, and the power end of second drive module is connected with the power supply, described
The output end of second drive module is connected with the grid end of the 3rd electric capacity and the 8th NMOS tube.
Alternatively, first drive module includes：First phase inverter, power end and the electricity of first phase inverter
Source is connected, and the input of first phase inverter receives the 3rd clock signal, when first phase inverter is to the described 3rd
Clock signal carries out anti-phase processing；Second phase inverter, the power end of second phase inverter is connected with the power supply, and described second is anti-
The input of phase device receives the 3rd clock signal after anti-phase processing, and second phase inverter is to the 3rd after the anti-phase processing
Clock signal carries out anti-phase processing, the output end of second phase inverter as first drive module output end.
Alternatively, second drive module includes：3rd phase inverter, power end and the electricity of the 3rd phase inverter
Source is connected, and the input of the 3rd phase inverter receives the 4th clock signal, when the 3rd phase inverter is to the described 4th
Clock signal carries out anti-phase processing；4th phase inverter, the power end of the 4th phase inverter is connected with the power supply, and the described 4th is anti-
The input of phase device receives the 4th clock signal after anti-phase processing, and the 4th phase inverter is to the 4th after the anti-phase processing
Clock signal carries out anti-phase processing, the output end of the 4th phase inverter as second drive module output end.
Alternatively, the charge pump also includes：3rd drive module, the input of the 3rd drive module receives described
First clock signal, the power end of the 3rd drive module is connected with power supply, the output end of the 3rd drive module and institute
The one end for stating the first electric capacity is connected；4th drive module, the input of the 4th drive module receives the second clock letter
Number, the power end of the 4th drive module is connected with the power supply, the output end and described second of the 4th drive module
One end of electric capacity is connected.
In order to solve the above problems, the utility model embodiment also discloses a kind of charge pump circuit, including described electricity
Lotus pump.
The utility model embodiment includes advantages below：First clock signal, second are received by one end of the first electric capacity
One end of electric capacity receives second clock signal, and clock signal generating module is risen to the 3rd clock signal and the 4th clock signal
Pressure, to generate the 5th clock signal of correspondence and the 6th clock signal, wherein, when the first clock signal, second clock signal, the 3rd
Clock signal and the 4th clock signal are non-overlapping, and set the grid end of the 3rd NMOS tube to receive the 6th clock signal, the 4th NMOS
The grid end of pipe receives the 5th clock signal.This way it is possible to avoid the 3rd NMOS tube is needed for first node voltage is less than charge pump
Turned on during output voltage, and avoid the 4th NMOS tube from being turned on when Section Point voltage is less than output voltage needed for charge pump,
The ripple of charge pump output voltage can be effectively reduced.
Brief description of the drawings
Fig. 1 is the design architecture schematic diagram of traditional 4V charge pump circuits；
Fig. 2 is a kind of structural representation of charge pump embodiment of the present utility model；
Fig. 3 is the waveform diagram of signal in a kind of charge pump embodiment of the present utility model；
Fig. 4 is the structural representation of clock signal generating module in a kind of charge pump embodiment of the present utility model；
Fig. 5 is the structural representation of signal generating circuit in a kind of charge pump embodiment of the present utility model.
Embodiment
To enable above-mentioned purpose of the present utility model, feature and advantage more obvious understandable, below in conjunction with the accompanying drawings and tool
Body embodiment is described in further detail to the utility model.
Reference picture 2, it illustrates a kind of structural representation of charge pump embodiment of the present utility model, can specifically be wrapped
Include：First electric capacity C1 and the second electric capacity C2, the first electric capacity C1 one end receive the first clock signal clk 1, the one of the second electric capacity C2
End receives second clock signal CLK2；Clock signal generating module 1,1 pair of the 3rd clock signal clk 3 of clock signal generating module
Boosted with the 4th clock signal clk 4, the 5th clock signal clk 5 and the 6th clock signal clk 6 are generated with correspondence；Reference
Fig. 3, the first clock signal clk 1, second clock signal CLK2, the 3rd clock signal clk 3 and the 4th clock signal clk 4 are mutually not
It is overlapping；First NMOS tube N1 and the second NMOS tube N2, the first NMOS tube N1 drain terminal and the second NMOS tube N2 drain terminal respectively with
The input voltage of charge pump provides end and is connected, and input voltage provides end and provides input voltage vin；3rd NMOS tube N3, the 3rd
NMOS tube N3 drain terminal is connected with the first NMOS tube N1 source, and the 3rd NMOS tube N3 grid end receives the 6th clock signal
There is first node na1, na1 points of first node between CLK6, the 3rd NMOS tube N3 drain terminal and the first NMOS tube N1 source
It is not connected with the first electric capacity C1 other end and the second NMOS tube N2 grid end；4th NMOS tube N4, the 4th NMOS tube N4 leakage
End is connected with the second NMOS tube N2 source, and the 4th NMOS tube N4 grid end receives the 5th clock signal clk 5, the 4th NMOS tube
There is Section Point na2, Section Point na2 is respectively with the second electric capacity C2's between N4 drain terminal and the second NMOS tube N2 source
The other end and the first NMOS tube N1 grid end are connected, and the 4th NMOS tube N4 source is used as electric charge with the 3rd NMOS tube N3 source
The output end of pump.
Wherein, charge pump is by the first electric capacity C1, the second electric capacity C2 high pass characteristic in Fig. 2, constantly to first node
Na1 and Section Point na2 chargings, so that the high voltage that the output end of charge pump is exported needed for maintaining.
This way it is possible to avoid the 3rd NMOS tube is turned on when first node voltage is less than output voltage needed for charge pump, with
And avoid the 4th NMOS tube from being turned on when Section Point voltage is less than output voltage needed for charge pump.Further, since the 3rd clock
Signal CLK3 and the 4th clock signal clk 4 are non-overlapping, then the 5th clock signal clk 5 and the 6th clock signal clk 6 also mutually not
Overlapping, therefore, the 3rd NMOS tube and the 4th NMOS tube will not be simultaneously turned on, and can effectively reduce the line of charge pump output voltage
Ripple.
Alternatively, reference picture 4, clock signal generating module 1 can include：5th NMOS tube N5, the 5th NMOS tube N5's
Drain terminal is connected with power supply, supplies voltages VCC；6th NMOS tube N6, the 6th NMOS tube N6 drain terminal is connected with power supply；3rd
Electric capacity C3, the 3rd electric capacity C3 one end receive the 4th clock signal clk 4；First PMOS P1, the first PMOS P1 source with
5th NMOS tube N5 source is connected, and has the 3rd node between the first PMOS P1 source and the 5th NMOS tube N5 source
Na3, the 3rd node na3 is connected with the 3rd electric capacity C3 other end；When 4th electric capacity C4, the 4th electric capacity C4 one end receive the 3rd
Clock signal CLK3；Second PMOS P2, the second PMOS P2 grid end is connected with the 3rd node na3, the second PMOS P2 source
End is connected with the 6th NMOS tube N6 source, has the 4th between the second PMOS P2 source and the 6th NMOS tube N6 source
Node na4, fourth node na4 are connected with the 4th electric capacity C4 other end and the first PMOS P1 grid end respectively；7th NMOS
Pipe N7, the 7th NMOS tube N7 grid end receive the 3rd clock signal clk 3, the 7th NMOS tube N7 source ground connection, the 7th NMOS tube
N7 drain terminal is connected with the first PMOS P1 drain terminal, the 7th NMOS tube N7 drain terminal and the first PMOS P1 drain terminal output the
Five clock signal clks 5；8th NMOS tube N8, the 8th NMOS tube N8 grid end receive the 4th clock signal clk 4, the 8th NMOS tube
N8 source ground connection, the 8th NMOS tube N8 drain terminal is connected with the second PMOS P2 drain terminal, the 8th NMOS tube N8 drain terminal with
Second PMOS P2 drain terminal exports the 6th clock signal clk 6.Wherein, input voltage vin can be equal to supply voltage VCC.
Specifically, when the 3rd clock signal clk 3 is changed by high level to low level, the 4th clock signal clk 4 is by low
Level changes to high level.It can be seen from the characteristic that electric capacity both end voltage can not be mutated, the first PMOS P1 source voltage terminal liter
Height, the first PMOS P1 grid end voltage reduction, so the first PMOS P1 is turned on, the second PMOS P2 shut-offs, while the 7th
NMOS tube N7 is turned off, the 8th NMOS tube N8 conductings.Now, the voltage of final 6th clock signal clk 6 drops to 0, VCC from 2*VCC
Voltage for supply voltage, and the 5th clock signal clk 5 is increased to 2*VCC from 0.
When the 3rd clock signal clk 3 is changed by low level to high level, the 4th clock signal clk 4 is by high level to low
Level changes.It can be seen from the characteristic that electric capacity both end voltage can not be mutated, the second PMOS P2 source voltage terminal rise, second
PMOS P2 grid end voltage reduction, so the second PMOS P2 is turned on, the first PMOS P1 shut-offs, while the 8th NMOS tube N8
Shut-off, the 7th NMOS tube N7 conductings.Now, it is power supply electricity that the voltage of final 5th clock signal clk 5 drops to 0, VCC from 2*VCC
Pressure, and the voltage of the 6th clock signal clk 6 is increased to 2*VCC from 0.
Alternatively, the 5th NMOS tube N5 and the 6th NMOS tube N6 can be Low threshold high pressure NMOS pipe.Alternatively, first
PMOS P1 and the second PMOS P2 can be high voltage PMOS pipe.Alternatively, the 7th NMOS tube N7 and the 8th NMOS tube N8 can be with
For high pressure NMOS pipe.
Alternatively, reference picture 4, clock signal generating module 1 can also include：First drive module 11, the first driving mould
The input of block 11 receives the 3rd clock signal clk 3, and the output end of the first drive module 11 exports seven clock signal clks _ D,
The power end of first drive module 11 is connected with power supply, output end and the 4th electric capacity C4 and the 7th NMOS of the first drive module 11
Pipe N7 grid end is connected, and the first drive module 11 is used for the output resistance for reducing by the 3rd clock signal clk 3；Second drive module
12, the input of the second drive module 12 receives the 4th clock signal clk 4, the output end output the 8th of the second drive module 12
Clock signal clk _ B_D, the power end of the second drive module 12 is connected with power supply, the output end and the 3rd of the second drive module 12
Electric capacity C3 and the 8th NMOS tube N8 grid end are connected, and the second drive module 12 is used for the output electricity for reducing by the 4th clock signal clk 4
Resistance.
Alternatively, reference picture 4, the first drive module 11 can include：First phase inverter F1, the first phase inverter F1 power supply
End is connected with power supply, and the first phase inverter F1 input receives the 3rd clock signal clk 3, and the first phase inverter F1 is to the 3rd clock
Signal CLK3 carries out anti-phase processing；Second phase inverter F2, the second phase inverter F2 power end is connected with power supply, the second phase inverter F2
Input receive the 3rd clock signal clk 3 after anti-phase processing, the second phase inverter F2 is believed the 3rd clock after anti-phase processing
Number CLK3 carries out anti-phase processing, the second phase inverter F2 output end as the first drive module 11 output end the 7th clock of output
Signal CLK_D.Wherein, the first phase inverter F1, the second phase inverter F2 can be with identical or differ.
Alternatively, reference picture 4, the second drive module 12 can include：3rd phase inverter F3, the 3rd phase inverter F3 power supply
End is connected with power supply, and the 3rd phase inverter F3 input receives the 4th clock signal clk 4, and the 3rd phase inverter F3 is to the 4th clock
Signal CLK4 carries out anti-phase processing；4th phase inverter F4, the 4th phase inverter F4 power end is connected with power supply, the 4th phase inverter F4
Input receive the 4th clock signal clk 4 after anti-phase processing, the 4th phase inverter F4 is believed the 4th clock after anti-phase processing
Number CLK4 carries out anti-phase processing, the 4th phase inverter F4 output end as the second drive module 12 output end the 8th clock of output
Signal CLK_B_D.Wherein, the 3rd phase inverter F3, the 4th phase inverter F4 can be with identical or differ.
Alternatively, reference picture 2, charge pump can also include：3rd drive module 2, the input termination of the 3rd drive module 2
The first clock signal clk 1 is received, the power end of the 3rd drive module 2 is connected with power supply, the output end of the 3rd drive module 2 and the
One electric capacity C1 one end is connected, and the 3rd drive module 2 is used for the output resistance for reducing by the first clock signal clk 1；4 wheel driven dynamic model
Block 3, the input of the 4th drive module 3 receives second clock signal CLK2, power end and the power supply phase of the 4th drive module 3
Even, the output end of the 4th drive module 3 is connected with the second electric capacity C2 one end, and the 4th drive module 3 is used to reduce second clock
Signal CLK2 output resistance.
Alternatively, reference picture 2, the 3rd drive module 2 can include：5th phase inverter F5, the 5th phase inverter F5 power supply
End is connected with power supply, and the 5th phase inverter F5 input receives the first clock signal clk 1, and the 5th phase inverter F5 is to the first clock
Signal CLK1 carries out anti-phase processing；Hex inverter F6, hex inverter F6 power end are connected with power supply, hex inverter F6
Input receive the first clock signal clk 1 after anti-phase processing, hex inverter F6 is believed the first clock after anti-phase processing
Number CLK1 carries out anti-phase processing, hex inverter F6 output end as the 3rd drive module 2 output end.Wherein, the 5th is anti-
Phase device F5, hex inverter F6 can be with identical or differ.
Alternatively, reference picture 2, the 4th drive module 3 can include：7th phase inverter F7, the 7th phase inverter F7 power supply
End is connected with power supply, and the 7th phase inverter F7 input receives second clock signal CLK2, and the 7th phase inverter F7 is to second clock
Signal CLK2 carries out anti-phase processing；8th phase inverter F8, the 8th phase inverter F8 power end is connected with power supply, the 8th phase inverter F8
Input receive second clock signal CLK2, the 8th phase inverter F8 after anti-phase processing the second clock after anti-phase processing believed
Number CLK2 carries out anti-phase processing, the 8th phase inverter F8 output end as the 4th drive module 3 output end.Wherein, the 7th is anti-
Phase device F7, the 8th phase inverter F8 can be with identical or differ.
Alternatively, when producing the first clock signal clk 1, second clock signal CLK2, the 3rd clock signal clk 3 and the 4th
Clock signal CLK4 circuit can be with as shown in figure 5, the circuit includes：First nor gate AN1, the first of the first nor gate AN1 is defeated
Enter the input clock CLK that end receives charge pump.It is the 9th anti-phase that the 9th phase inverter F9 that 2N is sequentially connected, 2N are sequentially connected
Device F9 input is connected with the first nor gate AN1 output end.2M+1 individual the tenth phase inverter F10 being sequentially connected, 2M+1 is individual
The input for the tenth phase inverter F10 being sequentially connected is connected with 2N the 9th phase inverter F9 being sequentially connected output end, 2M+1
Individual the tenth phase inverter F10 being sequentially connected output end exports the first clock signal clk 1.11st phase inverter F11, the 11st
Phase inverter F11 input receives the input clock CLK of charge pump.Second nor gate AN2, the first of the second nor gate AN2 is defeated
The output end for entering end with 2N the 9th phase inverter F9 being sequentially connected is connected, the second nor gate AN2 the second input and the tenth
One phase inverter F11 output end is connected.It is the 12nd anti-that the 12nd phase inverter F12 that 2P is sequentially connected, 2P are sequentially connected
Phase device F12 input is connected with the second nor gate AN2 output end, and individual the 12nd phase inverter F12's being sequentially connected of 2P is defeated
Go out end with the first nor gate AN1 the second input to be connected.The 13rd phase inverter F13 that 2Q+1 is sequentially connected, 2Q+1 according to
13rd phase inverter F13 of secondary connection input is connected with 2P the 12nd phase inverter F12 being sequentially connected output end, 2Q
The output end of first phase inverter exports the 3rd clock signal clk 3 in+1 the 13rd phase inverter F13 for being sequentially connected.First
OR gate A1, the first OR gate A1 first input end are connected with 2Q+1 the 13rd phase inverter F13 being sequentially connected output end, the
One OR gate A1 the second input is connected with the 11st phase inverter F11 output end, the first OR gate A1 output end output second
Clock signal clk 2.Second OR gate A2, the second OR gate A2 first input end is connected with the first OR gate A1 output end, second or
Door A2 the second input is connected with the 11st phase inverter F11 output end, and the second OR gate A2 output end exports the 4th clock
Signal CLK4.Wherein, N, M, P, Q are the integer more than 0, and N, M, P, Q can be equal with equal, part or complete unequal.In Fig. 5,
N, M, P, Q are 1.Wherein, the 9th phase inverter F9, the tenth phase inverter F10, the 11st phase inverter F11, the 12nd phase inverter F12,
13 phase inverter F13 can be with identical or differ.First nor gate AN1, the second nor gate AN2 can be with identical or differ.The
One OR gate A1, the second OR gate A2 can be with identical or differ.
The charge pump of the utility model embodiment includes advantages below：The first clock is received by one end of the first electric capacity to believe
Number, one end of the second electric capacity receives second clock signal, and clock signal generating module is believed the 3rd clock signal and the 4th clock
Number boosted, to generate the 5th clock signal and the 6th clock signal, wherein, the first clock signal, second clock signal,
Three clock signals and the 4th clock signal are non-overlapping, and set the grid end of the 3rd NMOS tube to receive the 5th clock signal, the 4th
The grid end of NMOS tube receives the 6th clock signal.This way it is possible to avoid the 3rd NMOS tube is less than charge pump in first node voltage
Turned on during required output voltage, and avoid the 4th NMOS tube from being led when Section Point voltage is less than output voltage needed for charge pump
It is logical, the ripple of charge pump output voltage can be effectively reduced.
The utility model embodiment also discloses a kind of charge pump circuit, and the charge pump circuit can include above-mentioned electric charge
Pump.
The charge pump circuit of the utility model embodiment includes advantages below：By set the first electric capacity in charge pump one
End receives the first clock signal, and one end of the second electric capacity receives second clock signal, and clock signal generating module is to the 3rd clock
Signal and the 4th clock signal are boosted, to generate the 5th clock signal and the 6th clock signal, wherein, the first clock letter
Number, second clock signal, the 3rd clock signal and the 4th clock signal it is non-overlapping, and set the 3rd NMOS tube grid end receive
5th clock signal, the grid end of the 4th NMOS tube receives the 6th clock signal.This way it is possible to avoid the 3rd NMOS tube in charge pump
Turned on when first node voltage is less than output voltage needed for charge pump, and avoid the 4th NMOS tube low in Section Point voltage
Turned on when output voltage needed for charge pump, the ripple of charge pump output voltage can be effectively reduced.
For charge pump circuit embodiment, because it includes charge pump, so description is fairly simple, related part
Illustrate referring to the part of charge pump embodiment.
Each embodiment in this specification is described by the way of progressive, what each embodiment was stressed be with
Between the difference of other embodiment, each embodiment identical similar part mutually referring to.
Although having been described for the preferred embodiment of the utility model embodiment, those skilled in the art once learn
Basic creative concept, then can make other change and modification to these embodiments.So, appended claims are intended to solution
It is interpreted as including preferred embodiment and falls into having altered and changing for the utility model scope of embodiments.
Finally, in addition it is also necessary to explanation, herein, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between there is any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or terminal device including a series of key elements are not only wrapped
Those key elements, but also other key elements including being not expressly set out are included, or also include being this process, method, article
Or the intrinsic key element of terminal device.In the absence of more restrictions, by wanting that sentence "including a ..." is limited
Element, it is not excluded that also there is other identical element in the process including the key element, method, article or terminal device.
Above to a kind of charge pump provided by the utility model and a kind of charge pump circuit, it is described in detail, this
Apply specific case in text to be set forth principle of the present utility model and embodiment, the explanation of above example is
It is used to help understand method of the present utility model and its core concept；Simultaneously for those of ordinary skill in the art, according to this
The thought of utility model, will change in specific embodiments and applications, in summary, this specification content
It should not be construed as to limitation of the present utility model.
Claims (10)
1. a kind of charge pump, it is characterised in that including：
First electric capacity and the second electric capacity, one end of first electric capacity receive the first clock signal, one end of second electric capacity
Receive second clock signal；
Clock signal generating module, the clock signal generating module is risen to the 3rd clock signal and the 4th clock signal
Pressure, the 5th clock signal and the 6th clock signal are generated with correspondence；First clock signal, the second clock signal, institute
State the 3rd clock signal and the 4th clock signal is non-overlapping；
The drain terminal of first NMOS tube and the second NMOS tube, the drain terminal of first NMOS tube and second NMOS tube respectively with electricity
The input voltage of lotus pump provides end and is connected；
3rd NMOS tube, the drain terminal of the 3rd NMOS tube is connected with the source of first NMOS tube, the 3rd NMOS tube
Grid end receive the 6th clock signal, have between the drain terminal of the 3rd NMOS tube and the source of first NMOS tube
First node, the first node is connected with the other end of first electric capacity and the grid end of second NMOS tube respectively；
4th NMOS tube, the drain terminal of the 4th NMOS tube is connected with the source of second NMOS tube, the 4th NMOS tube
Grid end receive the 5th clock signal, have between the drain terminal of the 4th NMOS tube and the source of second NMOS tube
Section Point, the Section Point is connected with the other end of second electric capacity and the grid end of first NMOS tube respectively, institute
State the source of the 4th NMOS tube and output end of the source of the 3rd NMOS tube as the charge pump.
2. charge pump according to claim 1, it is characterised in that the clock signal generating module includes：
5th NMOS tube, the drain terminal of the 5th NMOS tube is connected with power supply；
6th NMOS tube, the drain terminal of the 6th NMOS tube is connected with the power supply；
3rd electric capacity, one end of the 3rd electric capacity receives the 4th clock signal；
First PMOS, the source of first PMOS is connected with the source of the 5th NMOS tube, first PMOS
Source and the 5th NMOS tube source between there is the 3rd node, the 3rd node is another with the 3rd electric capacity
End is connected；
4th electric capacity, one end of the 4th electric capacity receives the 3rd clock signal；
Second PMOS, the grid end of second PMOS is connected with the 3rd node, the source of second PMOS with
The source of 6th NMOS tube is connected, and has the between the source of the source of second PMOS and the 6th NMOS tube
Four nodes, the fourth node is connected with the other end of the 4th electric capacity and the grid end of first PMOS respectively；
7th NMOS tube, the grid end of the 7th NMOS tube receives the 3rd clock signal, the source of the 7th NMOS tube
Ground connection, the drain terminal of the 7th NMOS tube is connected with the drain terminal of first PMOS, the drain terminal of the 7th NMOS tube and institute
The drain terminal for stating the first PMOS exports the 5th clock signal；
8th NMOS tube, the grid end of the 8th NMOS tube receives the 4th clock signal, the source of the 8th NMOS tube
Ground connection, the drain terminal of the 8th NMOS tube is connected with the drain terminal of second PMOS, the drain terminal of the 8th NMOS tube and institute
The drain terminal for stating the second PMOS exports the 6th clock signal.
3. charge pump according to claim 2, it is characterised in that the 5th NMOS tube and the 6th NMOS tube are low
Threshold value high pressure NMOS pipe.
4. charge pump according to claim 2, it is characterised in that first PMOS and second PMOS are height
Press PMOS.
5. charge pump according to claim 2, it is characterised in that the 7th NMOS tube and the 8th NMOS tube are height
Press NMOS tube.
6. charge pump according to claim 2, it is characterised in that the clock signal generating module also includes：
First drive module, the input of first drive module receives the 3rd clock signal, the first driving mould
The power end of block is connected with the power supply, the output end of first drive module and the 4th electric capacity and the 7th NMOS
The grid end of pipe is connected；
Second drive module, the input of second drive module receives the 4th clock signal, the second driving mould
The power end of block is connected with the power supply, the output end of second drive module and the 3rd electric capacity and the 8th NMOS
The grid end of pipe is connected.
7. charge pump according to claim 6, it is characterised in that first drive module includes：
First phase inverter, the power end of first phase inverter is connected with the power supply, the input termination of first phase inverter
The 3rd clock signal is received, first phase inverter carries out anti-phase processing to the 3rd clock signal；
Second phase inverter, the power end of second phase inverter is connected with the power supply, the input termination of second phase inverter
The 3rd clock signal after anti-phase processing is received, second phase inverter carries out anti-to the 3rd clock signal after the anti-phase processing
Phase processor, the output end of second phase inverter as first drive module output end.
8. charge pump according to claim 6, it is characterised in that second drive module includes：
3rd phase inverter, the power end of the 3rd phase inverter is connected with the power supply, the input termination of the 3rd phase inverter
The 4th clock signal is received, the 3rd phase inverter carries out anti-phase processing to the 4th clock signal；
4th phase inverter, the power end of the 4th phase inverter is connected with the power supply, the input termination of the 4th phase inverter
The 4th clock signal after anti-phase processing is received, the 4th phase inverter carries out anti-to the 4th clock signal after the anti-phase processing
Phase processor, the output end of the 4th phase inverter as second drive module output end.
9. charge pump according to claim 1, it is characterised in that also include：
3rd drive module, the input of the 3rd drive module receives first clock signal, the 3rd driving mould
The power end of block is connected with power supply, and the output end of the 3rd drive module is connected with one end of first electric capacity；
4th drive module, the input of the 4th drive module receives the second clock signal, the 4 wheel driven dynamic model
The power end of block is connected with the power supply, and the output end of the 4th drive module is connected with one end of second electric capacity.
10. a kind of charge pump circuit, it is characterised in that including the charge pump according to any one of claim 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621468106.5U CN206442294U (en) | 2016-12-29 | 2016-12-29 | A kind of charge pump and charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621468106.5U CN206442294U (en) | 2016-12-29 | 2016-12-29 | A kind of charge pump and charge pump circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206442294U true CN206442294U (en) | 2017-08-25 |
Family
ID=59643480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621468106.5U Withdrawn - After Issue CN206442294U (en) | 2016-12-29 | 2016-12-29 | A kind of charge pump and charge pump circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206442294U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106787690A (en) * | 2016-12-29 | 2017-05-31 | 北京兆易创新科技股份有限公司 | A kind of charge pump and charge pump circuit |
| CN110022059A (en) * | 2017-12-20 | 2019-07-16 | 美光科技公司 | Electronic device and its operating method |
| CN111509973A (en) * | 2020-05-15 | 2020-08-07 | 中南民族大学 | Charge pump capable of reducing output voltage ripple |
| US11088617B2 (en) | 2017-12-20 | 2021-08-10 | Micron Technology, Inc. | Electronic device with an output voltage booster mechanism |
-
2016
- 2016-12-29 CN CN201621468106.5U patent/CN206442294U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106787690A (en) * | 2016-12-29 | 2017-05-31 | 北京兆易创新科技股份有限公司 | A kind of charge pump and charge pump circuit |
| CN106787690B (en) * | 2016-12-29 | 2023-09-29 | 兆易创新科技集团股份有限公司 | Charge pump and charge pump circuit |
| CN110022059A (en) * | 2017-12-20 | 2019-07-16 | 美光科技公司 | Electronic device and its operating method |
| US11088617B2 (en) | 2017-12-20 | 2021-08-10 | Micron Technology, Inc. | Electronic device with an output voltage booster mechanism |
| CN111509973A (en) * | 2020-05-15 | 2020-08-07 | 中南民族大学 | Charge pump capable of reducing output voltage ripple |
| CN111509973B (en) * | 2020-05-15 | 2022-04-19 | 中南民族大学 | Charge pump capable of reducing output voltage ripple |
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| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 12th Floor, Block A, Tiangong Building, Science and Technology University, No. 30 Xueyuan Road, Haidian District, Beijing, 100083 Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |
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Granted publication date: 20170825 Effective date of abandoning: 20230929 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20170825 Effective date of abandoning: 20230929 |