CN206378852U - A kind of Multifunctional test equipment - Google Patents
A kind of Multifunctional test equipment Download PDFInfo
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- CN206378852U CN206378852U CN201720018918.8U CN201720018918U CN206378852U CN 206378852 U CN206378852 U CN 206378852U CN 201720018918 U CN201720018918 U CN 201720018918U CN 206378852 U CN206378852 U CN 206378852U
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Abstract
Include multifunctional testing plate the utility model discloses a kind of Multifunctional test equipment, multifunctional testing plate includes two POWERPC processors, data processing FPGA, control FPGA, the Ti single-chip microcomputers of temperature voltage controller, PCIE exchange chip, one piece of norflash and 2G DDR2, and two POWERPC processors are respectively processor 1 and processor 2.The utility model can test the relevant interface (Srio of Board Under Test, PCIE exchange chips, GTX, Serdes, I2C, GPIO) transmission data it is whether correct, so that it is determined that those interface transmission datas of the development board are problematic, it can be malfunctioned with that tunnel data transport of precise positioning board, board positioning debugging efficiency is provided significantly.
Description
Technical field
The utility model is related to a kind of test equipment, specifically a kind of Multifunctional test equipment.
Background technology
As Informatization Development is more and more faster, the board of data processing used in everyday and data control is more and more, that
With the time used it is elongated and some other the reason for, the interface transmission data of the processing data of these data processing plates is just
Problem occurs, and the data handling system wherein used is much polylith board works simultaneously, then now just occur and be
The situation of processing data of uniting error, it is necessary to which the inspection of one piece of one piece of board carrys out queueing problem, but in the process of the system development
In testing scheme often to the inspection data transmission interface of the system one, this is just to checking bringing for positioning board error
Difficulty.Many times all have to please former exploitation unit send developer to come orientation problem, this just makes positioning and exclusion plate
The efficiency of the problem of card is low, and some boards are not all got in touch with due to of the remote past or even developer, then orientation problem is imitated
Rate is just lower, because the currently used data handling system based on development board is very many, so problem above can often be met
Arrive, such case need one it is good, and efficient processing mode tackles.
The content of the invention
The purpose of this utility model is to provide a kind of Multifunctional test equipment, to solve what is proposed in above-mentioned background technology
Problem.
To achieve the above object, the utility model provides following technical scheme：
A kind of Multifunctional test equipment, including multifunctional testing plate, multifunctional testing plate include two POWERPC processing
Device, data processing FPGA, control FPGA, Ti single-chip microcomputers, the PCIE of a temperature voltage controller exchange core
The DDR2 of piece, one piece of norflash and 2G, two POWERPC processors are respectively processor 1 and processor 2, two POWERPC
Processor and a data processing FPGA are linked together by a PCIE exchange chip, a control FPGA and processor 1
Connect together, processor 1,1000/100/10 adaptive network of processor 2 and a serial ports walk front panel there is provided with
The network and serial ports of PC are to even, processor 1, processor 2 respectively walk I2C to VPX mouthfuls of tests all the way and the I2C of board even connect
Mouthful, the Ti single-chip microcomputers of a temperature voltage controller are walked a whole plate SR and resetted to front panel for user, one
The Ti single-chip microcomputers of temperature voltage controller control processor 1, processor 2, the clock for controlling FPGA, PCIE exchange chip in addition
Configuration and temperature management and control, a control FPGA control processor 1 access norflash, control processor 1, data processing FPGA,
The reset function of PCIE exchange chips, a data processing FPGA be responsible for Multipexer SRIO, PCIE exchange chip, GTX,
SERDES, GPIO passage carry out data transmission test by VPX interfaces and Board Under Test.
It is used as further program of the utility model：PC with the front panel network interface connection of multifunctional testing plate by sending
Networking command data are on multifunctional testing plate, and it is to test a certain special interface that processor 1, which is resolved to, is handed over first by PCIE
The BAR0 spaces that chip bus accesses data processing FPGA are changed, the register for configuring corresponding interface channel enables corresponding interface
The data transfer of data channel enable, be direct configuration processor 1, the register of processor 2 enables I2C interface modules
, processor 1 is sent on the FPGA analog interface passages that the data to data that fixed position is specified on DDR is handled by DMA
On PCIE exchange chip address spaces, data processing FPGA is connected to the data channel after the data VPX mouthfuls and is sent to Board Under Test
On the interface being mated with, Board Under Test is connected to the data being connected to after the data back to multifunctional testing plate, multifunctional testing
The source data that plate is connected to after the data with sending before is contrasted.
It is used as further program of the utility model：The a certain special interface can for SRIO, PCIE exchange chip,
GTX、SERDES、I2C、GPIO。
It is used as the utility model further scheme：The complete preprocessor 1 of data test of a certain special interface will
Test result is sent to PC ends by network, and test result is shown on interface by PC ends notifies user.
Compared with prior art, the beneficial effects of the utility model are：The utility model can test the correlation of Board Under Test
Whether interface (Srio, PCIE exchange chip, GTX, Serdes, I2C, GPIO) transmission data are correct, so that it is determined that the exploitation
Those interface transmission datas of plate are problematic, can be malfunctioned with that tunnel data transport of precise positioning board, plate is provided significantly
Locking position debugging efficiency.
Brief description of the drawings
Fig. 1 is the theory diagram of multifunctional testing plate in Multifunctional test equipment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belongs to the scope of the utility model protection.
Referring to Fig. 1, in the utility model embodiment, a kind of Multifunctional test equipment, including multifunctional testing plate, many work(
Energy test board includes two POWERPC processors, data processing FPGA, control FPGA, a temperature voltage control
The Ti single-chip microcomputers of device, PCIE exchange chip, one piece of norflash and 2G DDR2, two POWERPC processors are respectively
Processor 1 and processor 2, two POWERPC processors and a data processing FPGA are connected by a PCIE exchange chip
Together, a control FPGA connects together with processor 1, processor 1, a 1000/100/10 adaptive net of processor 2
Network and a serial ports walk front panel there is provided the network and serial ports with PC to even, processor 1, processor 2 are respectively walked I2C all the way and arrived
VPX mouthfuls of tests are walked a whole plate SR and arrived to the I2C interfaces of the board connected, the Ti single-chip microcomputers of a temperature voltage controller
Front panel resets for user, and the Ti single-chip microcomputers of one temperature voltage controller control processor 1, processor 2, control in addition
The clock configuration and temperature management and control of FPGA, PCIE exchange chip processed, a control FPGA control processor 1 access norflash,
The reset function of control processor 1, data processing FPGA, PCIE exchange chip, a data processing FPGA is responsible for Multipexer
SRIO, PCIE exchange chip, GTX, SERDES, GPIO passage carry out data transmission test by VPX interfaces and Board Under Test.
PC with the front panel network interface connection of multifunctional testing plate by sending networking command data to multifunctional testing plate
On, it is to test a certain special interface that processor 1, which is resolved to, passes through PCIE exchange chip bus access data processings FPGA first
BAR0 spaces, the data transfer for the data channel that the register for configuring corresponding interface channel enables corresponding interface enables,
All I2C passages that processor 2 goes to VPX mouthfuls are direct configuration processors 1, and the register of processor 2 enables I2C interface moulds
Block, processor 1 is sent on the FPGA analog interface passages that the data to data that fixed position is specified on DDR is handled by DMA
On PCIE exchange chip address spaces, data processing FPGA is connected to the data channel after the data VPX mouthfuls and is sent to Board Under Test
On the interface being mated with, Board Under Test is connected to the data being connected to after the data back to multifunctional testing plate, multifunctional testing
The source data that plate is connected to after the data with sending before is contrasted.The a certain special interface can exchange for SRIO, PCIE
Chip, GTX, SERDES, I2C, GPIO.The complete preprocessor 1 of data test of a certain special interface passes through test result
Network is sent to PC ends, and test result is shown on interface by PC ends notifies user.
It is obvious to a person skilled in the art that the utility model is not limited to the details of above-mentioned one exemplary embodiment, and
And in the case of without departing substantially from spirit or essential attributes of the present utility model, can realize that this practicality is new in other specific forms
Type.Therefore, no matter from the point of view of which point, embodiment all should be regarded as exemplary, and is nonrestrictive, this practicality is new
The scope of type limits by appended claims rather than described above, it is intended that the equivalency fallen in claim is contained
All changes in justice and scope are included in the utility model.Any reference in claim should not be considered as limitation
Involved claim.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped
Containing an independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art should
Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
It may be appreciated other embodiment.
Claims (4)
1. a kind of Multifunctional test equipment, including multifunctional testing plate, multifunctional testing plate include two POWERPC processors,
One data processing FPGA, control FPGA, the Ti single-chip microcomputers of temperature voltage controller, PCIE exchange chip,
One piece of norflash and 2G DDR2, two POWERPC processors are respectively processor 1 and processor 2, it is characterised in that two
Individual POWERPC processors and a data processing FPGA are linked together by a PCIE exchange chip, a control FPGA
Connected together with processor 1, before processor 1,1000/100/10 adaptive network of processor 2 and a serial ports are walked
Plate, processor 1, processor 2 respectively walk I2C interface of I2C to the VPX mouthfuls of tests all the way to board even, a temperature voltage control
The Ti single-chip microcomputers of device are walked a SR and resetted to front panel for user, the Ti single-chip microcomputers of one temperature voltage controller
Processor 1, processor 2 are controlled in addition, control the clock configuration and temperature management and control of FPGA, PCIE exchange chip, a control
The access norflash of FPGA control processors 1, control processor 1, the reset function of data processing FPGA, PCIE exchange chip,
One data processing FPGA is responsible for Multipexer SRIO, PCIE exchange chip, GTX, SERDES, GPIO passage and passes through VPX interfaces
Carry out data transmission test with Board Under Test.
2. Multifunctional test equipment according to claim 1, it is characterised in that PC by with before multifunctional testing plate
Panel network interface connection sends networking command data to multifunctional testing plate, and processor 1 tests a certain special interface, passes through first
PCIE exchange chip bus access data processings FPGA BAR0 spaces, the register for configuring corresponding interface channel enables correspondence
The data transfer of data channel of interface enable, the register of processor 2 enables I2C interface modules, and processor 1 passes through
DMA is with sending the PCIE exchange chips on the FPGA analog interface passages for the data to data processing that fixed position is specified on DDR
Spatially, data processing FPGA is connected to the data channel after the data VPX mouthfuls and is sent to the interface that Board Under Test is mated with for location
On, Board Under Test is connected to the data being connected to after the data back to multifunctional testing plate.
3. Multifunctional test equipment according to claim 2, it is characterised in that a certain special interface can be
SRIO, PCIE exchange chip, GTX, SERDES, I2C, GPIO.
4. Multifunctional test equipment according to claim 2, it is characterised in that the data test of a certain special interface
Test result is sent to PC ends by complete preprocessor 1 by network, and test result is shown on interface by PC ends notifies user.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720018918.8U CN206378852U (en) | 2017-01-09 | 2017-01-09 | A kind of Multifunctional test equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720018918.8U CN206378852U (en) | 2017-01-09 | 2017-01-09 | A kind of Multifunctional test equipment |
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| CN206378852U true CN206378852U (en) | 2017-08-04 |
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| CN201720018918.8U Active CN206378852U (en) | 2017-01-09 | 2017-01-09 | A kind of Multifunctional test equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112272130A (en) * | 2020-09-25 | 2021-01-26 | 杭州加速科技有限公司 | Communication bus system of semiconductor tester |
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2017
- 2017-01-09 CN CN201720018918.8U patent/CN206378852U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112272130A (en) * | 2020-09-25 | 2021-01-26 | 杭州加速科技有限公司 | Communication bus system of semiconductor tester |
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