CN206365079U - The LED drive chip and circuit of a kind of compatible lead and trail edge light modulator - Google Patents
The LED drive chip and circuit of a kind of compatible lead and trail edge light modulator Download PDFInfo
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- CN206365079U CN206365079U CN201621333414.7U CN201621333414U CN206365079U CN 206365079 U CN206365079 U CN 206365079U CN 201621333414 U CN201621333414 U CN 201621333414U CN 206365079 U CN206365079 U CN 206365079U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The utility model provides the LED drive chip and circuit of a kind of compatible lead and trail edge light modulator, and LED drive chip includes the conducting angle detection circuit of the angle of flow of detection light modulator；Sample and keep the voltage peak sampling hold circuit of the peak value of the output sampled voltage；Detect the light modulator type detecting circuit of the cut type of light modulator；Confirm that the light modulator type of the cut type of the light modulator confirms circuit；Export the constant-current control circuit of a constant current switch clock signal；Export the switching logic of a switching signal；3rd phase inverter；And the drive module of driving peripheral circuit.The utility model so that LED dodges problem caused by avoiding divider resistance interference, and need not reduce system cost simultaneously using peripheral divider resistance.In addition, for different voltage applications and topological structure, without the resistance for redesigning divider resistance, therefore suitable for various circuit topologies and application, without redesign system for this.
Description
Technical field
The utility model is related to electronic technology field, more particularly to a kind of LED of compatible lead and trail edge light modulator drives
Chip and circuit.
Background technology
LED has the advantages that luminous efficiency height, service life length, stability are good for comparing traditional lighting light fixture.In order to
Accelerate LED in the popularization of lighting field, market demands realize LED on the basis of traditional illumination system infrastructure is not changed
The direct replacement of lamp and conventional lamp.
For dimmer application, the light modulator used in traditional lighting is leading edge dimmer and trailing edge dimmer, and both cut
Phase mode and the required condition of application are different.Wherein leading edge dimmer is controllable silicon dimmer, is dimmed when being used for LED
When, the input current for flowing through controllable silicon dimmer have to be larger than its holding electric current, and otherwise light modulator will be unable to keep normally-open
State, causes LED to dodge.Therefore LED drive circuit needs the special mode of operation for setting and being applied for leading edge dimmer, passes through
Detecting and adjusting input current ensures leading edge dimmer steady operation.And trailing edge dimmer is different because of the principle of cut, and it is not required to
Input current is detected and adjusted, so needing to switch to the mode of operation applied for trailing edge dimmer.Light modulator
LED brightness is determined by changing the angle of flow to AC cuts.Therefore LED driver needs to detect leading after light modulator cut
Current flow angle and the dim signal adjustment output current for being converted to chip internal.
As shown in Figure 1 be existing compatible lead and trail edge light modulator LED drive circuit, including LED drive chip 1 with
And by light modulator 21 ', rectification circuit 22 ', divider resistance Rdiv0 ' and Rdiv1 ', transformer T0 ', sustained diode 0 ', power
Metal-oxide-semiconductor M0 ' and sampling resistor Rcs ' compositions peripheral circuit 2.Wherein, divider resistance Rdiv0 ' and Rdiv1 ' are to busbar voltage
Vbus ' partial pressures obtain the sampled voltage Vdiv ' of bus.In LED drive chip, the low pass being made up of resistance Rf ' and electric capacity Cf '
Wave filter is filtered sampling to Vdiv '.The sampled voltage that low pass filter is obtained is raised and obtained by fixed voltage source Vio '
Vf′.Vdiv ' and Vf ' is compared by comparator 11 '.In trailing edge dimmer application, as shown in Fig. 2 working as busbar voltage
Vbus ' with AC ' sine rise when, due to Vbus ' frequencies are smaller can be completely by low pass filter, filter capacitor Cf's ' is upper
Polar plate voltage follows Vdiv '.When after light modulator 21 ' along during cut, busbar voltage Vbus ' rapid decreases, filter capacitor Cf's ' is upper
Pole plate slowly discharges, and its voltage is more than Vdiv '.Therefore within the whole busbar voltage cycle, after being raised through fixed voltage source Vio '
Vf ' be consistently higher than Vdiv ', the output low level of comparator 11 '.Rest-set flip-flop 13 ' is reset in chip power up phase, now puts
Position end is set to low level by comparator 11 ', and output leadmode ' remains low level, and mark now for rear edge adjust by light modulator 21 '
Light device.When detecting trailing edge dimmer, leadmode '=0 shields input current adjusting module 14 '.
Ahead of the curve in dimmer applications, as shown in figure 3, at the end of the cut of the forward position of light modulator 21 ', busbar voltage Vbus '
Rapid increase, by the filter action of resistance Rf ' and electric capacity Cf ' low pass filter constituted so that Cf ' top crown voltage will not
Vdiv ' quickly is followed, can only slowly charge rising.And now Vdiv ' rapid increases and more than Vf ', the output of comparator 11 ' is high
Level, it is that now light modulator 21 ' is leading edge dimmer to high level mark that rest-set flip-flop 13 ', which is set output leadmode ',.Work as inspection
When measuring light modulator 21 ' for leading edge dimmer, leadmode '=1 enables input current adjusting module 14 ', so that examinations
Ensure its holding electric current for being more than controllable silicon with adjustment system input current.Light modulator 21 ' is adopted to the angle of flow of AC ' input cuts
Sample is also by divider resistance Rdiv0 ' as shown in Figure 1 and Rdiv1 ' realizations.Partial pressure sampled signal Vdiv ' and internal reference base
Quasi- vref ' compares output square wave by comparator 12 '.When Vdiv ' is more than vref ', it is believed that light modulator 21 ' turns on comparator
12 ' output high level, the shut-off output low level of comparator 12 ' of light modulator 21 ' is thought when Vdiv ' is less than vref '.Light modulator class
Type detect signal leadmode ' and reflection the angle of flow square-wave signal triac as constant-current control module 15 ' input signal,
Participate in light modulation and current constant control.
The major defect of the LED drive circuit of above-mentioned compatible lead and trail edge light modulator is：To light modulator cut type
Detection with the angle of flow is needed by periphery divider resistance Rdiv0 ' and Rdiv1 ' realizations.This not only adds system cost, and
And being easily disturbed because divider resistance value is larger causes LED to be dodged.In addition, for different voltage applications and topological structure,
Need to redesign divider resistance resistance, so as to add the complexity of system design.
Utility model content
For above-mentioned the deficiencies in the prior art, the utility model provides a kind of improved compatible lead and trail edge light modulator
LED drive chip and circuit, it need not be using peripheral divider resistance, so that LED dodges problem caused by avoiding resistance interference
And system cost is reduced simultaneously, and various circuit topologies and application are applied to the detection of light modulator type and the angle of flow,
System need not be redesigned for this.
To achieve these goals, on the one hand the utility model provides a kind of LED drives of compatible lead and trail edge light modulator
Dynamic chip, it is characterised in that including：
One is used to be adjusted according to an output sampled voltage, an internal reference voltage and the maximum ON time signal detection of a switch
The conducting angle detection circuit of the angle of flow of light device, its first input end connects an output voltage sampling end, the connection of the second input
One internal reference voltage end, the maximum ON time signal end of the switch of the 3rd input connection one；
One is used to sample and keeps the voltage peak sampling hold circuit of the peak value of the output sampled voltage, its input
Connect the output voltage sampling end；
One be used for detect light modulator cut type light modulator type detecting circuit, its first input end connection described in lead
First output end of logical angle detection circuit, its second input connects the output end of the voltage peak sampling hold circuit；
One is used to confirm that the light modulator type of the cut type of the light modulator to confirm circuit, and the connection of its input is described to adjust
The output end of light device type detecting circuit, the second output end of its clock triggering end connection conducting angle detection circuit；
One is used for the constant-current control circuit of one constant current switch clock signal of output, and its first input end connects the light modulator
Type confirms the output end of circuit, the second output end of its clock triggering end connection conducting angle detection circuit；
One is used for the switching logic of one switching signal of output, and its first input end connects the conducting angle detection circuit
The 3rd output end, the maximum ON time signal end of the second input connection switch, the 3rd input connects the constant current
The output end of circuit is controlled, output end connects the first control end of the voltage peak sampling hold circuit；
One the 3rd phase inverter, its input connects the output end of the switching logic, and output end connects the voltage
Second control end of peak sampling hold circuit；And
One drive module for driving peripheral circuit, its input connects the output end of the switching logic, defeated
Go out end connection peripheral circuit.
Further, the conducting angle detection circuit includes：
One detection resistance, its one end connection it is described conducting angle detection circuit first input end, the other end connection described in lead
First output end of logical angle detection circuit；
One comparator, its positive input terminal connects the other end of the detection resistance, and negative input end connects the angle of flow inspection
Second input of slowdown monitoring circuit, the 3rd output end of the output end connection conducting angle detection circuit；And
One second rest-set flip-flop, its reset terminal connects the output end of the comparator, and set end connects the angle of flow inspection
3rd input of slowdown monitoring circuit, the second output end of the output end connection conducting angle detection circuit.
Further, the voltage peak sampling hold circuit includes：
One first switch, its input connects the input of the voltage peak sampling hold circuit, control end connection institute
State the first control end of voltage peak sampling hold circuit；
One first sampling capacitance, its top crown connects the output end of the first switch, bottom crown ground connection；
One second switch, its input connects the output end of the first switch, and control end connects the voltage peak and adopted
Second control end of sample holding circuit, output end connects the output end of the voltage peak sampling hold circuit；And
One second sampling capacitance, its top crown connects the output end of the second switch, bottom crown ground connection；
Further, the light modulator type detecting circuit includes a hysteresis comparator, and the connection of its positive input terminal is described to adjust
The first input end of light device type detecting circuit, negative input end connects the first input end of the light modulator type detecting circuit,
Output end connects the output end of the light modulator type detecting circuit.
Further, the light modulator type confirms that circuit includes：
One first rest-set flip-flop, its set end connects the input that the light modulator type confirms circuit；
One first d type flip flop, its set end connects the output end of first rest-set flip-flop, and the connection of clock triggering end is described
Light modulator type confirms the clock triggering end of circuit；
One second d type flip flop, its set end connects the output end of first d type flip flop, and the connection of clock triggering end is described
Light modulator type confirms the clock triggering end of circuit；
One first rising edge pulse generation circuit, its input connects the output end of first d type flip flop；
One second rising edge pulse generation circuit, its input connects the output end of second d type flip flop；
One first nor gate, its first input end connects the output end of the first rising edge pulse generation circuit, second
Input connects the output end of the second rising edge pulse generation circuit；
One second phase inverter, its input connects the output end of first nor gate, and output end connects the first RS
The reset terminal of trigger；
One first NAND gate, its first input end connects the output end of first rest-set flip-flop, the connection of the second input
The output end of first d type flip flop, the 3rd input connects the output end of second d type flip flop；And
One first phase inverter, its input connects the output end of first NAND gate, and output end connects the light modulator
Type confirms the output end of circuit.
Further, the switching logic includes：
One second nor gate, its first input end connects the first input end of the switching logic, the second input
Connect the second input of the switching logic；
One the 4th phase inverter, its input connects the output end of second nor gate；And
One second NAND gate, its first input end connects the 3rd input of the switching logic, the second input
The output end of the 4th phase inverter is connected, output end connects the output end of the switching logic.
Further, the first rising edge pulse generation circuit includes：
One the 5th phase inverter, its input connects the input of the first rising edge pulse generation circuit；
One first Postponement module, its input connects the output end of the 5th phase inverter；
One the 3rd NAND gate, its first input end connects the output end of first Postponement module, the connection of the second input
The input of 5th phase inverter；And
One hex inverter, its input is connected in the output end of the 3rd NAND gate, output end connection described first
Rise the output end along pulse-generating circuit.
Further, the second rising edge pulse generation circuit includes：
One the 7th phase inverter, its input connects the input of the second rising edge pulse generation circuit；
One second Postponement module, its input connects the output end of the 7th phase inverter；
One the 4th NAND gate, its first input end connects the output end of second Postponement module, the connection of the second input
The input of 7th phase inverter；And
One the 8th phase inverter, its input is connected in the output end of the 4th NAND gate, output end connection described second
Rise the output end along pulse-generating circuit.
On the other hand the utility model provides a kind of LED drive circuit of compatible lead and trail edge light modulator, and it includes one
LED drive chip and a peripheral circuit, it is characterised in that the LED drive chip is any one of preceding claims 1-8 institutes
The LED drive chip for the compatible lead and trail edge light modulator stated.
Further, the peripheral circuit includes：
One AC power；
One light modulator, its input connects the positive output end of the AC power；
One rectification circuit, its positive input terminal connects the output end of the light modulator, and negative input end connects the AC power
Negative output terminal, negative output terminal ground connection；
One transformer, its primary side different name end connects the positive output end of the rectification circuit, and secondary different name end connects a LED and born
The negative pole of load；
One power MOS pipe, the primary side Same Name of Ends of its connection transformer that drains, source electrode connects the output sampled voltage
End, grid connects the output end of the drive module；
One sampling resistor, its one end connects the source electrode of the power MOS pipe, other end ground connection；And
One fly-wheel diode, its positive pole connects the secondary Same Name of Ends of the transformer, and negative pole connects the sun of the LED load
Pole.
By using above-mentioned technical proposal, the utility model has the advantages that：
LED drive chip of the present utility model and circuit are in use, need not be using peripheral divider resistance, so as to avoid
LED dodges problem caused by divider resistance interference, and reduces system cost simultaneously.In addition, for different voltage apply and
Topological structure, without the resistance for redesigning divider resistance, therefore inspection of the utility model to light modulator type and the angle of flow
Survey and be applied to various circuit topologies and application, without redesign system for this.
Brief description of the drawings
Fig. 1 is the circuit theory diagrams of the LED drive circuit of existing compatible lead and trail edge light modulator；
Fig. 2 is the key node waveform in existing LED drive circuit ahead of the curve dimmer applications；
Fig. 3 is key node waveform of the existing LED drive circuit in trailing edge dimmer application；
Fig. 4 is the circuit theory diagrams of the LED drive circuit of compatible lead and trail edge light modulator of the present utility model；
Fig. 5 A be the utility model in the first rising edge pulse generation circuit circuit theory diagrams；
Fig. 5 B be the utility model in the second rising edge pulse generation circuit circuit theory diagrams；
Fig. 6 is the key node waveform of the utility model in the application.
Embodiment
Below according to accompanying drawing 4-6, preferred embodiment of the present utility model is provided, and is described in detail, is enabled preferably
Understand function of the present utility model, feature.
Fig. 4 shows the LED drive circuit of the compatible lead and trail edge light modulator of the utility model, and it is by of the present utility model
The LED drive chip 1 and peripheral circuit 2 of compatible lead and trail edge light modulator are constituted.As shown in figure 4, LED of the present utility model drives
Dynamic chip 1 includes constant-current control circuit 19, drive module DRV, hysteresis comparator 13, comparator 11, rest-set flip-flop 14, RS triggerings
Device 12, d type flip flop 15, d type flip flop 16, the first NAND gate NAND1, the second NAND gate NAND2, the first nor gate NOR1, second
Nor gate NOR2, the first phase inverter INV1, the second phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4, on first
Rise along pulse-generating circuit 17, the second rising edge pulse generation circuit 18, first switch S1, second switch S2, detection resistance
Rcsin, the first sampling capacitance C0 and the second sampling capacitance C1.Peripheral circuit 2 includes AC power AC, light modulator 21 and (for example may be used
Control silicon light modulator), rectification circuit 22, transformer T0, sustained diode 0, sampling resistor Rcs and power MOS pipe M0.Wherein, than
Conducting angle detection circuit is constituted compared with device 11, Rcsin and rest-set flip-flop 12, the circuit exports sampled voltage CS to judge by detection
Whether bus Vbus is high, so that it is determined that the angle of flow of light modulator 21.C0, C1, S1 and S2 constitute voltage peak sampling and keep electricity
Road, the circuit is used for CS peak values of sampling and keep when M0 is turned on.Hysteresis comparator 13 constitutes light modulator type detecting circuit, should
Circuit is used for the CS peakedness ratios for maintaining the CS peak values during current M0 conductings with being sampled during once being turned on before M0 compared with judgement
Bus Vbus is mutated with the presence or absence of rising edge, so as to judge the cut type of light modulator 21.D type flip flop 15, d type flip flop 16, RS
Trigger 14, NAND1, the first phase inverter INV1, the first rising edge pulse generation circuit 17, the second rising edge pulse generation circuit
18th, NOR1 and the second phase inverter INV2 constitutes light modulator type confirmation circuit, and the circuit is mainly responsible for completing 3 mothers of accumulative detection
Line Vbus rising edge jumping phenomenons, output leadmod is high level and locked that the purpose is to the detection for strengthening light modulator 21 is reliable
Property, need to be consecutively detected 3 times just confirm controllable silicon dimmer cut type.NOR2, the 4th phase inverter INV4 and NAND2 are constituted
Switching logic, in M0 turn-on cycles, if CS is less than vref always, by tonmax shut-off switch (i.e. power tubes
M0).DRV is responsible for the power MOS pipe M0 of driving periphery.3rd phase inverter INV3 is used to coordinate the inverted logic for producing swon to power
Press peak sampling hold circuit.Constant-current control circuit 19 is responsible for realizing output constant current control.
In the embodiment shown in fig. 4, the specific annexation between each part is as follows：
AC power AC positive output end is connected with the input of light modulator 21, and its negative output terminal is negative with rectification circuit 22
Input is connected.
The input of light modulator 21 is connected with the positive output end in AC sources, its output end and the positive input terminal phase of rectification circuit 22
Even.
The positive input terminal of rectification circuit 22 is connected with the output end of light modulator 21, its negative input end and the negative output terminal in AC sources
It is connected；The positive output end of rectification circuit 22 is connected with the different name end of transformer T0 primary sides, its negative output terminal ground connection.
The first input end of constant-current control circuit 19 is connected with the first phase inverter INV1 output end, to receive light modulator class
Type detects signal leadmode, and its second input is connected with the output end of rest-set flip-flop 12, to receive a dimmer conduction angle
Signal triacb, its output end is connected with NAND gate NAND2 first input end, to export a constant current switch clock signal ton.
NAND gate NAND2 first input end is connected with the output end of constant-current control circuit 19, its second input and
Four phase inverter INV4 output end is connected, its output end and the input of drive module DRV input and the 3rd phase inverter INV3
End and first switch S1 control end are connected, to export a switching signal swon.
Drive module DRV input is connected with NAND gate NAND2 output end, and its output end is with power MOS pipe M0's
Grid is connected, to export a drive signal drv.
3rd phase inverter INV3 input is connected with NAND gate NAND2 output end to receive signal swon, and it is exported
End is related to second switch S2 control end, and exports a switching signal swonb.
First switch S1 input is connected with sampling resistor Rcs one end (i.e. output voltage sampling end), to receive one
Sampled voltage CS is exported, its output end is connected with the first sampling capacitance C0 top crown.First switch S1 is by NAND gate NAND2's
Output signal swon is controlled, when swon is high level, and otherwise first switch S1 conductings turn off.
First sampling capacitance C0 top crown is connected with first switch S1 output end, its bottom crown ground connection.
Second switch S2 input is connected with the first sampling capacitance C0 top crown, output end and the second sampling capacitance C1
The top crown of (C1 capacitance is much smaller than C0 capacitance) is connected.Output signals of the second switch S2 by the 3rd phase inverter INV3
Swonb is controlled, when swonb is high level, and otherwise second switch S2 conductings turn off.
Detection resistance Rcsin one end is connected with sampling resistor Rcs one end (i.e. output voltage sampling end), the other end with
The positive input terminal of hysteresis comparator 13 is connected.
The positive input terminal of hysteresis comparator 13 is connected with the positive input terminal of comparator 11, its negative input end and the second sampling electricity
The top crown for holding C1 is connected, and its output end is connected with the set end of rest-set flip-flop 14.
The set end of rest-set flip-flop 14 is connected with the output end of hysteresis comparator 13, its reset terminal and the second phase inverter INV2
Output end be connected, its output end is connected with the set end of d type flip flop 15.
The set end of d type flip flop 15 is connected with the output end of rest-set flip-flop 14 to receive signal crs1, its clock triggering end
It is connected with the output end of rest-set flip-flop 12 to receive signal triacb, its output end is connected with the set end of d type flip flop 16.
The set end of d type flip flop 16 is connected with the output end of d type flip flop 15 to receive signal crs2, its clock triggering end with
The output end of rest-set flip-flop 12 is connected to receive signal triacb, and its output end is connected with NAND gate NAND1 the 3rd input.
The input of first rising edge pulse generation circuit 17 is connected to receive signal with the output end of d type flip flop 15
Crs2, its output end AND OR NOT gate NOR1 first input end are connected.
The input of second rising edge pulse generation circuit 18 is connected to receive signal with the output end of d type flip flop 16
Crs3, its output end AND OR NOT gate NOR1 the second input are connected.
Nor gate NOR1 first input end is connected with the output end of the first rising edge pulse generation circuit 17, and it is second defeated
Enter end with the output end of the second rising edge pulse generation circuit 18 to be connected, its output end and the second phase inverter INV2 input phase
Even.
Second phase inverter INV2 input AND OR NOT gate NOR1 output end is connected, its output end and rest-set flip-flop 14
Reset terminal is connected.
NAND gate NAND1 first input end is connected with the output end of rest-set flip-flop 14 to receive signal crs1, and it second
Input is connected with the output end of d type flip flop 15 to receive signal crs2, the output end phase of its 3rd input and d type flip flop 16
Even to receive signal crs3, its output end is connected with the first phase inverter INV1 input.
First phase inverter INV1 input is connected with NAND gate NAND1 output end, its output end and current constant control electricity
The first input end on road 19 is connected.
The positive input terminal of comparator 11 is connected with the positive input terminal of hysteresis comparator 13, its negative input end and an internal reference
Voltage end is connected to receive an internal reference voltage vref, and its output end is connected with the reset terminal of rest-set flip-flop 12.
The reset terminal of rest-set flip-flop 12 is connected with the output end of comparator 11 to receive signal csmin, its set end and one
The maximum ON time signal end of switch is connected, to receive the maximum ON time signal tonmax of a switch, its output end and constant current
The second input of circuit 19 is controlled to be connected.
Nor gate NOR2 first input end is connected with the output end of comparator 11 to receive signal csmin, and it is second defeated
Enter end with the maximum ON time signal end of switch to be connected, to receive switch maximum ON time signal tonmax, its output end and
4th phase inverter INV4 input is connected.
4th phase inverter INV4 input AND OR NOT gate NOR2 output end is connected, its output end and NAND gate NAND2
The second input be connected.
Transformer T0 primary side different name end is connected with the positive output end of rectification circuit 22, its primary side Same Name of Ends and power MOS
Pipe M0 drain terminal is connected.Its secondary Same Name of Ends is connected with the anode of sustained diode 0, the moon of its secondary different name end and LED load
Extremely it is connected.
The anode of fly-wheel diode is connected with transformer T0 secondary Same Name of Ends, and its negative electrode is connected with the anode of LED load.
Sampling resistor Rcs one end is connected with power MOS pipe M0 source, other end ground connection.
Power MOS pipe M0, its drain terminal is connected with transformer T0 primary side Same Name of Ends, and its grid end is defeated with drive module DRV's
Go out and be connected to receive drive signal drv, its source is connected with sampling resistor Rcs one end.
The circuit theory diagrams of foregoing first rising edge pulse generation circuit 17 and the first rising edge pulse generation circuit 17 point
Not as shown in Figure 5 A and 5B, wherein, the first rising edge pulse generation circuit 17 includes：One the 5th phase inverter IV5, its input connects
Connect the output end of d type flip flop 15；One first Postponement module 171, its input connects the 5th phase inverter INV5 output end；One
Three NAND gate NAND3, its first input end connects the output end of the first Postponement module 171, and the connection the 5th of the second input is anti-phase
Device INV5 input；And a hex inverter INV6, its input connects the 3rd NAND gate NAND3 output end, output
The first nor gate NOR1 of end connection first input end.Second rising edge pulse generation circuit 18 includes：One the 7th phase inverter
INV7, the output end of its input connection institute d type flip flop 15；One second Postponement module 181, its input connects the 7th phase inverter
INV7 output end；One the 4th NAND gate NAND4, its first input end connects the output end of the second Postponement module 181, and second is defeated
Enter the 7th phase inverter INV7 of end connection input；And one the 8th phase inverter INV8, its input connects the 4th NAND gate
NAND4 output end, output end connects the first nor gate NOR1 the second input.
The operation principle of the utility model embodiment is as follows：
As shown in figure 4, CS is compared by resistance Rcsin with internal reference voltage vref, (vref value can be according to actual feelings
Condition is adjusted), when CS is less than vref, the output csmin low levels of comparator 11, if the maximum ON time set in chip 1
Interior CS is still less than vref, then rest-set flip-flop 12 is by maximum ON time signal tonmax set, and output triacb is high level.
Comparator 11 exports high level and rest-set flip-flop 12 is resetted if CS is more than vref, and output triacb is low level.If
CS is still not above vref, then it is assumed that now busbar voltage is very low in the maximum ON time that chip 1 is set, light modulation
Device 21 is off state.Vref is had been above if CS is in maximum ON time, then it is assumed that now busbar voltage is present,
Light modulator 21 is in the conduction state.By detecting the conducting and shut-off of light modulator 21 with upper type, triacb is used as light modulator
21 conducting angle signal, high level represents that light modulator 21 is turned off, and low level represents that light modulator 21 is turned on.
If during power MOS pipe M0 is turned on, CS is less than vref, and M0 must keep opening state to be led until switch maximum
Logical time signal tonmax triggerings.So just it can guarantee that when CS is consistently less than vref, tonmax can be triggered reliably to light modulation
The angle of flow of device 21 is detected.Passed through with the output signal csmin of comparator 11 and switch maximum ON time signal tonmax
Nor gate NOR2 and the 4th phase inverter INV4 is shielded to the switching sequence signal ton that constant-current control circuit 19 is exported.Only
Triggered when CS is more than verf or tomax, power MOS pipe just allows to be turned off.
As shown in figure 4, when power MOS pipe M0 is turned on, first switch S1 is also switched on, the first sampling capacitance C0 top crown
The CS voltage linears of cs1 following sampling resistance rise.After power MOS pipe M0 is turned off, first switch S1 is also switched off, and is now sampled
Electric capacity top crown cs1 is maintained at current CS voltages, i.e. peak value samplings of the first sampling capacitance C0 to CS.While second switch
S2 is turned on, and the second sampling capacitance C1 is connected with the first sampling capacitance C0, because the capacitance of electric charge redistribution and C1 is much smaller than C0
Capacitance, so C1 top crown CS2 is quickly charged to C0 top crowns CS1 voltage, so that in power tube M0 shut-offs
Afterwards during next power tube is turned off, CS peak value is sampled by C0 to be kept and is used as the negative input signal of hysteresis comparator 13.
When power MOS pipe M0 is turned on again, CS voltages are through positive input signals of the resistance Rcsin as hysteresis comparator 13, if CS
(the hysteresis voltage value can root for the magnitude of voltage of a linear rise hysteresis voltage higher than the crest voltage that previous cycle C1 is sampled
Adjusted according to situation), then the upset of hysteresis comparator 13 exports high level.After power MOS pipe M0 shut-offs, as above, new CS peak values electricity
Pressure flushes to the second sampling capacitance C1, wait the peakedness ratios of next switch periods compared with.As above by current CS and previous switch
The CS peak values in cycle are compared the peak value jumping phenomenon that purpose is to detect CS.Because switch conduction times are fixed, inductance is solid
Fixed, CS crest voltages are only relevant with the busbar voltage of input.When busbar voltage is by leading edge dimmer cut, it may appear that precipitous
Uphill process, so that CS crest voltage is undergone mutation, the circuit also just judges light modulator and cut type with this.
In order to prevent because the reason such as power network fluctuation and circuit interference causes CS crest voltages to be mutated light modulator may being caused to cut
Facies type is judged by accident, and circuit must all detect CS mutation in continuous multiple (such as 3) AC cycle busbar voltage rapid increases
The cut type detection signal leadmode=1 of light modulator 21 is just exported after signal and is locked.When forward position dimmer conduction bus electricity
Rapid increase is pressed, when the CS peak values mutation output of hysteresis comparator 13 crs is high, rest-set flip-flop 14 is set output crs1=1.
When leading edge dimmer shut-off triacb upsets are high level, the output of d type flip flop 15 crs2=1.When Crs2 upsets are high level, warp
First rising edge pulse generation circuit 17 produces reseting pulse signal.Reseting pulse signal is anti-phase by nor gate NOR1 and second
Device INV2 resets to rest-set flip-flop.Crs1 overturns as low level again.It is as above, sluggish when leading edge dimmer is once being turned on
The output crs of comparator 13 overturns as high level again, and it is high level that rest-set flip-flop 14, which is set output crs1,.Forward position is adjusted afterwards
Light device is turned off again, and triacb rising edge causes the output crs3=crs2=1, crs2=crs1=1 of d type flip flop 16.
Crs3 upsets produce reset pulse through the second rising edge pulse generation circuit 18 simultaneously, and reseting pulse signal passes through nor gate NOR1
Rest-set flip-flop is resetted with the second phase inverter INV2.Crs1 overturns as low level again.When third time leading edge dimmer is turned on,
Hysteresis comparator 13 exports crs=1, and RS has been triggered by set again, crs1=1.Now crs1=crs2=crs3=1, is passed through
NAND gate NAND1 and the first phase inverter INV1 outputs leadmode=1.Due to there is no pulse after the conducting of third time leading edge dimmer
Reset signal resets to rest-set flip-flop 14, so as to lock leadmode=1.Leadmode and the reflection angle of flow square wave
Signal triac drives as the input signal of constant-current control module, output constant current switching sequence signal ton, triggering drive module DRV
Dynamic M0 outputs constant current.
The key node waveform of the utility model in the application is as shown in fig. 6, after system electrification, leading edge dimmer is turned off
When, switch swon closes ON time work.When leading edge dimmer is turned on, busbar voltage Vbus rapid increases, now in switch
In swon high level times, CS linear rises.When CS is more than verf, the triacb upsets of conducting angle signal are adjusted for low level mark
Light device is turned on.During switch conduction, cs1 follow cs1 after CS linear rises, switch OFF keep CS crest voltage until
During next switch conduction, continue to follow CS.Cs2 is updated to the CS crest voltages of current period in switch OFF by cs1, therefore
Cs2 is the envelope of CS peak values.CS is compared with the CS peak signals cs2 sampled in previous switch periods, is more than cs2 in CS
When, crs is high level, afterwards switch OFF, and CS is less than cs2, and crs upsets are low level, therefore high level pulse letter is presented in crs
Number.Crs high level pulse triggering crs1 permanent High levels.Triacb rising edge carries out displacement behaviour to crs1, crs2, crs3
Make, crs2 is set to high level, resetted while being reset to crs1.When next dimmer conduction turns off the cycle, repeat above-mentioned
Process, crs3, which is set simultaneously to reset crs1, to be resetted.During third time dimmer conduction, crs1 is set to high level, now
Crs1=crs2=crs3=1, light modulator type detection signal leadmode=1.Because now crs2 and crs3 do not occur
Rising edge, crs1 will not be cleared reset, and leadmode keeps high level state locking.
Record above, preferred embodiment only of the present utility model is not limited to scope of the present utility model, this
Above-described embodiment of utility model can also make a variety of changes.I.e. every claims according to the present utility model application and
Simple, equivalent changes and modifications that description is made, fall within the claims of the utility model patent.
Claims (10)
1. a kind of LED drive chip of compatible lead and trail edge light modulator, it is characterised in that including：
One is used for according to an output sampled voltage, an internal reference voltage and the maximum ON time signal detection light modulator of a switch
The angle of flow conducting angle detection circuit, its first input end connect an output voltage sampling end, the second input connection one in
Portion's reference voltage terminal, the maximum ON time signal end of the switch of the 3rd input connection one；
One is used to sample and keeps the voltage peak sampling hold circuit of the peak value of the output sampled voltage, the connection of its input
The output voltage sampling end；
The light modulator type detecting circuit of the one cut type for detecting light modulator, its first input end connects the angle of flow
The first output end of circuit is detected, its second input connects the output end of the voltage peak sampling hold circuit；
One is used to confirm that the light modulator type of the cut type of the light modulator to confirm circuit, and its input connects the light modulator
The output end of type detecting circuit, the second output end of its clock triggering end connection conducting angle detection circuit；
One is used for the constant-current control circuit of one constant current switch clock signal of output, and its first input end connects the light modulator type
Confirm the output end of circuit, the second output end of its clock triggering end connection conducting angle detection circuit；
One is used for the switching logic that exports a switching signal, the of its first input end connection conducting angle detection circuit
Three output ends, the maximum ON time signal end of the second input connection switch, the 3rd input connects the current constant control
The output end of circuit, output end connects the first control end of the voltage peak sampling hold circuit；
One the 3rd phase inverter, its input connects the output end of the switching logic, and output end connects the voltage peak
Second control end of sampling hold circuit；And
One drive module for driving peripheral circuit, its input connects the output end of the switching logic, output end
Connect peripheral circuit.
2. the LED drive chip of compatible lead and trail edge light modulator according to claim 1, it is characterised in that described to lead
Logical angle detection circuit includes：
One detection resistance, the first input end of its one end connection conducting angle detection circuit, the other end connects the angle of flow
Detect the first output end of circuit；
One comparator, its positive input terminal connects the other end of the detection resistance, and negative input end connects the angle of flow detection electricity
Second input on road, the 3rd output end of the output end connection conducting angle detection circuit；And
One second rest-set flip-flop, its reset terminal connects the output end of the comparator, and set end connects the angle of flow detection electricity
3rd input on road, the second output end of the output end connection conducting angle detection circuit.
3. the LED drive chip of compatible lead and trail edge light modulator according to claim 1, it is characterised in that the electricity
Pressure peak sampling hold circuit includes：
One first switch, its input connects the input of the voltage peak sampling hold circuit, and control end connects the electricity
Press the first control end of peak sampling hold circuit；
One first sampling capacitance, its top crown connects the output end of the first switch, bottom crown ground connection；
One second switch, its input connects the output end of the first switch, and control end connects the voltage peak sampling and protected
The second control end of circuit is held, output end connects the output end of the voltage peak sampling hold circuit；And
One second sampling capacitance, its top crown connects the output end of the second switch, bottom crown ground connection.
4. the LED drive chip of compatible lead and trail edge light modulator according to claim 1, it is characterised in that the tune
Light device type detecting circuit includes a hysteresis comparator, and the first of its positive input terminal connection light modulator type detecting circuit is defeated
Enter end, negative input end connects the first input end of the light modulator type detecting circuit, and output end connects the light modulator type
Detect the output end of circuit.
5. the LED drive chip of compatible lead and trail edge light modulator according to claim 1, it is characterised in that the tune
Light device type confirms that circuit includes：
One first rest-set flip-flop, its set end connects the input that the light modulator type confirms circuit；
One first d type flip flop, its set end connects the output end of first rest-set flip-flop, and clock triggering end connects the light modulation
Device type confirms the clock triggering end of circuit；
One second d type flip flop, its set end connects the output end of first d type flip flop, and clock triggering end connects the light modulation
Device type confirms the clock triggering end of circuit；
One first rising edge pulse generation circuit, its input connects the output end of first d type flip flop；
One second rising edge pulse generation circuit, its input connects the output end of second d type flip flop；
One first nor gate, its first input end connects the output end of the first rising edge pulse generation circuit, the second input
The output end of end connection the second rising edge pulse generation circuit；
One second phase inverter, its input connects the output end of first nor gate, and output end connects the first RS triggerings
The reset terminal of device；
One first NAND gate, its first input end connects the output end of first rest-set flip-flop, and the connection of the second input is described
The output end of first d type flip flop, the 3rd input connects the output end of second d type flip flop；And
One first phase inverter, its input connects the output end of first NAND gate, and output end connects the light modulator type
Confirm the output end of circuit.
6. the LED drive chip of compatible lead and trail edge light modulator according to claim 1, it is characterised in that described to open
Closing logic circuit includes：
One second nor gate, its first input end connects the first input end of the switching logic, the connection of the second input
Second input of the switching logic；
One the 4th phase inverter, its input connects the output end of second nor gate；And
One second NAND gate, its first input end connects the 3rd input of the switching logic, the connection of the second input
The output end of 4th phase inverter, output end connects the output end of the switching logic.
7. the LED drive chip of compatible lead and trail edge light modulator according to claim 5, it is characterised in that described
One rising edge pulse generation circuit includes：
One the 5th phase inverter, its input connects the input of the first rising edge pulse generation circuit；
One first Postponement module, its input connects the output end of the 5th phase inverter；
One the 3rd NAND gate, its first input end connects the output end of first Postponement module, and the connection of the second input is described
The input of 5th phase inverter；And
One hex inverter, its input connects the output end of the 3rd NAND gate, and output end connects first rising edge
The output end of pulse-generating circuit.
8. the LED drive chip of compatible lead and trail edge light modulator according to claim 5, it is characterised in that described
Two rising edge pulse generation circuits include：
One the 7th phase inverter, its input connects the input of the second rising edge pulse generation circuit；
One second Postponement module, its input connects the output end of the 7th phase inverter；
One the 4th NAND gate, its first input end connects the output end of second Postponement module, and the connection of the second input is described
The input of 7th phase inverter；And
One the 8th phase inverter, its input connects the output end of the 4th NAND gate, and output end connects second rising edge
The output end of pulse-generating circuit.
9. a kind of LED drive circuit of compatible lead and trail edge light modulator, it includes a LED drive chip and a peripheral circuit,
Characterized in that, the LED drive chip is the compatible lead and trail edge light modulator any one of preceding claims 1-8
LED drive chip.
10. the LED drive circuit of compatible lead and trail edge light modulator according to claim 9, it is characterised in that described outer
Enclosing circuit includes：
One AC power；
One light modulator, its input connects the positive output end of the AC power；
One rectification circuit, its positive input terminal connects the output end of the light modulator, and negative input end connects the negative of the AC power
Output end, negative output terminal ground connection；
One transformer, its primary side different name end connects the positive output end of the rectification circuit, and secondary different name end connects a LED load
Negative pole；
One power MOS pipe, the primary side Same Name of Ends of its connection transformer that drains, the source electrode connection output sampled voltage end,
Grid connects the output end of the drive module；
One sampling resistor, its one end connects the source electrode of the power MOS pipe, other end ground connection；And
One fly-wheel diode, its positive pole connects the secondary Same Name of Ends of the transformer, and negative pole connects the anode of the LED load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621333414.7U CN206365079U (en) | 2016-12-06 | 2016-12-06 | The LED drive chip and circuit of a kind of compatible lead and trail edge light modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621333414.7U CN206365079U (en) | 2016-12-06 | 2016-12-06 | The LED drive chip and circuit of a kind of compatible lead and trail edge light modulator |
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| Publication Number | Publication Date |
|---|---|
| CN206365079U true CN206365079U (en) | 2017-07-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621333414.7U Withdrawn - After Issue CN206365079U (en) | 2016-12-06 | 2016-12-06 | The LED drive chip and circuit of a kind of compatible lead and trail edge light modulator |
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| Country | Link |
|---|---|
| CN (1) | CN206365079U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106385738A (en) * | 2016-12-06 | 2017-02-08 | 上海灿瑞科技股份有限公司 | LED (Light-emitting Diode) drive chip compatible with leading-edge light modulator and trailing-edge light modulator, and circuit |
| CN110035580A (en) * | 2019-04-19 | 2019-07-19 | 上海源微电子科技有限公司 | A kind of constant-current control circuit of booster type LED drive circuit and its application |
| CN110213863A (en) * | 2019-07-12 | 2019-09-06 | 贵州道森集成电路科技有限公司 | A kind of circuit structure and method of adjustment of the line regulation of LED drive chip |
| CN111262563A (en) * | 2020-03-19 | 2020-06-09 | 湖南品腾电子科技有限公司 | Large current output circuit |
-
2016
- 2016-12-06 CN CN201621333414.7U patent/CN206365079U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106385738A (en) * | 2016-12-06 | 2017-02-08 | 上海灿瑞科技股份有限公司 | LED (Light-emitting Diode) drive chip compatible with leading-edge light modulator and trailing-edge light modulator, and circuit |
| CN110035580A (en) * | 2019-04-19 | 2019-07-19 | 上海源微电子科技有限公司 | A kind of constant-current control circuit of booster type LED drive circuit and its application |
| CN110213863A (en) * | 2019-07-12 | 2019-09-06 | 贵州道森集成电路科技有限公司 | A kind of circuit structure and method of adjustment of the line regulation of LED drive chip |
| CN111262563A (en) * | 2020-03-19 | 2020-06-09 | 湖南品腾电子科技有限公司 | Large current output circuit |
| CN111262563B (en) * | 2020-03-19 | 2023-09-08 | 湖南品腾电子科技有限公司 | High-current output circuit |
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