CN206322148U

CN206322148U - How plural multiply-add operation control device based on microcontroller

Info

Publication number: CN206322148U
Application number: CN201621354875.2U
Authority: CN
Inventors: 纪晓玲
Original assignee: Yulin University
Current assignee: Yulin University
Priority date: 2016-12-12
Filing date: 2016-12-12
Publication date: 2017-07-11
Anticipated expiration: 2026-12-12

Abstract

A kind of how plural multiply-add operation control device based on microcontroller, it has the master circuit being controlled to circuit；CPLD circuit, the output end of the input termination master circuit of the circuit, the input of the output termination master circuit of the circuit；Clock circuit, the input of the output termination CPLD circuit of the circuit；Jtag circuit, the input of the output termination CPLD circuit of the circuit.The device is reasonable in design, circuit is simple, cost is relatively low, easy to control, it is adaptable to small-sized control occasion.

Description

How plural multiply-add operation control device based on microcontroller

Technical field

The utility model belongs to the device technical field of many complex operations, and in particular to based on microcontroller More plural multiply-add operation control device.

Background technology

Plural number obtains extensive practical application in electrotechnics, hydrodynamics, Theory of Vibration, wing theory.People are with multiple Number is parameter, has developed the theory of " complex function ", it can be seen that research plural number is significant.

At present, existing many plural multiply-add operations are mainly what is realized by digital signal processor, this implementation With following deficiency：Cost is higher；Circuit is complicated；High is required to user, it is necessary to take a long time and energy could be grasped； Some less application scenarios are not applied to.Microcontroller is that we commonly use, and it has low cost, and a piece of controller chip is only Several members, unlike digital signal processor is so expensive；Using extensive；Control is simple, and effector is easy to association.

The content of the invention

Technical problem to be solved in the utility model is to overcome the shortcomings of above-mentioned how plural multiply-add operation control, is provided A kind of reasonable in design, circuit is simple, cost is relatively low, the how plural multiply-add operation control dress easy to control based on microcontroller Put.

Solving the technical scheme of above-mentioned technical problem use is：

There is provided more plural as master circuit for CPLD circuit using the microcontroller of low cost due to the utility model Input；The multiply-add operation of many plural numbers is carried out using CPLD circuit, the output end of the input termination master circuit of the circuit should The input of the output termination master circuit of circuit；Using clock circuit, clock is provided for many complex operations of CPLD circuit, The input of the output termination CPLD circuit of the circuit；Using jtag circuit, the debugging in sequence of threads is carried out, and under program Carry.The device is reasonable in design, circuit is simple, cost is relatively low, easy to control, it is adaptable to small-sized control occasion.

Brief description of the drawings

Fig. 1 is the utility model electrical principle block diagram.

Fig. 2 is the utility model electronic circuit connection figure.

Embodiment

The utility model is described in further details with reference to the accompanying drawings and examples, but the utility model is not limited to this A little embodiments.

Embodiment 1

In Fig. 1, how plural multiply-add operation control device of the utility model based on microcontroller is by master controller electricity Road, CPLD circuit, clock circuit, jtag circuit are connected and composed, master circuit, and whole circuit is controlled；CPLD circuit, The output end of the input termination master circuit of the circuit, the input of the output termination master circuit of the circuit；Clock electricity Road, the input of the output termination CPLD circuit of the circuit；Jtag circuit, the input of the output termination CPLD circuit of the circuit End.

In fig. 2, the master circuit of the present embodiment is made up of integrated circuit U1, wherein, integrated circuit U1 model C8051F000.Integrated circuit U1 pin 17,16,40,31,62 meets 3V, and integrated circuit U1 pin 5,15,61,41,30 connects Ground.Jtag circuit is made up of connector J1, and connector J1 pin 1 meets integrated circuit U2 pin F3, and connector J1's draws Pin 2 meets integrated circuit U2 pin F8, and connector J1 pin 3 meets integrated circuit U2 pin A10, connector J1 pin 4 Integrated circuit U2 pin A1 is met, connector J1 pin 4 is grounded.Clock circuit is made up of paster crystal oscillator Y1, wherein, Y1 types Number JHY50M, Y1 pin 3 is grounded, and Y1 pin 1 meets 3V, and Y1 pin 4 meets integrated circuit U2 pin A6.

CPLD circuit is made up of integrated circuit U2, wherein, integrated circuit U2 model EPM7064BFC100-7.It is integrated The pin H3, F5, D4, G7, E6, C8 of circuit U 2 meet 3V；Integrated circuit U2 pin H8, G4, F6, E5, C3, D7 ground connection；It is integrated The pin D5, G6 of circuit U 2 meet 2.5V.Integrated circuit U1 pin 26 meets integrated circuit U2 pin K8, and integrated circuit U1's draws Pin 25 meets integrated circuit U2 pin K7, and integrated circuit U1 pin 24 meets integrated circuit U2 pin K6, integrated circuit U1's Pin 23 meets integrated circuit U2 pin J9, and integrated circuit U1 pin 58 meets integrated circuit U2 pin J8, integrated circuit U1 Pin 57 meet integrated circuit U2 pin J7, integrated circuit U1 pin 46 meets integrated circuit U2 pin J6, integrated circuit U1 pin 45 meets integrated circuit U2 pin H7, and integrated circuit U1 pin 38 meets integrated circuit U2 pin H6, integrated electricity Road U1 pin 37 meets integrated circuit U2 pin G10, and integrated circuit U1 pin 36 meets integrated circuit U2 pin G9, integrated The pin 35 of circuit U 1 meets integrated circuit U2 pin G8, and integrated circuit U1 pin 34 meets integrated circuit U2 pin F10, collection Pin 32 into circuit U 1 meets integrated circuit U2 pin F9, and integrated circuit U1 pin 60 meets integrated circuit U2 pin K5, Integrated circuit U1 pin 59 meets integrated circuit U2 pin K4, and integrated circuit U1 pin 33 connects integrated circuit U2 pin K3, integrated circuit U1 pin 27 meet integrated circuit U2 pin K2, and integrated circuit U1 pin 54 connects drawing for integrated circuit U2 Pin J5, integrated circuit U1 pin 53 meet integrated circuit U2 pin J4, and integrated circuit U1 pin 52 connects integrated circuit U2's Pin J3, integrated circuit U1 pin 51 meet integrated circuit U2 pin H5, and integrated circuit U1 pin 44 meets integrated circuit U2 Pin H4, integrated circuit U1 pin 43 meets integrated circuit U2 pin H2.

Operation principle of the present utility model is as follows：

System electrification, clock circuit Y1 produces 50MHZ clock signal, wherein, Y1 model JMY50M, clock signal Exported from Y1 pin 4, be input to integrated circuit U2 pin A6；The integrated circuit U2 moment detects its pin K3, K2, J5, J4 The change of level, when pin J4 level from low is changed into high, after pin J5 level is changed into low from height, integrated circuit U2 detections are drawn Whether pin K2 signal occurs rising edge saltus step, and after saltus step is produced, integrated circuit U2 reads that integrated circuit U1 is sent The complex data of one 8 participation computing, 8 data-signals are from integrated circuit U1 pin 26, and 25,24,23,58,57,46, 45 outputs, are input to integrated circuit U2 pin K8, K7, K6, J9, J8, J7, J6, H7；Hereafter, integrated circuit U2 continues to detect Pin K2 second rising edge saltus step of signal, reads second 8 data-signal that integrated circuit U1 is sent；It is same with this Reason, integrated circuit U2 detects pin K2 signal, generates 16 signal rising edge saltus steps altogether, therefore integrated circuit U2 is received 16 8 data-signals, complete the data input of many complex operations；Hereafter, pin J4 level is changed into low from height, pin J5's Level is changed into high from low, represents complex data end of input.

At the same time, integrated circuit U2 receives the data that integrated circuit U1 is sent, wherein, control signal is input to collection Into the pin K3, K2, J5, J4 of circuit U 2；Data-signal is input to U2 pin K8, K7, K6, J9, J8, J7, J6, H7；Hereafter, By the parallel data width conversion logic inside integrated circuit U2, in the driving of integrated circuit U2 pins K2 signal rising edge Under, by 16 8 data-signals sent from integrated circuit U1 of reception, it is transformed into the data-signal a32 of 4 32, B32, c32, d32；Hereafter, by the complex multiplication control logic inside integrated circuit U2, in integrated circuit U2 pins K2 signal Under the driving of rising edge, complete a32 and be multiplied with b32, c32 is multiplied with d32；Again, by the complex addition inside integrated circuit U2 Control logic, under the driving of integrated circuit U2 pins K2 signal rising edge, completes above-mentioned multiplication result phase add operation.

Finally, integrated circuit U2 carries out the transmission of plural multiply-add operation result, wherein, control signal is from integrated circuit U2's Pin J3, H5 output, is input to integrated circuit U1 pin 52,51；Integrated circuit U1 detects J3 level by high step-down, opens Begin to read result data, hereafter, integrated circuit U1 detects H5 level by high step-down, and integrated circuit U1, which is just read, once ties number According to；With this similarly, integrated circuit U1 detects H5 level from high to low altogether, 4 saltus steps, and four knot data are read altogether, are completed The data transfer of many complex operation results.

Claims

1. a kind of how plural multiply-add operation control device based on microcontroller, it is characterised in that：

It has the master circuit being controlled to circuit；CPLD circuit, the input of the circuit terminates the defeated of master circuit Go out end, the input of the output termination master circuit of the circuit；Clock circuit, the output of the circuit terminates the defeated of CPLD circuit Enter end；Jtag circuit, the input of the output termination CPLD circuit of the circuit.

2. the how plural multiply-add operation control device according to claim 1 based on microcontroller, it is characterised in that described Master circuit：It is made up of integrated circuit U1, integrated circuit U1 model C8051F000；Participate in many plural numbers multiply-add The data-signal of computing is exported from integrated circuit U1 pin 26,25,24,23,58,57,46,45；Participate in many multiply-add fortune of plural number The control signal of calculation is exported from integrated circuit U1 pin 33,27,54,53.

3. the how plural multiply-add operation control device according to claim 1 based on microcontroller, it is characterised in that described Master circuit：The result data of many plural multiply-add operations is participated in from integrated circuit U1 pin 38,37,36,35,34,32, 60,59 inputs；The control signal for participating in many plural multiply-add operations is inputted from integrated circuit U1 pin 52,51,44,43.

4. the how plural multiply-add operation control device according to claim 1 based on microcontroller, it is characterised in that described CPLD circuit：CPLD circuit is made up of integrated circuit U2, integrated circuit U2 model EPM7064BFC100-7.

5. the how plural multiply-add operation control device according to claim 1 based on microcontroller, it is characterised in that described CPLD circuit：The CPLD circuit realizes many plural multiply-add operations, and the result data of how plural multiply-add operation is output into master Control device circuit.