CN206302146U - The current foldback circuit of three level inverter - Google Patents
The current foldback circuit of three level inverter Download PDFInfo
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- CN206302146U CN206302146U CN201621458293.9U CN201621458293U CN206302146U CN 206302146 U CN206302146 U CN 206302146U CN 201621458293 U CN201621458293 U CN 201621458293U CN 206302146 U CN206302146 U CN 206302146U
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Abstract
The utility model embodiment discloses a kind of current foldback circuit of three level inverter.The circuit includes：Latch units; the latch units are used for after detecting the afterflow inductance and excessively stream occur; exported again after the conductivity control signal on an IGBT grids and the 3rd IGBT grids is latched a pulse width modulation (PWM) cycle by inversion positive axis; after two-way IGBT is turned off; inductive current continues excessively stream; and reach the second level protection thresholding after, inversion positive axis latch shut-off second IGBT.The current foldback circuit of the three level inverter that the utility model embodiment is provided to and the sink current of taking out of machine or grid-connected middle appearance provide and be effectively protected.
Description
Technical field
The utility model embodiment is related to uninterrupted power source technical field, more particularly to a kind of mistake of three level inverter
Stream protection circuit.
Background technology
It is same in order to improve efficiency in present uninterrupted power source (Uninterruptible power supply, UPS) industry
When reduces cost, rectifying part is substantially all the bus of use ± 400V.Converting Unit selects scope tube to expand, while improving
Inversion efficiency, all using tri-level inversion.Fig. 1 shows the circuit structure of above-mentioned three level inverter.Referring to Fig. 1, four
The collector and emitter of IGBT is in sequential series, forms the bridge arm of three level inverter.Specifically, the collection of an IGBT Q1A
Electrode is connected with direct-flow positive voltage BUS+, and the emitter stage of an IGBT is connected with the colelctor electrode of the 2nd IGBT Q2A, the 2nd IGBT
The emitter stage of Q2A is connected with the colelctor electrode of the 3rd IGBT Q3A, the emitter stage of the 3rd IGBT Q3A and the collection of the 4th IGBT Q4A
Electrode is connected, and the emitter stage of the 4th IGBT Q4A is connected with negative DC voltage BUS-.The emitter stage of the 2nd IGBT Q2A with by continuing
The filter unit connection that stream inductance L1A and filter capacitor C1A is collectively constituted.The both end voltage of the filter capacitor C1A is exactly defeated
Go out voltage.In addition, bridging has two clamps two between the emitter stage of an IGBT Q1A and the emitter stage of the 3rd IGBT Q3A
Pole pipe D5A, D6A.Wherein, the negative electrode of the first clamp diode D5A is connected with the emitter stage of an IGBT Q1A, and the first pincers
The anode of position diode D5A is connected with the negative pressure exit point of voltage output port；The negative electrode of the second clamp diode D6A and electricity
Press output port negative pressure exit point connection, and the anode and the 3rd IGBT Q3A of the second clamp diode D6A transmitting
Pole connects.
The grid input signal of four IGBT is complementary two-by-two.Specifically, the grid input letter of an IGBT and the 3rd IGBT
Number complementation, the grid input signal of the 2nd IGBT and the 4th IGBT is complementary.It means that when the grid input letter of an IGBT
When number being high level, the grid input signal of the 3rd IGBT necessarily low level.Equally, when the grid input signal of the 2nd IGBT
When being low level, the grid input signal of the 4th IGBT necessarily high level.Because the grid input signal of four IGBT can
Control each IGBT conducting whether, therefore, the grid input signal of above-mentioned each IGBT is otherwise known as conductivity control signal.
Inversion insulated gate bipolar transistor in tri-level inversion (Insulated gate bipolar transistor,
IGBT) voltage stress is 400V, can select the IGBT of 600V.But tri-level inversion overcurrent protection is more multiple than two level inverse conversions
Miscellaneous, in multimode and machine or combining inverter, also there is sink current protection problem in it.Common guard method has two kinds, one
Kind turns off the outer tube of three level when being excessively stream, another kind is to close all IGBT.The first protection should be common in unit,
Protection still can guarantee that the voltage stress of each pipe and the polarity of voltage of inverter bridge leg, but if in inversion and bypass short circuit
In the case of, because inverter voltage and civil power have voltage difference, this will result in takes out or sink current.And another protected mode can be solved
Certainly this problem, but easily caused while all IGBT are simultaneously turned off IGBT tie between electric capacity charge it is inconsistent, so as to cause
IGBT partial pressures are unequal, easily cause IGBT over-voltage breakdowns.
Utility model content
For above-mentioned technical problem, the utility model embodiment provides a kind of overcurrent protection electricity of three level inverter
Road, with to being effectively protected in the sink current offer of taking out of simultaneously machine or grid-connected middle appearance.
The utility model embodiment provides a kind of current foldback circuit of three level inverter, the tri-level inversion
Device is diode clamp formula three level inverter, and the diode clamp formula three level inverter is including mutual successively
First insulated gate bipolar transistor IGBT, the 2nd IGBT, the 3rd IGBT and the 4th IGBT of series connection, for the first pincers for clamping
Position diode and the second clamp diode, and the filter unit being made up of afterflow inductance and filter capacitor, it is characterised in that institute
Stating current foldback circuit includes：
First latch units, the input of first latch units and the afterflow inductance connection, described first latches
The output end of unit is connected with the grid of an IGBT and the grid of the 3rd IGBT, for detecting the afterflow electricity
When excessively stream occurs in sense, the conductivity control signal on an IGBT grids and the 3rd IGBT grids is latched into a pulse width modulation
Exported again after PWM cycle.
The utility model embodiment provide three level inverter current foldback circuit, by set voltage ratio compared with
Device, rest-set flip-flop and corresponding output stage gate circuit, can effectively prevent and machine or taking out for grid-connected middle appearance fill electricity
Flow the adverse effect produced for circuit.
Brief description of the drawings
The detailed description made to non-limiting example made with reference to the following drawings by reading, it is of the present utility model
Other features, objects and advantages will become more apparent upon：
Fig. 1 is the circuit structure diagram of the three level inverter that prior art is provided；
Fig. 2 be the utility model first embodiment provide three level inverter current foldback circuit in first latch
The circuit structure diagram of unit；
Fig. 3 is the equivalent circuit diagram of the three level inverter that prior art is provided；
Fig. 4 is the logical construction of the current foldback circuit of the three level inverter that the utility model second embodiment is provided
Structure chart；
Fig. 5 be the utility model second embodiment provide three level inverter current foldback circuit in second latch
The circuit structure diagram of unit；
Fig. 6 is that the utility model second embodiment provides inductive current and bridge arm electricity when taking out sink current overcurrent protection
The oscillogram of pressure.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explanation the utility model, rather than to restriction of the present utility model.Further need exist for
It is bright, for the ease of description, part rather than the entire infrastructure related to the utility model is illustrate only in accompanying drawing.
First embodiment
Present embodiments provide a kind of technical scheme of the current foldback circuit of three level inverter.In the technical scheme
In, the current foldback circuit of three level inverter includes a latch units, and the latch units are used for existing three electricity
Conductivity control signal in flat inverter on the grid of an IGBT and the 3rd IGBT latches a pulse width modulation (PWM) week
Exported again after phase.
Because IGBT is in the presence of electric capacity between knot, the three level inverter in Fig. 1 can be expressed as Fig. 3, as an IGBT
When Q1A and the 3rd IGBT Q3A is closed, the current path of positive bus-bar is cut off, inductance is by the clamps of the 2nd IGBT Q2A and first two
Pole pipe D5A afterflows, electric current declines.Before an IGBT Q1A and the 3rd IGBT Q3A are cut off, IGBT Q1A conductings, the 3rd
IGBT Q3A are off in itself, and bridge arm voltage is+400V.Due to the clamping action in previous cycle, the 3rd IGBT Q3A and
The voltage across poles VCE of four IGBT Q4A is 400V.And an IGBT Q1A pipes shut-off and in a flash, due to the 2nd IGBT Q2A
Acted on the afterflow of the first clamp diode D5A, the tube voltage drop of an IGBT Q1A is+400V, and the 3rd IGBT Q3A and the
Four IGBT Q4A share the 400V voltages of negative busbar.So the voltage stress of each IGBT is also normal, even if inductive current afterflow
To after zero, electric capacity produces resonance between output voltage and filter inductance L1A, IGBT knot, and resonance current is reverse.Due to the second clamp
The clamping action of diode D6A, the tube voltage drop of the 3rd IGBT Q3A and the 4th IGBT Q4A is all without more than 400V.Whole process
In, each switching tube is operated in safety zone.Excessively stream, short-circuit protection whole reliability of this protection process to single cpu mode.
For the overcurrent protection of Modular UPS multi-machine parallel connection or combining inverter, between being related to the module or civil power of parallel connection
Take out sink current, equally take positive axis overcurrent protection to analyze, excessively stream now has several situations：1st, load overload current limliting；2nd, mould
Parallel connection is out of order between block, causes mutual to take out electric current or sink current.In second situation, other modules or the city of parallel connection are divided again
Piezoelectric voltage two kinds of situations higher than this module and low.When other module voltages are high, because parallel connection part is out of order or governing speed
Relatively slow, now other modules can be to this module sink current, and sink current is turned on by the 3rd IGBT Q3A, and output voltage is led over the ground
It is logical, the reverse energy storage of inductance.Inductive current passes through a 2nd IGBT Q2A and IGBT Q1A to just after 3rd IGBT Q3A shut-offs
Bus afterflow and formed, now excessively stream occur the 3rd IGBT Q3A turn on during, therefore protection when, one need to be latched PWM weeks
Phase, i.e., an IGBT Q1A and the 3rd IGBT Q3A are turned off in a cycle.In the case of this protection, in the 3rd IGBT
Before Q3A shut-offs, electric capacity has been filled with electricity between the knot of the 4th IGBT Q4A, the voltage across poles VCE of the 4th IGBT Q4A is clamped negative
Busbar voltage, after the 3rd IGBT Q3A shut-offs, inductive current is first by between the knot of the 3rd IGBT Q3A and the 4th IGBT Q4A
Electric capacity afterflow, makes bridge arm voltage rise to+400V by original 0V.Charged because the 4th IGBT Q4A are preceding, in this mistake
Cheng Zhong, the voltage stress of the 4th IGBT Q4A is higher than the 3rd IGBT Q3A, but when the voltage across poles VCE of the 4th IGBT Q4A is higher than
After negative busbar voltage, its voltage is clamped to zero line by the second clamp diode D6A, its voltage across poles VCE is no more than 400V.The
One IGBT Q1A body diodes lead energy, and an IGBT Q1A and the 2nd IGBT Q2A are straight-through equivalent to conductor, the 3rd IGBT Q3A
The voltage stress of positive bus-bar is born, inductive current declines, and so, each IGBT is still operated in safety zone.
In order to achieve the above object, a kind of current foldback circuit is present embodiments provided.Referring to Fig. 2, current foldback circuit
Including a voltage comparator, a rest-set flip-flop, and two NAND gate circuits.The purposes of voltage comparator is by voltage
It is compared, to judge whether to occur in that over-current phenomenon avoidance.The S signal input parts of rest-set flip-flop and the output signal of voltage comparator
End connection.The R signal input of rest-set flip-flop is connected with the pwm signal for driving.
Two signal input parts of NAND gate circuit are inversion signal inputs.With first IGBT Q1A of connection therein
As a example by one, its two input signals one are the reversed-phase output signals of rest-set flip-flopAnother input signal be for
Drive the pwm signal PWMA of an IGBT Q1A.The voltage comparator is realized by an operational amplifier.
Preferably, rest-set flip-flop can be basic RS filpflop, can also be synchronous rs flip-flop.
In another alternative implementation method of the present embodiment, two NAND gate circuits may alternatively be OR gate
Circuit.When NAND gate circuit is replaced by OR circuit, the reversed-phase output signal of rest-set flip-flop is used as one of OR circuit
Input signal.For as a example by the OR gate for driving an IGBT Q1A, for the pwm signal PWMA quilts of the first IGBT Q1A of driving
As another input signal of OR circuit.
The present embodiment by setting rest-set flip-flop in current foldback circuit, by an IGBT in three level inverter and
The grid voltage of the 3rd IGBT exported again after latching a cycle, it is to avoid the overvoltage that IGBT is caused because taking out sink current is hit
Wear, for three level inverter provides effective overcurrent protection.
Breakdown except avoiding IGBT, the current foldback circuit that the present embodiment is provided also has preferable harmonic characterisitic.Plus
After having entered above-mentioned current foldback circuit, total harmonic distortion factor (the Total harmonic of three level inverter output voltage
Distortion, THD) maintain within 3%.
Second embodiment
The present embodiment further provides the mistake of three level inverter based on the utility model above-described embodiment
Flow another technical scheme of protection circuit.In the technical scheme, the current foldback circuit of three level inverter is not only wrapped
The first latch units are included, also including for two grades of second latch units of overcurrent protection.
Referring to Fig. 4, the current foldback circuit of three level inverter includes：First latch units 41, and with described
Second latch units 42 of the cascade of one latch units 41.The input of the first latch units 41 is connected with afterflow inductance L1A, and it two
Grid of the individual output end respectively with an IGBT Q1A and the 3rd IGBT Q3A is connected.
The input of the second latch units 42 is equally connected with afterflow inductance L1A, and its output end is with the 2nd IGBT Q2A's
Grid is connected.As the trigger signal of the second latch units 42, the conducting of the 3rd IGBT Q3A exported by the first latch units
Control signal is also connected to the second latch units 42.So, the second latch units can according to the instruction of conductivity control signal,
It is determined that the suitable latch started to the shut-off control signal of the 2nd IGBT Q2A.
When and machine module lock mutually break down, when there is paraphase, own module is operated in inversion positive axis, and its
It and machine module or civil power are operated in negative semiaxis, now IGBT Q1A temporary over-currents protection.Turn off an IGBT Q1A and
After 3rd IGBT Q3A, the pressure drop that filter inductance is is-VOUT, is now output as bearing, and output ground is by the first clamp diode
D5A and the 2nd IGBT Q2A give filter inductance energy storage.Now the electric current rate of rise can decline, but electric current also may proceed to rise.This
When need second protection, i.e., to inductive current design second class protection, second class protection thresholding more than the first order overcurrent protection, while
Inversion IGBT pipes are protected to be operated in safe current region.Why two poles protection is set, without directly simultaneously turning off first
IGBT Q1A, the 2nd IGBT Q2A and the 3rd IGBT Q3A because simultaneously turn off these three pipes, an IGBT Q1A and
Electric capacity charges simultaneously between the knot of two IGBT Q2A, if pipe has differences, electric capacity is inconsistent or the turn-off time is inconsistent between knot,
An IGBT Q1A over-voltage breakdowns are then easily caused, and is designed second class protection here and be ensure that the 2nd IGBT Q2A pipes are later than
One IGBT Q1A are turned off.
Fig. 5 shows the internal structure of the second latch units.Referring to Fig. 5, the second latch units inside includes：Voltage
Comparator, rest-set flip-flop, and a NAND gate as output stage.The voltage comparator is used for input voltage and second
Comparison reference voltage is compared, and judges with to whether afterflow inductance L1A continues excessively stream.The rest-set flip-flop is to second
The shut-off control signal of IGBT Q2A is latched.The NAND gate is connected with the rest-set flip-flop, for after to latch
The shut-off control signal of two IGBT Q2A is exported.Due to the output end and the grid of the 2nd IGBT Q2A of the second latch units
Connection, because the latch effect of the second latch units, the turn-off time of the 2nd IGBT Q2A has been delayed by a PWM cycle.
Particularly, the value of the second comparison reference voltage, it should more than the first comparison reference electricity in the first latch units
The value of pressure.
Fig. 6 shows voltage timing diagram during using second class protection.Referring to Fig. 6, before the 2nd IGBT Q2A are turned off, first
IGBT Q1A and the 3rd IGBT Q3A are turned off.Now bridge arm voltage has been clamped to zero, electric capacity between an IGBT Q1A pipe knots
Positive pole line voltage is charged to, when the 2nd IGBT Q2A pipes are turned off, inductive current passes through the 3rd IGBT Q3A and the 4th
IGBT Q4A body diode afterflows, electric current rapid decrease, and electric capacity is charged to negative busbar voltage between the knot of the 2nd IGBT Q2A,
Due to the clamped effect of the second clamp diode D5A, between the knot of an IGBT Q1A electric capacity cannot discharge and recharge again, answer this this mistake
Each IGBT can trouble free service in journey.This two pole protection mistakes flow point should ensure IGBT energy trouble free service, ensure again from
First IGBT Q1A shut-off to the 2nd IGBT Q2A shut-off have enough time delays, to ensure an IGBT Q1A pipe knots between electric capacity fill
Electricity.After second class protection, all of IGBT is turned off, and when opening in next cycle, need in advance open the 2nd IGBT Q2A
Pipe, then IGBT Q1A pipes are opened, to prevent the 2nd IGBT Q2A over-voltage breakdowns.
Preferred embodiment of the present utility model is the foregoing is only, the utility model is not limited to, for this area
For technical staff, the utility model can have various changes and change.All institutes within spirit of the present utility model and principle
Any modification, equivalent substitution and improvements of work etc., should be included within protection domain of the present utility model.
Claims (8)
1. a kind of current foldback circuit of three level inverter, the three level inverter is the level of diode clamp formula three
Inverter, and the diode clamp formula three level inverter includes that the first insulated gate bipolar being serially connected successively is brilliant
Body pipe IGBT, the 2nd IGBT, the 3rd IGBT and the 4th IGBT, for the first clamp diode for clamping and the second two poles of clamp
Pipe, and the filter unit being made up of afterflow inductance and filter capacitor, it is characterised in that the current foldback circuit includes：
First latch units, the input of first latch units and the afterflow inductance connection, first latch units
Output end be connected with the grid of an IGBT and the grid of the 3rd IGBT, go out for detecting the afterflow inductance
During existing excessively stream, the conductivity control signal on an IGBT grids and the 3rd IGBT grids is latched into a pulse width modulation (PWM)
Exported again after cycle.
2. the current foldback circuit of three level inverter according to claim 1, it is characterised in that described first latches
Unit includes：
Voltage comparator, an input and the afterflow inductance connection of the voltage comparator, another input and
One comparison reference signal is connected, and the output end of the voltage comparator is connected with the S signal input parts of rest-set flip-flop, for by institute
The both end voltage for stating filter capacitor compares with first comparison reference signal；
Rest-set flip-flop, the rest-set flip-flop is basic RS filpflop, and its R signal input is connected with PWM cycle signal, for right
The conductivity control signal is latched；
First NAND gate and the second NAND gate, the inversion signal output end of the rest-set flip-flop respectively with first NAND gate and
One inversion signal input connection of second NAND gate, for the conductivity control signal output by latching.
3. the current foldback circuit of three level inverter according to claim 1, it is characterised in that described first latches
Unit includes：
Voltage comparator, an input and the afterflow inductance connection of the voltage comparator, another input and
One comparison reference signal is connected, and the output end of the voltage comparator is connected with the S signal input parts of rest-set flip-flop, for by institute
The both end voltage for stating filter capacitor compares with first comparison reference signal；
Rest-set flip-flop, the rest-set flip-flop is basic RS filpflop, and its R signal input is connected with PWM cycle signal, for right
The conductivity control signal is latched；
First OR gate and the second OR gate, the inversion signal output end of the rest-set flip-flop respectively with first OR gate and described
One in-phase signal input connection of two OR gates, for the conductivity control signal output by latching.
4. the current foldback circuit of three level inverter according to claim 1, it is characterised in that described first latches
Unit includes：
Voltage comparator, an input and the afterflow inductance connection of the voltage comparator, another input and
One comparison reference signal is connected, and the output end of the voltage comparator is connected with the S signal input parts of rest-set flip-flop, for by institute
The both end voltage for stating filter capacitor compares with first comparison reference signal；
Rest-set flip-flop, the rest-set flip-flop is synchronous rs flip-flop, and its R signal input is connected with PWM cycle signal, for right
The conductivity control signal is latched；
First NAND gate and the second NAND gate, the inversion signal output end of the rest-set flip-flop respectively with first NAND gate and
One inversion signal input connection of second NAND gate, for the conductivity control signal output by latching.
5. the current foldback circuit of three level inverter according to claim 1, it is characterised in that described first latches
Unit includes：
Voltage comparator, an input and the afterflow inductance connection of the voltage comparator, another input and
One comparison reference signal is connected, and the output end of the voltage comparator is connected with the S signal input parts of rest-set flip-flop, for by institute
The both end voltage for stating filter capacitor compares with first comparison reference signal；
Rest-set flip-flop, the rest-set flip-flop is synchronous rs flip-flop, and its R signal input is connected with PWM cycle signal, for right
The conductivity control signal is latched；
First OR gate and the second OR gate, the inversion signal output end of the rest-set flip-flop respectively with first OR gate and described
One in-phase signal input connection of two OR gates, for the conductivity control signal output by latching.
6. according to the current foldback circuit of any described three level inverter of claim 2 to 5, it is characterised in that described
Current foldback circuit also includes：
Second latch units, the input of second latch units and the afterflow inductance connection, second latch units
Output end be connected with the grid of the 2nd IGBT, for first latch units output through latch conducting control
After signal, when still detecting excessively stream, by the grid of the 2nd IGBT shut-off control signal latch a PWM cycle after again
Output.
7. the current foldback circuit of three level inverter according to claim 6, it is characterised in that described second latches
Unit includes：
Voltage comparator, an input and the afterflow inductance connection of the voltage comparator, another input and
Two comparison reference signals are connected, and the output end of the voltage comparator is connected with the S signal input parts of rest-set flip-flop, for by institute
The both end voltage for stating filter capacitor compares with second comparison reference signal；
Rest-set flip-flop, its R signal input is connected with PWM cycle signal, for being latched to the shut-off control signal；
NAND gate, the inversion signal output end of the rest-set flip-flop is connected with an inversion signal input of the NAND gate,
For to the shut-off control signal output by latching.
8. the current foldback circuit of three level inverter according to claim 7, it is characterised in that described second compares
Value of the value of reference signal higher than first comparison reference signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201621458293.9U CN206302146U (en) | 2016-12-28 | 2016-12-28 | The current foldback circuit of three level inverter |
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| CN201621458293.9U CN206302146U (en) | 2016-12-28 | 2016-12-28 | The current foldback circuit of three level inverter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110601147A (en) * | 2019-08-20 | 2019-12-20 | 珠海银河智能电网有限公司 | Permanent magnet driver with state protection and implementation method thereof |
| CN110868092A (en) * | 2019-11-28 | 2020-03-06 | 湖北嘉辰达新能源科技有限公司 | Three-level phase-shifted full-bridge high-power supply |
-
2016
- 2016-12-28 CN CN201621458293.9U patent/CN206302146U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110601147A (en) * | 2019-08-20 | 2019-12-20 | 珠海银河智能电网有限公司 | Permanent magnet driver with state protection and implementation method thereof |
| CN110868092A (en) * | 2019-11-28 | 2020-03-06 | 湖北嘉辰达新能源科技有限公司 | Three-level phase-shifted full-bridge high-power supply |
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