CN109039046A - A kind of buffer circuit of half full-bridge submodule of modularization multi-level converter - Google Patents
A kind of buffer circuit of half full-bridge submodule of modularization multi-level converter Download PDFInfo
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- CN109039046A CN109039046A CN201810806248.5A CN201810806248A CN109039046A CN 109039046 A CN109039046 A CN 109039046A CN 201810806248 A CN201810806248 A CN 201810806248A CN 109039046 A CN109039046 A CN 109039046A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
- H02M1/348—Passive dissipative snubbers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a kind of buffer circuit of half full-bridge submodule of modularization multi-level converter, half full-bridge submodule includes left half-bridge module, right half-bridge module and connection circuit；It also include that three groups of RCD buffer circuits connects after every group of RCD buffer circuit includes: a resistance and a diodes in parallel with a capacitor, the diode cathode connection capacitance cathode.The present invention proposes the buffer structure of 3 groups of RCD buffer circuits, the IGBT of left half-bridge module is inhibited to turn off due to voltage spikes by first group of RCD buffer circuit, the IGBT of right half-bridge module is inhibited to turn off due to voltage spikes by second group of RCD buffer circuit, the IGBT of connection circuit is inhibited to turn off due to voltage spikes by third group RCD buffer circuit, simplify the buffer circuit of half full-bridge submodule, while degradation buffer circuit cost, IGBT can preferably be inhibited to turn off voltage；The present invention proposes the parameter designing of RCD buffer circuit, can reduce system cost, and guarantees that IGBT shutdown overvoltage does not overshoot.
Description
Technical field
The invention belongs to IGBT buffer circuit research fields, more particularly, to a kind of modularization multi-level converter half
The buffer circuit of full-bridge submodule.
Background technique
Modularization multi-level converter (Modular Multilevel Converter, MMC) has modular construction easy
In encapsulation extension, the small advantages such as low with harmonic wave of output voltage of switching device stress, it is applied in practical projects, such as the U.S.
Transbay engineering, China five end flexible DC transmission engineering of Zhoushan.
Different according to submodule topological structure, modularization multi-level converter is generally divided into semi-bridge type, bridge-type and clamp
Dimorphism three types.Half full-bridge submodule (Semi-Full Bridge Sub-module, SFB-SM) is a kind of clamp dimorphism
Module, it is made of 7 IGBT anti-paralleled diodes, has four kinds of+2Uc ,+Uc, 0 and-Uc level fan-out capabilities.Compared to energy
The full-bridge submodule of direct fault current is actively blocked, SFB-SM reduces power electronic devices quantity.Simultaneously as SFB-SM
Two capacitor charge and discharge simultaneously, therefore two capacitance voltages remain balanced.
Due to the presence of main circuit parasitic inductance, so that insulated gate bipolar transistor (Silicon Insulated
Gate Bipolar Transistor, Si IGBT) turn off process can generate very big shutdown due to voltage spikes, excessively high shutdown electricity
Pointing summit damages IGBT, while may cause IGBT and misleading, therefore needs to be arranged buffering electricity in IGBT practical application circuit
Road inhibits shutdown due to voltage spikes.Currently, the buffer circuit design method of half-bridge submodule mainly has:
1) one group of resistor-capacitor diode in parallel by each switching device (Resistance Capacitance Diode,
RCD) buffer circuit.As shown in Fig. 1 (a), both end voltage is increased so that diode current flow is to capacitor charging in IGBT turn off process,
To inhibit IGBT to turn off due to voltage spikes, IGBT turn-off power loss is reduced.This method design is simple and reliable, but has used a large amount of
RCD buffer circuit, so that buffer circuit structure is complex.
2) in capacitor both ends one group of RCD buffer circuit in parallel.As shown in Fig. 1 (b), since two IGBT of half-bridge submodule are opened
OFF signal is complementary, and the process of switching tube shutdown, another switching tube must be connected, therefore half-bridge submodule buffer circuit can
To be simplified.
In conclusion since half full-bridge submodule contains a large amount of IGBT, traditional buffer circuit design method compared with
For complexity, higher cost.Therefore, a kind of RCD buffer circuit of half full-bridge submodule of simplification is needed.
Summary of the invention
In view of the drawbacks of the prior art, it is an object of the invention to solve half full-bridge submodule of the prior art to need largely
Caused by IGBT the technical issues of design complexity, higher cost.
To achieve the above object, the present invention provides a kind of buffering of half full-bridge submodule of modularization multi-level converter electricity
Road, the half full-bridge submodule include left half-bridge module, right half-bridge module and connection circuit；Wherein, the left half-bridge module packet
It includes: after first switch tube T1 and second switch T2 series connection, being parallel to tie point P1 and tie point N1 with first capacitor C1；It is described
Right half-bridge module include: third switch transistor T 3 and the 4th switch transistor T 4 series connection after, with the second capacitor C2 be parallel to tie point P2 and
Tie point N2；Connecting circuit includes the 5th switch transistor T 5, the 6th switch transistor T 6 and the 7th switch transistor T 7, the bridging of the 6th switch transistor T 6
Between the tie point P1 and tie point P2 of left and right half-bridge module, the 7th switch transistor T 7 is connected across the tie point of left and right half-bridge module
Between N1 and tie point N2, the 5th switch transistor T 5 is connected between the 6th switch transistor T 6 and the 7th switch transistor T 7,
It also include three groups of RCD buffer circuits, after every group of RCD buffer circuit includes: a resistance and a diodes in parallel,
It connects with a capacitor, the diode cathode connects the capacitance cathode, and the diode cathode is denoted as tie point A, institute
It states capacitor cathode and is denoted as tie point B；
First group of RCD buffer circuit tie point A is connected with half full-bridge submodule tie point P1, tie point B and half full-bridge
Module connection points N1 is connected；
Second group of RCD buffer circuit tie point A is connected with half full-bridge submodule tie point P2, tie point B and half full-bridge
Module connection points N2 is connected；
Third group RCD buffer circuit tie point A is connected with half full-bridge submodule tie point P1, tie point B and half full-bridge
Module connection points N2 is connected.
Specifically, each switching tube is made of 1 IGBT inverse parallel, 1 diode in T1~T7.
Specifically, the half specific connection type of full-bridge submodule are as follows:
The emitter of the first switch tube T1 is connected with the collector of second switch T2；The first switch tube T1's
The anode connection of collector, the emitter of the 6th switch transistor T 6 and first capacitor C1；The emitter of the second switch T2,
The cathode of the emitter of five switch transistor Ts 5, the collector of the 7th switch transistor T 7 and first capacitor C1 connects；5th switching tube
The anode connection of the collector of T5, the collector of the 6th switch transistor T 6, the collector of third switch transistor T 3 and the second capacitor C2；Institute
State the cathode connection of the emitter of the 7th switch transistor T 7, the emitter of the 4th switch transistor T 4 and the second capacitor C2；The third is opened
Close the emitter of pipe T3 and the collector connection of the 4th switch transistor T 4.
Specifically, the left half-bridge module further includes the 8th switching tube M1, is series at tie point P1 with first capacitor C1
With tie point N1；The right half-bridge module further includes the 9th switching tube M2, is series at tie point P2 and company with first capacitor C2
Contact N2.
Specifically, each switching tube is made of 1 IGBT inverse parallel, 1 diode in T1~T7.
Specifically, the half specific connection type of full-bridge submodule are as follows:
The emitter of the first switch tube T1 is connected with the collector of second switch T2；The first switch tube T1's
The source electrode of collector, the emitter of the 6th switch transistor T 6 and the 8th switching tube M1 connects；The drain electrode of the 8th switching tube M1 and
The anode connection of first capacitor C1；Emitter, the 7th switching tube of the emitter of the second switch T2, the 5th switch transistor T 5
The cathode connection of the collector and first capacitor C1 of T7；The current collection of the collector of 5th switch transistor T 5, the 6th switch transistor T 6
The source electrode of pole, the collector of third switch transistor T 3 and the 9th switching tube M2 connects；The drain electrode and second of the 9th switching tube M2
The anode connection of capacitor C2；The emitter of 7th switch transistor T 7, the emitter of the 4th switch transistor T 4 and the second capacitor C2
Cathode connection；The emitter of the third switch transistor T 3 and the collector connection of the 4th switch transistor T 4.
Specifically, each switching tube is made of 1 SiC MOSFET inverse parallel, 1 diode in M1~M2.
Specifically, in the RCD buffer circuit capacitor C calculation formula are as follows:
Wherein, IpFor IGBT collector current peak value, UCFor the rated operational voltage of capacitor in the RCD buffer circuit, tf
For the capacitor both end voltage rise time in the RCD buffer circuit；
The calculation formula of resistance R in the RCD buffer circuit are as follows:
3RC=ton(min) (2)
Wherein, ton (min) is minimum IGBT turn-on time, and C is capacitance size in the RCD buffer circuit；
Diode minimum pressure voltage chooses the load voltage value of IGBT in the RCD buffer circuit.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, have below beneficial to effect
Fruit:
(1) compared with prior art, the present invention proposes the buffer structure of 3 groups of RCD buffer circuits, slow by first group of RCD
Rushing circuit inhibits the IGBT of left half-bridge module to turn off due to voltage spikes, inhibits right half-bridge module by second group of RCD buffer circuit
IGBT turns off due to voltage spikes, inhibits the IGBT of connection circuit to turn off due to voltage spikes by third group RCD buffer circuit, simplifies half
The buffer circuit of full-bridge submodule can preferably inhibit IGBT to turn off voltage while degradation buffer circuit cost.
(2) compared with prior art, the present invention proposes the parameter designing of RCD buffer circuit, according to discharge resistance consumption
Energy is the energy design capacitor of capacitor charging, and 5% or less the charge on capacitor C is discharged into charged lotus designs resistance,
Diode minimum pressure voltage is chosen for the load voltage value design diode of IGBT in major loop, and suitable RCD parameter can reduce
System cost, and guarantee that IGBT shutdown overvoltage does not overshoot.
Detailed description of the invention
Fig. 1 (a) is 1 structural schematic diagram of buffer circuit of half-bridge submodule in the prior art；
Fig. 1 (b) is 2 structural schematic diagram of buffer circuit of half-bridge submodule in the prior art.
Fig. 2 is modularization multi-level converter MMC topological structure schematic diagram provided in an embodiment of the present invention.
Fig. 3 is half full-bridge submodule topological structure schematic diagram provided in an embodiment of the present invention.
Fig. 4 is half full-bridge submodule buffer circuit topological structure schematic diagram provided in an embodiment of the present invention.
Fig. 5 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith+UC, current direction is timing
Simulation result diagram；
Fig. 6 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith+UC, when current direction is negative
Simulation result diagram；
Fig. 7 is that half full-bridge submodule output level provided in an embodiment of the present invention is+UCWith 0, current direction is timing
Simulation result diagram；
Fig. 8 is that half full-bridge submodule output level provided in an embodiment of the present invention is+UCWith 0, when current direction is negative
Simulation result diagram；
Fig. 9 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith 0, current direction is timing
Simulation result diagram；
Figure 10 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith 0, when current direction is negative
Simulation result diagram；
Figure 11 is that half full-bridge submodule output level provided in an embodiment of the present invention is-UCWith 0, current direction is timing
Simulation result diagram；
Figure 12 is that half full-bridge submodule output level provided in an embodiment of the present invention is-UCWith 0, when current direction is negative
Simulation result diagram；
Wherein, in Fig. 5-Figure 12, (a) is output voltage waveforms；It (b) is output current wave；(c) for not comprising buffering electricity
The switching tube both end voltage waveform on road；It (d) is the switching tube both end voltage waveform comprising buffer circuit.
Figure 13 is half full-bridge submodule buffer circuit topological structure schematic diagram of capacitance switch type provided in an embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
The present invention is described by taking half full-bridge submodule of modularization multi-level converter MMC as an example simplifies buffer circuit design side
Case.Fig. 2 is modularization multi-level converter MMC topological structure schematic diagram provided in an embodiment of the present invention.As shown in Fig. 2, comprising
A, B, C three-phase, every phase include upper and lower two bridge arms, and each bridge arm concatenates a bridge arm electricity by N number of half full-bridge sub-module cascade
Sense is constituted.
Fig. 3 is half full-bridge submodule topological structure schematic diagram provided in an embodiment of the present invention.As shown in figure 3, half full-bridge is sub
Module includes left half-bridge module, right half-bridge module and connection circuit；Wherein,
The left half-bridge module include: first switch tube T1 and second switch T2 series connection after, it is in parallel with first capacitor C1；
The right half-bridge module include: third switch transistor T 3 and the 4th switch transistor T 4 series connection after, it is in parallel with the second capacitor C2；Connect circuit
Including the 5th switch transistor T 5, the 6th switch transistor T 6 and the 7th switch transistor T 7, the 6th switch transistor T 6, the 7th switch transistor T 7 bridge respectively
Between the half-bridge module of left and right, the 5th switch transistor T 5 is connected between the 6th switch transistor T 6 and the 7th switch transistor T 7；In T1~T7
Each switching tube is made of 1 IGBT inverse parallel, 1 diode.
Fig. 4 is half full-bridge submodule buffer circuit topological structure schematic diagram provided in an embodiment of the present invention.As shown in figure 4,
In order to simplify buffer circuit, present invention employs half full-bridge submodules and three groups of RCD buffer circuits.
The half specific connection type of full-bridge submodule are as follows: the emitter of the first switch tube T1 and second switch T2's
Collector connection, tie point are denoted as tie point P；The emitter of the collector of the first switch tube T1, the 6th switch transistor T 6
And the anode connection of first capacitor C1, tie point are denoted as tie point P1；The emitter of the second switch T2, the 5th switch
The cathode of the emitter of pipe T5, the collector of the 7th switch transistor T 7 and first capacitor C1 connects, and tie point is denoted as tie point N1；
Collector, the collector of the 6th switch transistor T 6, the collector of third switch transistor T 3 and the second capacitor of 5th switch transistor T 5
The anode connection of C2, tie point are denoted as tie point P2；The transmitting of the emitter, the 4th switch transistor T 4 of 7th switch transistor T 7
The connection of the cathode of pole and the second capacitor C2, tie point are denoted as tie point N2；The emitter and the 4th of the third switch transistor T 3
The collector of switch transistor T 4 connects, and tie point is denoted as tie point N.
RCD buffer circuit is made of a resistance, a diode and a capacitor.The RCD buffer circuit connection side
Formula is one diode of resistor coupled in parallel, and diode cathode connects capacitance cathode.Preferably, the diode cathode is denoted as connection
Point A, the capacitor cathode are denoted as tie point B.
RCD buffer circuit working principle are as follows: when switching tube shutdown, both end voltage rises, so that diode in parallel is led
It is logical.Capacitor charging limits the speed of IGBT both end voltage rising, cuts down due to voltage spikes.Simultaneously as due to voltage spikes is reduced,
The overlapping of raised voltage and drop-out current is reduced, to reduce IGBT turn-off power loss.Similarly, due to capacitor discharge so that
IGBT is quickly open-minded, and current rise rate increases, and service time shortens, and reduces the overlapping of voltage and current, reduces open-minded
Loss.
Three groups of specific connection types of RCD buffer circuit are as follows: first group of RCD buffer circuit tie point A and half full-bridge
Submodule tie point P1 is connected, and tie point B is connected with half full-bridge submodule tie point N1；Second group of RCD buffer circuit connects
Contact A is connected with half full-bridge submodule tie point P2, and tie point B is connected with half full-bridge submodule tie point N2；The third group
RCD buffer circuit tie point A is connected with half full-bridge submodule tie point P1, tie point B and half full-bridge submodule tie point N2 phase
Even.
Simplify the working principle of buffer circuit are as follows: left half-bridge module is inhibited by first group of RCD buffer circuit
IGBT turns off due to voltage spikes, inhibits the IGBT of right half-bridge module to turn off due to voltage spikes by second group of RCD buffer circuit, leads to
Cross the IGBT shutdown due to voltage spikes that the third group RCD buffer circuit inhibits connection circuit.
RCD buffer circuit parameter designing step are as follows:
1) capacitance parameter designs
Since the energy consumed in the size and resistance of capacitor is directly proportional, while influencing the effect of buffer circuit.Therefore, false
The electric current that capacitor is crossed in constant current is the half of peak point current, then has:
In formula, IpFor collector current peak value, UCFor capacitor rated operational voltage, tfFor the capacitor both end voltage rise time.
The minimum pressure voltage of Absorption Capacitance should be the load voltage value of IGBT in major loop in buffer circuit, and pressure voltage is chosen
It is too small to carry out hidden danger to the safety belt of major loop.Meanwhile the Absorption Capacitance of buffer circuit needs to select noninductive capacitor.
2) resistance parameter designs
Buffer circuit requires before each IGBT shutdown, and capacitor must discharge completely charge.Therefore, the choosing of resistance R
Taking must assure that after IGBT is opened, and the charge on capacitor is discharged into the 5% or less of charged lotus, it may be assumed that
3RC=ton(min) (2)
In formula, ton(min)For minimum turn-on time, C is capacitance size.
3) diode parameters design
Diode used in buffer loop selects fast recovery diode MUR860,600V rated.
In the present embodiment, collector current peak IpFor 12A, capacitance voltage rated value UCFor 100V, in capacitor both end voltage
Rise time tfFor 3 μ s, 0.09 μ F is calculated to obtain by formula (1), taking capacitor C is 0.1 μ F, and the voltage rating of actual capacitance device takes
Value is twice of capacitor rated operational voltage, i.e. 200V.In the present embodiment, minimum turn-on time ton(min)For 20 μ s, capacitor C is
0.1 μ F, can be calculated resistance R by formula (2) is 66.7 Ω, and taking resistance R is 60 Ω.
The feasibility of the half full-bridge submodule buffer circuit is demonstrated by PSpice simulation software.Simulation parameter such as table 1
It is shown.Simulation result is as shown in Fig. 5~Figure 12, using current direction shown in Fig. 4 as positive direction.
Table 1
Fig. 5 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith+UC, current direction is timing
Simulation result diagram, taking on each route parasitic inductance at this time is 2 μ H.Wherein, Fig. 5 (a) is output voltage waveforms.Such as Fig. 5 (a)
Shown, in 0~50 μ s, switch transistor T 1, T4, T6, T7 conducting export one times of rated operational voltage 100V；In 50~53 μ s, switch
Pipe T5 is open-minded, T6, T7 shutdown；In 53~100 μ s, switch transistor T 1, T4, T5 conducting export twice of rated operational voltage 200V；
In 100~103 μ s, switch transistor T 6, T7 are open-minded, T5 shutdown；In 103~150 μ s, switch transistor T 1, T4, T6, T7 conducting, output one
Times rated operational voltage 100V.Fig. 5 (b) is output current wave.It exports electric current and is greater than 0.Fig. 5 (c) is not comprising buffer circuit
Switch transistor T 5, T6, T7 both end voltage waveform, Fig. 5 (d) be the switch transistor T 5 comprising buffer circuit, T6, T7 both end voltage wave
Shape.The result shows that T5 pipe shutdown due to voltage spikes is 141.3V when not including buffer circuit, T5 pipe shutdown when comprising buffer circuit
Due to voltage spikes is 101.1V, and shutdown due to voltage spikes has obtained good inhibition.The shutdown due to voltage spikes of T6, T7 pipe is in two kinds of situations
Under shutdown due to voltage spikes it is little.
Fig. 6 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith+UC, when current direction is negative
Simulation result diagram, taking on each route parasitic inductance at this time is 2 μ H.Wherein, Fig. 6 (a) is output voltage waveforms.Such as Fig. 6 (a)
Shown, switching tube action timing is identical when being positive with current direction.Fig. 6 (b) is output current wave, exports electric current less than 0.Figure
6 (c) be the switch transistor T 5 not comprising buffer circuit, T6, T7 both end voltage waveform.Fig. 6 (d) is the switching tube comprising buffer circuit
T5, T6, T7 both end voltage waveform.The result shows that T5 pipe shutdown due to voltage spikes is 513.1V when not including buffer circuit, comprising slow
T5 pipe shutdown due to voltage spikes when rushing circuit is 164.7V, and shutdown due to voltage spikes has obtained great inhibition.The shutdown of T6, T7 pipe
The shutdown due to voltage spikes of due to voltage spikes in both cases is little.
Fig. 7 is that half full-bridge submodule output level provided in an embodiment of the present invention is+UCWith 0, current direction is timing
Simulation result diagram, taking parasitic inductance on each route at this time is 20 μ H.Wherein, Fig. 7 (a) is output voltage waveforms.Such as Fig. 7 (a)
Shown, in 0~50 μ s, switch transistor T 1, T4, T6, T7 conducting export one times of rated operational voltage 100V；In 50~53 μ s, switch
Pipe T3 is open-minded, T4, T7 shutdown；In 53~100 μ s, switch transistor T 1, T4, T6 conducting, output voltage 0；In 100~103 μ s, open
It is open-minded to close pipe T4, T7, T3 shutdown；In 103~150 μ s, switch transistor T 1, T4, T6, T7 conducting export one times of rated operational voltage
100V.Fig. 7 (b) is output current wave, and output electric current is greater than 0.Fig. 7 (c) does not include the switch transistor T 3 of buffer circuit, the both ends T4
Voltage waveform.Fig. 7 (d) is the switch transistor T 3 comprising buffer circuit, T4 both end voltage waveform.The result shows that not including buffering electricity
T3 pipe shutdown due to voltage spikes is 431.0V when road, and T3 pipe shutdown due to voltage spikes when comprising buffer circuit is 166.9V, shutdown electricity
Pointing peak has obtained good inhibition.T4 pipe shutdown due to voltage spikes is 235.3V when not comprising buffer circuit, includes buffer circuit
When T4 pipe shutdown due to voltage spikes be 100.8V, shutdown due to voltage spikes obtained good inhibition.
Fig. 8 is that half full-bridge submodule output level provided in an embodiment of the present invention is+UCWith 0, when current direction is negative
Simulation result diagram, taking parasitic inductance on each route at this time is 20 μ H.Wherein, Fig. 8 (a) is output voltage waveforms, and switching tube is dynamic
Make identical when timing is positive with current direction.Fig. 8 (b) is output current wave, exports electric current less than 0.Fig. 8 (c) be not comprising
The switch transistor T 3 of buffer circuit, T4 both end voltage waveform.Fig. 8 (d) is the switch transistor T 3 comprising buffer circuit, T4 both end voltage wave
Shape.The result shows that T4 pipe shutdown due to voltage spikes is 213.4V when not including buffer circuit, T4 pipe shutdown when comprising buffer circuit
Due to voltage spikes is 118.1V, and shutdown due to voltage spikes has obtained good inhibition.The shutdown due to voltage spikes of T3 pipe is in both cases
Shutdown due to voltage spikes it is little.
Fig. 9 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith 0, current direction is timing
Simulation result diagram, taking parasitic inductance on each route at this time is 2 μ H.Wherein, Fig. 9 (a) is output voltage waveforms.Such as Fig. 9 (a) institute
Show, in 0~50 μ s, switch transistor T 1, T4, T5 conducting export twice of voltage rating 200V；In 50~53 μ s, switch transistor T 3, T6 are opened
It is logical, T4, T5 shutdown；In 53~100 μ s, switch transistor T 1, T3, T6 conducting, output voltage 0；In 100~103 μ s, switching tube
T4, T5 are open-minded, T3, T6 shutdown；In 103~150 μ s, switch transistor T 1, T4, T5 conducting export twice of voltage rating 200V.Fig. 9
It (b) is output current wave, output electric current is greater than 0.Fig. 9 (c) is the switch transistor T 3 not comprising buffer circuit, the both ends T4, T5, T6
Voltage waveform.Fig. 9 (d) is the switch transistor T 3 comprising buffer circuit, T4, T5, T6 both end voltage waveform.The result shows that not including
T6 pipe shutdown due to voltage spikes is 202.0V when buffer circuit, and T6 pipe shutdown due to voltage spikes when comprising buffer circuit is 123.3V,
Shutdown due to voltage spikes has obtained good inhibition.Switch transistor T 3, T4, T5 shutdown due to voltage spikes in both cases shutdown electricity
Pointing peak is little.
Figure 10 is that half full-bridge submodule output level provided in an embodiment of the present invention is+2UCWith 0, when current direction is negative
Simulation result diagram, taking on each route parasitic inductance at this time is 2 μ H.Wherein, Figure 10 (a) is output voltage waveforms, switching tube
It is identical when action sequence is positive with current direction.Figure 10 (b) is output current wave, and output electric current is greater than 0.Figure 10 (c) is not
Switch transistor T 3 comprising buffer circuit, T4, T5, T6 both end voltage waveform.Figure 10 (d) be the switch transistor T 3 comprising buffer circuit,
T4, T5, T6 both end voltage waveform.The result shows that T4 pipe shutdown due to voltage spikes is 376.4V when not including buffer circuit, comprising slow
T4 pipe shutdown due to voltage spikes when rushing circuit is 115.3V, and shutdown due to voltage spikes has obtained good inhibition.Not comprising buffering electricity
T5 pipe shutdown due to voltage spikes is 450.9V when road, and T4 pipe shutdown due to voltage spikes when comprising buffer circuit is 111.3V, shutdown electricity
Pointing peak has obtained good inhibition.The shutdown due to voltage spikes shutdown due to voltage spikes in both cases of switch transistor T 3, T4, T5
Less.
Figure 11 is that half full-bridge submodule output level provided in an embodiment of the present invention is-UCWith 0, current direction is timing
Simulation result diagram, taking parasitic inductance on each route at this time is 2 μ H.Wherein, Figure 11 (a) is output voltage waveforms.Such as Figure 11 (a)
Shown, in 0~50 μ s, switch transistor T 2, T3, T6, T7 conducting export one times of reverse rated voltage -100V；In 50~53 μ s, open
It is open-minded to close pipe T5, T6, T7 shutdown；In 53~100 μ s, switch transistor T 2, T3, T5 conducting, output voltage 0；In 100~103 μ s,
Switch transistor T 6, T7 are open-minded, T5 shutdown；In 103~150 μ s, switch transistor T 2, T3, T6, T7 conducting export one times of reversed specified electricity
Pressure -100V.Figure 11 (b) is output current wave, and output electric current is greater than 0.Figure 11 (c) is the switching tube not comprising buffer circuit
T5, T6, T7 both end voltage waveform.Figure 11 (d) is the switch transistor T 5 comprising buffer circuit, T6, T7 both end voltage waveform.As a result table
Bright, T5 pipe shutdown due to voltage spikes is 158.8V when not including buffer circuit, and T5 pipe when comprising buffer circuit turns off due to voltage spikes
For 134.4V, turns off due to voltage spikes and obtained good inhibition.Switch transistor T 6, T7 shutdown due to voltage spikes in both cases
It is little to turn off due to voltage spikes.
Figure 12 is that half full-bridge submodule output level provided in an embodiment of the present invention is-UCWith 0, when current direction is negative
Simulation result diagram, taking parasitic inductance on each route at this time is 2 μ H.Wherein, Figure 12 (a) is output voltage waveforms, and switching tube is dynamic
Make identical when timing is positive with current direction.Figure 12 (b) is output current wave, and output electric current is greater than 0.Figure 12 (c) is not wrap
Switch transistor T 5, T6, T7 both end voltage waveform containing buffer circuit.Figure 12 (d) is the switch transistor T 5 comprising buffer circuit, T6, T7
Both end voltage waveform.The result shows that T5 pipe shutdown due to voltage spikes is 288.6V when not including buffer circuit, when including buffer circuit
T5 pipe shutdown due to voltage spikes be 180.7V, shutdown due to voltage spikes obtained good inhibition.The shutdown voltage of switch transistor T 6, T7
The shutdown due to voltage spikes of spike in both cases is little.
The half full-bridge submodule topological structure has active output+2UC、+UC、0、-UCThe ability of four kinds of level, being based on should
The MMC system of topological structure may be implemented DC Line Fault and pass through and pressure-raising operation.
In conclusion between varying level in conversion process, not including buffering electricity in the case of considering different current directions
The IGBT of the half full-bridge submodule on road can generate biggish shutdown overvoltage in turn off process, or even can reach five times of capacitor volumes
It is more than fixed working voltage.In addition all IGBT of half full-bridge submodule can be made after simplified buffer circuit of the present invention
Inhibited well in the shutdown overvoltage of turn off process, when parasitic inductance parameter is not king-sized, can be protected
Card shutdown overvoltage is no more than 130V (1.3 times of capacitor rated operational voltages), even if parasitic inductance parameter is very big, turns off overvoltage
No more than 170V (1.7 times of capacitor rated operational voltages), general switching tube voltage rating type selecting be twice of rated operational voltage with
On, therefore the half full-bridge submodule buffer circuit can satisfy the normal work of half full-bridge submodule.
Figure 13 is half full-bridge submodule buffer circuit topological structure schematic diagram of capacitance switch type provided in an embodiment of the present invention.
Compared with Fig. 4, This structure increases the 8th switching tube M1 and the 9th switching tube M2, each switching tube is by 1 SiC in M1~M2
1 diode of MOSFET inverse parallel is constituted.Its specific connection type are as follows:
The emitter of the first switch tube T1 is connected with the collector of second switch T2, and tie point is denoted as tie point
P；The source electrode of the collector of the first switch tube T1, the emitter of the 6th switch transistor T 6 and the 8th switching tube M1 connects, and connects
Contact is denoted as tie point P1；The drain electrode of the 8th switching tube M1 and the anode connection of first capacitor C1；The second switch
The cathode connection of the emitter of T2, the emitter of the 5th switch transistor T 5, the collector of the 7th switch transistor T 7 and first capacitor C1,
Tie point is denoted as tie point N1；Collector, the collector of the 6th switch transistor T 6, third switch transistor T 3 of 5th switch transistor T 5
Collector and the 9th switching tube M2 source electrode connection, tie point is denoted as tie point P2；The drain electrode of the 9th switching tube M2
With the anode connection of the second capacitor C2；The emitter of 7th switch transistor T 7, the emitter of the 4th switch transistor T 4 and the second electricity
Hold the cathode connection of C2, tie point is denoted as tie point N2；The emitter of the third switch transistor T 3 and the 4th switch transistor T 4
Collector connection, tie point are denoted as tie point N.
SiC MOSFET is compared with Si IGBT, with that conducting resistance is low, switching speed is fast and hot properties is excellent is excellent
Point.System loss, while increase that will not be excessive can be greatly reduced in conjunction with the submodule topology of Si IGBT and SiC MOSFET
System cost.
Working principle of the buffer circuit in half full-bridge submodule of capacitance switch type are as follows: buffered by first group of RCD
Circuit inhibits SiIGBT the and SiC MOSFET of left half-bridge module (including T1, T2, M1) to turn off due to voltage spikes, passes through described second
Group RCD buffer circuit inhibits SiIGBT the and SiC MOSFET of right half-bridge module (including T3, T4, M2) to turn off due to voltage spikes, leads to
Cross the IGBT shutdown due to voltage spikes that the third group RCD buffer circuit inhibits connection circuit (comprising T5, T6, M7).
As it will be easily appreciated by one skilled in the art that the above is merely preferred embodiments of the present invention, not to limit
The present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in this
Within the protection scope of invention.
Claims (8)
1. a kind of buffer circuit of half full-bridge submodule of modularization multi-level converter, the half full-bridge submodule includes left half-bridge
Module, right half-bridge module and connection circuit；Wherein, the left half-bridge module includes: first switch tube T1 and second switch T2
After series connection, tie point P1 and tie point N1 are parallel to first capacitor C1；The right half-bridge module includes: 3 He of third switch transistor T
After the series connection of 4th switch transistor T 4, tie point P2 and tie point N2 are parallel to the second capacitor C2；Connecting circuit includes the 5th switch
Pipe T5, the 6th switch transistor T 6 and the 7th switch transistor T 7, the 6th switch transistor T 6 are connected across tie point P1 and the company of left and right half-bridge module
Between contact P2, the 7th switch transistor T 7 is connected across between the tie point N1 of left and right half-bridge module and tie point N2, the 5th switching tube
T5 is connected between the 6th switch transistor T 6 and the 7th switch transistor T 7, which is characterized in that
It also include three groups of RCD buffer circuits, after every group of RCD buffer circuit includes: a resistance and a diodes in parallel, with one
A capacitor series connection, the diode cathode connect the capacitance cathode, and the diode cathode is denoted as tie point A, the electricity
Hold cathode and is denoted as tie point B；
First group of RCD buffer circuit tie point A is connected with half full-bridge submodule tie point P1, tie point B and half full-bridge submodule
Tie point N1 is connected；
Second group of RCD buffer circuit tie point A is connected with half full-bridge submodule tie point P2, tie point B and half full-bridge submodule
Tie point N2 is connected；
Third group RCD buffer circuit tie point A is connected with half full-bridge submodule tie point P1, tie point B and half full-bridge submodule
Tie point N2 is connected.
2. buffer circuit as described in claim 1, which is characterized in that each switching tube is by 1 IGBT inverse parallel 1 in T1~T7
A diode is constituted.
3. buffer circuit as claimed in claim 2, which is characterized in that the half specific connection type of full-bridge submodule are as follows:
The emitter of the first switch tube T1 is connected with the collector of second switch T2；The current collection of the first switch tube T1
The anode connection of pole, the emitter of the 6th switch transistor T 6 and first capacitor C1；The emitter of the second switch T2, the 5th open
Close the cathode connection of the emitter of pipe T5, the collector of the 7th switch transistor T 7 and first capacitor C1；5th switch transistor T 5
The anode connection of collector, the collector of the 6th switch transistor T 6, the collector of third switch transistor T 3 and the second capacitor C2；Described
The cathode of the emitter of seven switch transistor Ts 7, the emitter of the 4th switch transistor T 4 and the second capacitor C2 connects；The third switching tube
The emitter of T3 and the connection of the collector of the 4th switch transistor T 4.
4. buffer circuit as described in claim 1, which is characterized in that the left half-bridge module further includes the 8th switching tube M1,
It is series at tie point P1 and tie point N1 with first capacitor C1；The right half-bridge module further includes the 9th switching tube M2, with
First capacitor C2 is series at tie point P2 and tie point N2.
5. buffer circuit as claimed in claim 4, which is characterized in that each switching tube is by 1 IGBT inverse parallel 1 in T1~T7
A diode is constituted.
6. buffer circuit as claimed in claim 5, which is characterized in that the half specific connection type of full-bridge submodule are as follows:
The emitter of the first switch tube T1 is connected with the collector of second switch T2；The current collection of the first switch tube T1
The source electrode of pole, the emitter of the 6th switch transistor T 6 and the 8th switching tube M1 connects；The drain electrode and first of the 8th switching tube M1
The anode connection of capacitor C1；The emitter of the second switch T2, the emitter of the 5th switch transistor T 5, the 7th switch transistor T 7
The connection of the cathode of collector and first capacitor C1；The collector of 5th switch transistor T 5, the collector of the 6th switch transistor T 6,
The source electrode connection of the collector and the 9th switching tube M2 of three switch transistor Ts 3；The drain electrode of the 9th switching tube M2 and the second capacitor C2
Anode connection；The cathode of the emitter of 7th switch transistor T 7, the emitter of the 4th switch transistor T 4 and the second capacitor C2 connects
It connects；The emitter of the third switch transistor T 3 and the collector connection of the 4th switch transistor T 4.
7. buffer circuit as claimed in claim 4, which is characterized in that each switching tube is by 1 SiC MOSFET in M1~M2
1 diode of inverse parallel is constituted.
8. the buffer circuit as described in Claims 2 or 3 or 5 or 6, which is characterized in that capacitor C in the RCD buffer circuit
Calculation formula are as follows:
Wherein, IpFor IGBT collector current peak value, UCFor the rated operational voltage of capacitor in the RCD buffer circuit, tfFor institute
State the capacitor both end voltage rise time in RCD buffer circuit；
The calculation formula of resistance R in the RCD buffer circuit are as follows:
3RC=ton(min) (2)
Wherein, ton(min)For minimum IGBT turn-on time, C is capacitance size in the RCD buffer circuit；
Diode minimum pressure voltage chooses the load voltage value of IGBT in the RCD buffer circuit.
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| CN114094867A (en) * | 2021-11-24 | 2022-02-25 | 山东大学 | Fractal power converter and construction method thereof |
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| CN114094867A (en) * | 2021-11-24 | 2022-02-25 | 山东大学 | Fractal power converter and construction method thereof |
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| CN113922682A (en) * | 2021-12-13 | 2022-01-11 | 四川大学 | Direct cascade type modular multilevel converter of three-phase bridge circuit |
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