CN206260138U - The encapsulating structure of chip - Google Patents
The encapsulating structure of chip Download PDFInfo
- Publication number
- CN206260138U CN206260138U CN201621136784.1U CN201621136784U CN206260138U CN 206260138 U CN206260138 U CN 206260138U CN 201621136784 U CN201621136784 U CN 201621136784U CN 206260138 U CN206260138 U CN 206260138U
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- Prior art keywords
- chip
- circuit board
- encapsulating structure
- active region
- conductive
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Abstract
The utility model discloses a kind of encapsulating structure of chip, it is included：One chip, its front is provided with an active region and multiple brilliant pads, and multiple brilliant pad arrangements are located on an at least side of active region；One first circuit board, its first surface is provided with multiple first line layers, and multiple first line layers are connected respectively in each brilliant pad set on the front of chip；One insulating barrier, its covering be located on the first surface of first circuit board and the chip the back side；And a second circuit board, it has a first surface and a second surface, and first surface covering is located on the back side of the insulating barrier, and the second surface is provided with multiple second line layers, and multiple second line layers are used to be correspondingly connected to an outside printed circuit board (PCB)；Each first line layer electric connection corresponding with a conductive through holes are utilized respectively between each second line layer set on second circuit board set by first circuit board；The outside that each conductive through holes are located at around chip penetrates first circuit board, insulating barrier and second circuit board.
Description
Technical field
The utility model is related to a kind of encapsulating structure of chip, and espespecially a kind of outside setting around a chip is multiple
Conductive through holes (PTH, Plated Through Hole), so that each brilliant pad set on the front of the chip can pass through the plurality of
Conductive through holes (PTH) and be moved on the back side of the identification of fingerprint chip to be electrically connected with and on a printed circuit board (PCB),
So that active region set on the front of the chip can coordinate the printed circuit board (PCB) and realize the action function of active region.
Background technology
A chip is electrically connected with and installed in one in flip (flip-chip) mode using surface mount technology (SMT)
It is the common use configuration and prior art of current chip on printed circuit board (PCB) (PCB), it is now set on the front of the chip
Multiple brilliant pads (die pad) are in face of the printed circuit board (PCB) (PCB) and correspondingly can be electrically connected in the printed circuit board surface
On set circuit layer on each default contact.
But, when the front of a chip is provided with an active region (active area), such as identification of fingerprint chip, i.e., without
Method is electrically connected with and on a printed circuit board (PCB) (PCB) in existing flip (flip-chip) mode.Herein by Fig. 3
Shown chip 10 is illustrated as a example by an identification of fingerprint chip, but is not used to limit the utility model, the front of the chip 10
11 are provided with the multiple crystalline substances active region of pad 14 and (active area) 13, such as identification of fingerprint induction zone (sensor active
Area), the active region (identification of fingerprint induction zone) 13 to externally sensing one fingermark image (such as finger pressing or slide in fingerprint
Recognize on the surface of induction zone) and electronic signal is converted into, then printed electronic signal transmission to by the plurality of brilliant pad 14
Circuit board (printed circuit board (PCB) 60 as shown in Figure 2 and Figure 3) is carrying out finger print identification function or related operation.Due to the active region
(identification of fingerprint induction zone) 13 is externally sensing, therefore its surface must be towards the opposite side of the printed circuit board (PCB) (60), otherwise can be by
The printed circuit board (PCB) is covered, thus on the front 11 of the chip 10 multiple crystalline substance pads 14 cannot be electrically connected with and pacify in flip mode
On the printed circuit board (PCB) (60).
Although can be used between multiple crystalline substance pads 14 and printed circuit board (PCB) on the front 11 of the chip (identification of fingerprint chip) 10
Other junctures are electrically connected with, and such as connect (wire bond) mode using wire, but the wire for being used is from crystalline substance
The surface of pad 14 is drawn in arcuation and is introduced on the printed circuit board (PCB) at the back side 12 of the chip 10, therefore the peak of wire is relative
The front 11 of the chip 10 or 14 1 sections of height of brilliant pad thereon can be higher by, but the plurality of wire (wire) periphery can typically set again
An insulation outer jacket is put, is used to cover and protect those wires (wire), cause the encapsulating structure of the chip after completing
Overall total height enlarged relative, does not meet compact requirement.In addition, pacifying between the front 11 and the back side 12 of the chip 10
Row's multiple electrically conducts and uses silicon hole (TSV, Through Silicon Via), the design of such silicon hole (TSV) to be common in core
Piece encapsulate and related art in, but manufacturing process is relatively cumbersome and complexity, does not meet economic benefit.
From the foregoing, it will be observed that being provided with active region (such as identification of fingerprint in front to being provided with multiple crystalline substance pads 14 and on a front simultaneously
Induction zone) chip for, the need when structure and/or manufacturing process of the state of the art are difficult to meet actually used in fact
Ask, therefore in the encapsulation field of such chip, still suffer from it is further improved must property.
Utility model content
The utility model main purpose is to provide a kind of encapsulating structure of chip, and it is the outside around a chip
Multiple conductive through holes (PTH, Plated Through Hole) are set, wherein each conductive through holes (PTH) are located at around the chip
Outside and penetrate a first circuit board, an insulating barrier and a second circuit board so that set each brilliant pad energy in the chip front side
It is moved on the back side of the chip by the plurality of conductive through holes (PTH), to be electrically connected with and installed in a printed circuit board (PCB)
On so that active region (such as identification of fingerprint induction zone) set in the chip front side can coordinate the printed circuit board (PCB) and realization is acted on
Area's function (such as finger print identification function).
In order to achieve the above object, the encapsulating structure of the chip that the utility model is provided, it is included：One chip, it has
One front and a back side, are provided with an active region (such as identification of fingerprint induction zone) and multiple brilliant pads, multiple brilliant pad rows on the front
It is listed on an at least side of the active region；One first circuit board, it has a first surface and a second surface, this first
A part of region on surface is provided with multiple first line layers, and multiple first line layers are connected respectively in the chip front side
Set each brilliant pad, and the first circuit board extends out to the chip by the plurality of brilliant pad set on the front of the chip
Periphery；One insulating barrier, its covering is located on the first surface of the first circuit board and on the back side of the chip, and it is flat to form one
The whole back side；And a second circuit board, it has a first surface and a second surface, and wherein first surface covering is located at this
On the back side of insulating barrier, wherein the second surface is provided with multiple second line layers, and multiple second line layers are used to and outside
The one printed circuit board (PCB) correspondence being used in combination is connected, so that the chip can be arranged on printing electricity by the second circuit board
On the plate of road and realize be electrically connected with；Each first line layer wherein set by the first circuit board is set with the second circuit board
A conductive through holes with conductive coating are utilized respectively between each second line layer to be electrically connected with to correspond to；Wherein each conductive through holes
The outside that is located in around the chip simultaneously penetrates the first circuit board, the insulating barrier and the second circuit board.
In the embodiment of the utility model one, wherein the active region (such as identification of fingerprint induction zone) is located at the chip and (such as refers to
Line recognizes chip) positive middle section, the plurality of brilliant pad is arranged on a side of the active region or arranges and be located at the work
With on relative two side in area, so that the plurality of brilliant pad is on the front of the chip and near the area at the edge of the chip
Domain.
In the embodiment of the utility model one, the plurality of conductive through holes (PTH) are located on a side of the active region or set
On relative two side of the active region.
In the embodiment of the utility model one, wherein set active region on the front of the chip and the first circuit board
The first surface between a dielectric layer is further set, and the dielectric layer is arranged on the front of the chip and screens this completely
Active region but expose each brilliant pad.
In the embodiment of the utility model one, wherein first circuit board and the second circuit board is with flexible circuit board
(FPC) it is made.
In the embodiment of the utility model one, the wherein gross thickness of the encapsulating structure, i.e., by the second of the first circuit board
The thickness of the second line layer on surface to second surface of the second circuit board is equal to or less than 500 μm.
In the embodiment of the utility model one, wherein the positive size of the chip is length 9.8mm and width 4.18mm.
In the embodiment of the utility model one, wherein the positive full-size of the encapsulating structure is length 16mm and width
7mm, positive minimum dimension is length 11mm and width 4.5mm, can provide multiple choices in application.
Brief description of the drawings
The schematic cross-sectional view of the embodiment of encapsulating structure one of the chip that Fig. 1 is provided for the utility model；
The schematic cross-sectional view of another embodiment of encapsulating structure of the chip that Fig. 2 is provided for the utility model；
The frontage dimension of the encapsulating structure chips of the chip that Fig. 3 is provided for the utility model and its front of encapsulating structure
The schematic diagram of the maximum and embodiment of minimum dimension one.
Description of reference numerals：1- encapsulating structures；1a- encapsulating structures；1b- encapsulating structures；10- chips；11- fronts；12- is carried on the back
Face；13- active regions；The brilliant pads of 14-；20- first circuit boards；21- first surfaces；22- second surfaces；23- first line layer；30-
Insulating barrier；The 31- back sides；40- second circuit boards；41- first surfaces；42- second surfaces；The line layers of 43- second；50- conductions are worn
Hole；51- conductive coatings；60- printed circuit board (PCB)s；70- dielectric layers；80- scolding tin.
Specific embodiment
To make the utility model definitely full and accurate, hereby enumerate preferred embodiment and coordinate following schemes, this practicality is new
The structure and its technical characteristic of type are described in detail as after：
Embodiment as shown in Figure 1, the encapsulating structure 1 of the chip that the utility model is provided, it is included：One chip 10,
First circuit board 20, an insulating barrier 30 and a second circuit board 40；The wherein chip 10 illustrates by taking an identification of fingerprint chip as an example,
But it is not used to limit the utility model.
The chip 10 has a front 11 and a back side 12, wherein being provided with an active region on the front 11, (such as fingerprint is distinguished
Know induction zone) 13 and multiple crystalline substance pad 14, the plurality of brilliant pad 14 is arranged on an at least side of the active region 13.
The first circuit board 20 has a first surface 21 and a second surface 22, wherein at one of the first surface 21
Subregion is provided with multiple first line layers 23, and multiple first line layers 23 are connected respectively on the front 11 of the chip 10
Set each brilliant pad 14, as shown in figure 1, welded by the mode of scolding tin 80 but do not limited；The wherein first circuit board 20
Stretched out outside (right side in such as Fig. 1) to the chip 10 by the plurality of brilliant pad 14 set on the front 11 of the chip 10
Enclose.
The insulating barrier 30 covering is located on the first surface 21 of the first circuit board 20 and on the back side 12 of the chip 10,
And form a smooth back side 31.
The second circuit board 40 has a first surface 41 and a second surface 42, and the wherein first surface 41 covering is located at
On the back side 31 of the insulating barrier 30, wherein the second surface 42 is provided with multiple second line layers 43 (only with two the in figure
Two line layers 43 are represented), multiple second line layers 43 are connected to corresponding with the printed circuit board (PCB) 60 that outside is used in combination,
So that the chip 10 can be arranged on the printed circuit board (PCB) 60 by the second circuit board 40 (as shown in arrow A in Fig. 1) and
Realize being electrically connected with.
It is of the present utility model to be mainly characterized by：Each first line layer 23 set by the first circuit board 20 with this
Be utilized respectively between set each second line layer 43 on two circuit boards 40 one have conductive coating 51 conductive through holes (PTH,
Plated Through Hole) 50 electrical communication is corresponded to, so that each brilliant pad 14 set on the front 11 of the chip 10 can lead to
Cross the plurality of conductive through holes (PTH) 50 and be moved in the rear side of the chip 10, to be electrically connected with and be engaged installed in one
Printed circuit board (PCB) 60 on so that active region 13 set on the front 11 of the chip 10 can coordinate the printed circuit board (PCB) 60 and real
Existing active region function (such as finger print identification function)；Wherein each conductive through holes (PTH) 50 are located at outside around the chip 10 simultaneously
The first circuit board 20, the insulating barrier 30 and the second circuit board 40 are penetrated, as shown in figure 1, it is, the utility model is adopted
The plurality of conductive through holes (PTH) 50 not belong to silicon hole (TSV, Through Silicon common in the art
Via) structure kenel, therefore the utility model can effectively simplify the encapsulating structure 1 and its manufacturing process of the chip, to meet economy
Benefit.
In the embodiment of the utility model one, the active region 13 is located at the middle section in the front 11 of the chip 10, such as Fig. 3
It is shown.Additionally, the plurality of brilliant pad 14 be arranged on a side of the active region 13 (it is not shown, such as the brilliant pad of two rows in Fig. 3
A row in 14), or arrangement be located on relative two side of the active region 13, as shown in figure 3, so that the plurality of brilliant pad 14
On the front 11 of the chip 10 and near the region at the edge of the chip 10.Illustrated as a example by shown in Fig. 3, the chip (refers to
Line recognizes chip) 10 front 11 is provided with 14 brilliant pad (die pad) 14, and it is designed and is arranged in two rows and often arranges seven
Individual brilliant pad (die pad) 14, but be not used to limit the utility model, therefore wherein one brilliant pad (die pad) is only shown in Fig. 1
14, but be not used to limit the utility model.
Additionally, on the front 11 of the chip 10 set brilliant pad (the die pad) 14 of multiple arrangement (layout) mode, can be with
The action function (such as finger print identification function) of the chip 10 needs and makes different layouts, and such as in the embodiment shown in fig. 1, this
Each first line layer 23 and the arrangement of each conductive through holes (PTH, Plated Through Hole) 50 set by one circuit board 20 are located at
On one side of the active region (identification of fingerprint induction zone) 13 (right edge in such as Fig. 1), but it is not used to limit the utility model.
Additionally, in the embodiment shown in Figure 2, each first line layer 23 and each conduction set by the first circuit board 20 are worn
Hole (PTH, Plated Through Hole) 50 is arranged in relative two side of the active region (identification of fingerprint induction zone) 13
Upper (the left and right side in such as Fig. 2), but be not used to limit the utility model.
As shown in Figure 1 and Figure 2, set on the front 11 of the chip 10 active region 13 should with the first circuit board 20
One dielectric layer 70 can be further set between first surface 21, and the dielectric layer 70 be arranged on it is on the front 11 of the chip 10 and complete
Screen entirely and the active region 13 but expose each brilliant pad 14, wherein the dielectric layer 70 can't influence the effect of the active region 13 (such as to refer to
Line is recognized) function.
In the embodiment of the utility model one, the first circuit board 20 and the second circuit board 40 are 50 μm soft with thickness
Property circuit board (FPC, Flexible Printed Circuit) be made, with simplification encapsulating structure of the present utility model and its manufacture
Process.
In the embodiment of the utility model one, when the thickness of the chip (such as identification of fingerprint chip) 10 is 250 μm, and this
When one circuit board 20 is made with the second circuit board 40 with the flexible circuit board (FPC) that thickness is 50 μm, then the sheet for completing
The gross thickness of the encapsulating structure 1 of utility model, i.e., by the second surface 22 of the first circuit board 20 to the second circuit board 40
The thickness of the second line layer 43 on the second surface 42, can control equal to or less than 500 μm, as shown in Figure 1 and Figure 2.
Additionally, for the encapsulating structure 1 of the chip for enabling the utility model to provide expands its scope of application, such as convenient selection with
It is assembled on various electronic installations (such as mobile phone) with merging and is used, the positive size of the wherein chip 10 can be further configured to
Length 9.8mm and width 4.18mm；Wherein positive full-size (the encapsulating structure 1b in such as Fig. 3 of the encapsulating structure 1 of the chip
It is shown) length 16mm and width 7mm, and positive minimum dimension can be further configured to (as shown in encapsulating structure 1a in Fig. 3)
Length 11mm and width 4.5mm can be further configured to；It is, when the positive length and width of the encapsulating structure 1 of the chip
Degree is preset in a full-size (length 16mm × width 7mm) and a minimum dimension (length 11mm × width 4.5mm)
Between scope when, then can be convenient to various electronic installations (such as mobile phone) application when can make optimal selection.
Preferred embodiment of the present utility model is the foregoing is only, is merely illustrative for the utility model, rather than
Restricted；Those of ordinary skill in the art's understanding, can be right in the spirit and scope that the utility model claim is limited
It carries out many changes, modification, or even equivalent change, but falls within protection domain of the present utility model.
Claims (10)
1. a kind of encapsulating structure of chip, it is characterised in that include：
One chip, it has a front and a back side, and an active region and multiple brilliant pads, multiple brilliant pad arrangements are provided with the front
On an at least side of the active region；
One first circuit board, its a part of region with a first surface and a second surface, the first surface is provided with many
Individual first line layer is supplied, and multiple first line layers are connected respectively in each brilliant pad set on the front of the chip, and this
One circuit board is extended out to the periphery of the chip by the plurality of brilliant pad set on the front of the chip；
One insulating barrier, its covering is located on the first surface of the first circuit board and on the back side of the chip, and it is flat to form one
The whole back side；And
One second circuit board, it has a first surface and a second surface, and wherein first surface covering is located at the insulating barrier
The back side on, the wherein second surface is provided with multiple second line layers, and multiple second line layers are used to and outside one matches
The printed circuit board (PCB) correspondence that conjunction is used is connected, so that the chip is arranged on the printed circuit board (PCB) and real by the second circuit board
Now it is electrically connected with；
On each first line layer and the second circuit board wherein set by the first circuit board between set each second line layer
It is utilized respectively a conductive through holes with conductive coating to be electrically connected with to correspond to, so that each brilliant pad set on the front of the chip
The rear side of the chip is moved to by the plurality of conductive through holes to be electrically connected with and on the printed circuit board (PCB)；
Wherein each conductive through holes be located in the outside around the chip and penetrate the first circuit board, the insulating barrier and this second
Circuit board.
2. the encapsulating structure of chip according to claim 1, it is characterised in that the chip is an identification of fingerprint chip, and
The active region being located on the front of the chip is an identification of fingerprint induction zone.
3. the encapsulating structure of chip according to claim 1, it is characterised in that the active region is located at the positive of the chip
Middle section, the plurality of brilliant pad arrangement is located on a side of the active region or arrangement is located at relative two side of the active region
Bian Shang, so that the plurality of brilliant pad is on the front of the chip and near the region at the edge of the chip.
4. the encapsulating structure of chip according to claim 1, it is characterised in that the plurality of conductive through holes are located at the active region
A side on or be located on relative two side of the active region.
5. the encapsulating structure of chip according to claim 1, it is characterised in that the set effect on the front of the chip
One dielectric layer is further set between the first surface of area and the first circuit board.
6. the encapsulating structure of chip according to claim 5, it is characterised in that the dielectric layer is arranged on the front of the chip
It is upper and screen the active region but expose each brilliant pad completely.
7. the encapsulating structure of chip according to claim 1, it is characterised in that the first circuit board and the second circuit board
It is made with flexible circuit board.
8. the encapsulating structure of chip according to claim 1, it is characterised in that the gross thickness of the encapsulating structure, i.e., by this
The thickness of the second line layer on the second surface of first circuit board to second surface of the second circuit board is equal to or less than
500μm。
9. the encapsulating structure of chip according to claim 1, it is characterised in that the positive size of the chip is length
9.8mm and width 4.18mm.
10. the encapsulating structure of chip according to claim 1, it is characterised in that when the positive size of the chip is length
During degree 9.8mm and width 4.18mm, the positive full-size of the encapsulating structure is length 16mm and width 7mm, it is positive most
Small size is length 11mm and width 4.5mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621136784.1U CN206260138U (en) | 2016-10-19 | 2016-10-19 | The encapsulating structure of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621136784.1U CN206260138U (en) | 2016-10-19 | 2016-10-19 | The encapsulating structure of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206260138U true CN206260138U (en) | 2017-06-16 |
Family
ID=59023200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621136784.1U Active CN206260138U (en) | 2016-10-19 | 2016-10-19 | The encapsulating structure of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206260138U (en) |
-
2016
- 2016-10-19 CN CN201621136784.1U patent/CN206260138U/en active Active
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