CN206237440U - Communication protocol conversion circuit and communication protocol conversion equipment - Google Patents
Communication protocol conversion circuit and communication protocol conversion equipment Download PDFInfo
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- CN206237440U CN206237440U CN201621391073.9U CN201621391073U CN206237440U CN 206237440 U CN206237440 U CN 206237440U CN 201621391073 U CN201621391073 U CN 201621391073U CN 206237440 U CN206237440 U CN 206237440U
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- protocol conversion
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Abstract
The utility model is related to a kind of communication protocol conversion circuit, and it includes that CPU calculates control loop, loop control logic, communication protocol chip and power port and optical port communication loop;Power port and optical port communication loop include coaxial fitting, transformer, level switch module and fibre-optical splice;Loop control logic includes I/O mouthfuls, the 2nd I/O mouthfuls and a programmable logic cells;Coaxial fitting, transformer and level switch module are sequentially connected, level switch module also with the first I/O mouthfuls be connected, fibre-optical splice is connected with the 2nd I/O, and programmable logic cells connect the first I/O mouthfuls and the 2nd I/O mouthfuls respectively;Communication protocol chip connection CPU calculates control loop and programmable logic cells, and CPU calculated and connected between control loop and loop control logic.Using the utility model scheme, it is possible to achieve double switchings of optical port and power port, and the decoding chip of single channel is only needed, increased the flexibility of equipment and product cost can be reduced.
Description
Technical field
The utility model is related to technical field of electric power, and more particularly to a kind of communication protocol conversion circuit and communication protocol turn
Exchange device.
Background technology
2M data-interfaces are optical transport SDH (Synchronous Digital Hierarchy, SDH) networks
Minimum work unit, 2M is 2048kbit/S.Optical transmitter and receiver is specific by what is transmitted after the process for carrying out optical signal transmission terminates
Data carry out landing treatment, are typically all completed using 2M data-interfaces.
In data transmission service the performance test of 2M links be communication service debugging, open and troubleshooting important test
Project.The test numbers such as the bit error rate, dropout, ais alarm, frequency deviation test, clock characteristic, the time slot content analysis of 2M passages
According to being the important parameter index and technical basis for judging E1 data channel.In order to solve during live 2M lane testings, not jljl
The problem for managing interface conversion is gone forward side by side the test of line link loopback experiment, is typically necessary the conversion equipment using communication protocol.
In power system, with secondary equipment in power system (such as optical fiber differential protective and safety and stability control using 2M interfaces
Device processed) between communication protocol conversion equipment, or one kind of the interface only power port or optical port of general communication, or with
More decoding chip realizes power port and light port communications simultaneously, increases equipment cost and equipment sets dumb.
Utility model content
The purpose of this utility model is to provide a kind of communication protocol conversion circuit and communication Protocol Conversion equipment, Ke Yishi
Double switchings of existing optical port and power port, and the decoding chip of single channel is only needed, increased the flexibility of equipment and product can be reduced
Cost.
The purpose of this utility model is achieved through the following technical solutions:
A kind of communication protocol conversion circuit, including CPU calculate control loop, loop control logic, communication protocol chip with
And power port and optical port communication loop;
The power port and optical port communication loop include coaxial fitting, transformer, level switch module and fibre-optical splice;
The loop control logic includes the first I/O mouthful, the 2nd I/O mouthful and for may be programmed of controlling power port and light port communications to switch
Logic unit;
The coaxial fitting, the transformer and the level switch module are sequentially connected, the level conversion mould
Block also with the described first I/O mouthfuls be connected, the fibre-optical splice is connected with the 2nd I/O, programmable logic cells difference
Connect the described first I/O mouthfuls and the described 2nd I/O mouthfuls;The communication protocol chip is connected respectively by data/address bus and controlling bus
Meet the CPU and calculate control loop and the programmable logic cells, the CPU calculates control loop and the logic control is returned
Connected by data/address bus and controlling bus between road.
A kind of communication Protocol Conversion equipment, including cabinet and control board, communication protocol conversion circuit as described above
It is arranged in the control board, the control board is installed on the cabinet inside.
According to above-mentioned scheme of the present utility model, it includes that CPU calculates control loop, loop control logic, communication protocol
Chip and power port and optical port communication loop, the power port and optical port communication loop include that coaxial fitting, transformer, level turn
Mold changing block and fibre-optical splice, loop control logic include the first I/O mouthful, the 2nd I/O mouthfuls and for controlling power port and optical port to lead to
Believe the programmable logic cells of switching;Coaxial fitting, transformer and level switch module are sequentially connected, level switch module
Also with the first I/O mouthfuls be connected, fibre-optical splice is connected with the 2nd I/O, and programmable logic cells connect the first I/O mouthfuls and second respectively
I/O mouthfuls;Communication protocol chip connects CPU and calculates control loop and FPGA list respectively by data/address bus and controlling bus
Unit, CPU calculated and connected by data/address bus and controlling bus between control loop and loop control logic, so, it is only necessary to make
With the decoding chip (communication protocol chip) of single channel, optical port can be just solved using the programmable logic cells of loop control logic
With power port switching problem, increased the flexibility of equipment and product cost can be reduced.
Brief description of the drawings
Fig. 1 is the composition structural representation of the communication protocol conversion circuit in one embodiment of the present utility model;
Fig. 2 is the composition structural representation of the communication protocol conversion circuit in another embodiment of the present utility model;
Fig. 3 is the composition structural representation of the communication protocol conversion circuit in another embodiment of the present utility model;
Fig. 4 is the composition structural representation of the communication protocol conversion circuit in further embodiment of the present utility model;
Fig. 5 is the application schematic diagram of the communication Protocol Conversion equipment in one embodiment of the present utility model.
Specific embodiment
For the ease of understanding the utility model, the utility model is more fully retouched below with reference to relevant drawings
State.Preferred embodiment of the present utility model is given in accompanying drawing.But, the utility model can come in many different forms
Realize, however it is not limited to embodiment described herein.On the contrary, the purpose for providing these embodiments is made to of the present utility model
The understanding of disclosure is more thorough comprehensive.
Unless otherwise defined, all of technologies and scientific terms used here by the article is led with technology of the present utility model is belonged to
The implication that the technical staff in domain is generally understood that is identical.It is herein to be in term used in the description of the present utility model
The purpose of description specific embodiment, it is not intended that in limitation the utility model.Term as used herein " or/and " include
The arbitrary and all of combination of one or more related Listed Items.
It should be noted that when element is referred to as on " being fixed on " or " being arranged on " another element, it can be direct
On another element or it is connected on another element.When an element is referred to as " connection " another element, one
Element is referred to as " being connected " with another element, and it can be directly to another element or to be indirectly connected to this another
On individual element.Term as used herein " or/to " include the arbitrary and all of one or more related Listed Items
Combination.
It is shown in Figure 1, it is the composition structural representation of the communication protocol conversion circuit in one embodiment.Such as Fig. 1 institutes
Show, the communication protocol conversion circuit in the present embodiment, including CPU calculates control loop 101, communication protocol chip 102, logic control
Loop processed 103 and power port and optical port communication loop 104;
Power port and optical port communication loop 104 include coaxial fitting 1041, transformer 1042, level switch module 1043
With fibre-optical splice 1044;Loop control logic 103 includes the first I/O mouthfuls the 1032, the 2nd I/O mouthfuls 1033 and for controlling power port
The programmable logic cells 1031 switched with light port communications;
Coaxial fitting 1041, transformer 1042, level switch module 1043 are sequentially connected, level switch module 1043
Also with the first I/O mouthfuls 1032 be connected, fibre-optical splice 1044 with the 2nd I/O mouthfuls 1033 be connected, programmable logic cells 1031 are distinguished
Connect the first I/O mouthfuls 1032 and the 2nd I/O mouthfuls 1033;Communication protocol chip 102 is connected respectively by data/address bus and controlling bus
Meet CPU and calculate control loop 101 and loop control logic 103, CPU is calculated between control loop 101, loop control logic 103
Connected by data/address bus and controlling bus.
When implementing, above-mentioned programmable logic cells 1031 can by field programmable gate array (FPGA,
Field Programmable Gate Array) realize, but this is also not necessarily limited to, for example can also be by programmable logic device
(PLD, Programmable Logic Device) or other PLDs are realized.
Wherein, communication protocol chip 102 is used as communication decoding, when being decoded for 2M communications, the communication protocol chip 102
Can select 2M communication protocol chips.
Using the scheme in the present embodiment, in programmable logic cells 1031 according to CPU (Central Processing
Unit, central processing unit) control instruction of control loop 101 is calculated when being switched on the first I/O mouthfuls 1032, it is possible to achieve arrive
The switching of power port, second is switched in programmable logic cells 1031 according to the control instruction that CPU calculates control loop 101
At I/O mouthfuls 1033, it is possible to achieve to the switching of optical port, in this way, only needing to use decoding chip (the communication protocol chip of single channel
102) optical port and power port switching problem can just, be solved using the programmable logic cells of loop control logic, equipment is increased
Flexibility and product cost can be reduced.
At it in one embodiment, in order that communication protocol conversion circuit can be controlled by computer, as shown in Fig. 2
Communication protocol conversion circuit of the present utility model can also include Ethernet interface loop 201, and the Ethernet interface loop 201 has
Body can include the first Ethernet chip 2011, the second Ethernet chip 2014, the first isolating transformer 212, the
Two isolating transformers 2015, the first Ethernet interface 2013 and the second Ethernet interface 2016, the first Ethernet interface 2011, first are isolated
The Ethernet chip 2013 of transformer 2012 and first is sequentially connected, the second Ethernet interface 2014, the second isolating transformer
2015 and second Ethernet chip 2016 be sequentially connected, the first Ethernet chip 2011 and the second Ethernet interface core
Piece 2014 also connects CPU and calculates control loop 101 by data/address bus and controlling bus respectively.
Ethernet interface loop 201 in the present embodiment includes two socket loops, and a set of is the first Ethernet interface
2011st, the first isolating transformer 2012 and the first Ethernet chip 2013 composition interface loop, it is another set of be second with
Too the interface loop of network interface 2014, the second isolating transformer 2015 and the second Ethernet chip 2016 composition, specifically makes
Used time, usually using only a set of interface loop therein, another set of interface loop is used as spare interface loop.
Wherein in one embodiment, as shown in figure 3, CPU calculates control loop 101 includes process chip 301, RAM
(RamdomAccessMemory, effumability random access memory) chip 302, flash (Flash Memory, it is non-volatile
Memory) chip 303 and definite value flash304 chips, RAM chip 302, program flash chip 303 and definite value flash chip
304 are connected by data/address bus and controlling bus with process chip 301 respectively, and process chip 301 passes through data/address bus and control
Bus is connected with communication protocol chip 102.
In order to realize it is various communication and pair when etc. demand, as shown in figure 4, the communication protocol in one embodiment wherein
Change-over circuit, can also include the optical coupling isolator 401 being connected with programmable logic cells 1031, also including that can include and light
The RS-485 COM1s 402 of the connection of coupling isolator 401, pair when unit 403 or/and wireless communication unit 404.
Wherein, pair unit 403GPS can include GPS (Global Positioning System, global positioning system when
System) module or module during the Big Dipper (BeiDou Navigation Satellite, Beidou satellite navigation system) couple.Wirelessly
Communication unit includes WIFI communication units or/and bluetooth-communication unit.
Wherein in one embodiment, as shown in figure 4, loop control logic 103 can also include (the Joint of JTAG 1034
Test Action Group, joint test working group), JTAG 1034 and programmable logic cells 1031 are connected.JTAG 1034
It is the burning program of programmable logic cells 1031 and the interface of debugging routine, for realizing downloading and debugging principle figure and hard
Part description language writes code etc..
Wherein in one embodiment, as shown in figure 4, loop control logic 103 can also include clock chip 1035, when
Clock chip 1035 is connected with process chip 301, for realizing clock control.
Wherein in one embodiment, as shown in figure 4, communication protocol conversion circuit of the present utility model can be included with volume
Isolating switch power 405, isolating switch power 405 calculates control loop 101, communication protocol chip 102, logic with CPU respectively
Control loop 103 and power port and optical port communication loop 104 are connected, for calculating control loop 101, communication protocol core to CPU
Piece 102, loop control logic 103 and power port and optical port communication loop 104 are powered.Additionally, isolating switch power 405 can be with
With RS-485 COM1s 402, pair when unit 403 or/and wireless communication unit 404 be connected, for giving RS-485 communication ends
Mouthfuls 402, pair unit 403 or/and wireless communication unit 404 are powered when.
When communication protocol conversion circuit in the present embodiment is used, the input of isolating switch power 405 is usually to connect
220V alterating and direct currents are connect ,+5V the voltages of the output of isolating switch power 405 go to+3.3V after the voltage stabilizing of isolation strip and are connected to above-mentioned
On each loop or unit.
When implementing, CPU calculates control loop and typically calculates control loop from embedded type CPU, and logic control is returned
Fpga logic control loop is typically selected on road, and communication protocol chip typically selects 2M communication protocol chips.
It should be noted that a preferable examples of communication protocol conversion circuit of the present utility model are shown in Fig. 4
Structural representation.According to different Considerations, when communication protocol conversion circuit of the present utility model is implemented, can wrap
Containing the whole shown in Fig. 4, it is also possible to only comprising a portion shown in Fig. 4.
The model of each specific device in above-described embodiment can be:Embedded type CPU calculate control loop dominant frequency be
180MHz;The process chip of the model ARM9200 of process chip, the model K4S561632K of RAM chip, program flash
The model JS28F128J3D of chip, the model SST39VF1601 of definite value flash chip;The model of programmable logic cells
It is EP4CE40F23, the frequency of clock crystal oscillator is 32.768MHz;The Ω BNC of model 75 of coaxial fitting;The type of transformer
Number be PT-2003H, the model MYP2014B of level switch module;The model DM9161 of the first Ethernet chip,
Two Ethernet chip DM900A.It should be noted that these do not constitute the restriction to the utility model scheme.
Additionally, according to above-mentioned communication protocol conversion circuit of the present utility model, the utility model embodiment also provides one kind
Communication Protocol Conversion equipment, the communication Protocol Conversion equipment includes cabinet and control board, as above any one embodiment
Communication protocol conversion circuit is arranged in control board, and control board is installed on cabinet inside.
As shown in figure 5, the communication Protocol Conversion equipment of the utility model embodiment is when specifically used, it may be connected to one
On individual computer.The computer as the communication Protocol Conversion equipment of the utility model embodiment host computer, with the communication protocols
View conversion equipment is communicated.Wherein, the communication Protocol Conversion equipment of host computer sum is connected by Ethernet.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses several embodiments of the present utility model, and its description is more specific and detailed,
But therefore can not be interpreted as the limitation to utility model patent scope.It should be pointed out that for the common skill of this area
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
Protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (10)
1. a kind of communication protocol conversion circuit, it is characterised in that calculate control loop, loop control logic, communication protocols including CPU
View chip and power port and optical port communication loop;
The power port and optical port communication loop include coaxial fitting, transformer, level switch module and fibre-optical splice;It is described
Loop control logic includes I/O mouthfuls, the 2nd I/O mouthfuls and the FPGA for controlling power port and light port communications to switch
Unit;
The coaxial fitting, the transformer and the level switch module are sequentially connected, and the level switch module is also
With the described first I/O mouthfuls be connected, the fibre-optical splice is connected with the 2nd I/O, and the programmable logic cells are connected respectively
Described first I/O mouthfuls and the described 2nd I/O mouthfuls;The communication protocol chip connects institute respectively by data/address bus and controlling bus
State CPU and calculate control loop and the programmable logic cells, the CPU calculate control loop and the loop control logic it
Between connected by data/address bus and controlling bus.
2. communication protocol conversion circuit according to claim 1, it is characterised in that also including Ethernet interface loop, institute
State the Ethernet chip of Ethernet interface loop first, the second Ethernet chip, the first isolating transformer, the second isolation
Transformer, the first Ethernet interface and the second Ethernet interface, first Ethernet interface, first isolating transformer and first with
Too network interface chip is sequentially connected, second Ethernet interface, second isolating transformer and the second Ethernet chip
It is sequentially connected, first Ethernet chip and the second Ethernet chip are also total by data/address bus and control respectively
Line connects the CPU and calculates control loop.
3. communication protocol conversion circuit according to claim 1 and 2, it is characterised in that the CPU calculates control loop bag
Include process chip, RAM chip, program flash chip and definite value flash chip, the RAM chip, described program flash chip
It is connected with the process chip by data/address bus and controlling bus respectively with the definite value flash chip, the process chip
It is connected with the communication protocol chip by data/address bus and controlling bus.
4. communication protocol conversion circuit according to claim 1 and 2, it is characterised in that also including programmable being patrolled with described
The optical coupling isolator of volume unit connection, also including be connected with the optical coupling isolator RS-485 COM1s, pair when unit or
Person/and wireless communication unit.
5. communication protocol conversion circuit according to claim 4, it is characterised in that the loop control logic also includes
JTAG, the JTAG and the programmable logic cells are connected.
6. communication protocol conversion circuit according to claim 4, it is characterised in that the wireless communication unit includes WIFI
Communication unit or/and bluetooth-communication unit, unit includes module when GPS module or/and the Big Dipper pair at described pair.
7. communication protocol conversion circuit according to claim 3, it is characterised in that when the loop control logic also includes
Clock chip, the clock chip is connected with the process chip.
8. communication protocol conversion circuit according to claim 1, it is characterised in that described also including isolating switch power
Isolating switch power calculates control loop, the loop control logic, the communication protocol chip and institute with the CPU respectively
State power port and the connection of optical port communication loop.
9. communication protocol conversion circuit according to claim 1, it is characterised in that CPU calculates control loop for embedded
CPU calculates control loop, and the loop control logic is fpga logic control loop, and the communication protocol chip is 2M communication protocols
View chip.
10. a kind of communication Protocol Conversion equipment, it is characterised in that including cabinet and control board, such as claim 1 to 9 it
Communication protocol conversion circuit described in one is arranged in the control board, and the control board is installed in the cabinet
Portion.
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CN201621391073.9U CN206237440U (en) | 2016-12-16 | 2016-12-16 | Communication protocol conversion circuit and communication protocol conversion equipment |
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CN201621391073.9U CN206237440U (en) | 2016-12-16 | 2016-12-16 | Communication protocol conversion circuit and communication protocol conversion equipment |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109871346A (en) * | 2018-12-14 | 2019-06-11 | 北京理工导航控制科技有限公司 | One kind being based on High Speed Serial-network communication data conversion equipment |
CN114679221A (en) * | 2022-02-28 | 2022-06-28 | 广州广哈通信股份有限公司 | Communication device and equipment capable of configuring optical interface working mode |
-
2016
- 2016-12-16 CN CN201621391073.9U patent/CN206237440U/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109871346A (en) * | 2018-12-14 | 2019-06-11 | 北京理工导航控制科技有限公司 | One kind being based on High Speed Serial-network communication data conversion equipment |
CN114679221A (en) * | 2022-02-28 | 2022-06-28 | 广州广哈通信股份有限公司 | Communication device and equipment capable of configuring optical interface working mode |
CN114679221B (en) * | 2022-02-28 | 2024-03-08 | 广州广哈通信股份有限公司 | Communication device and equipment capable of configuring optical interface working mode |
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