CN210488282U - Multi-protocol data acquisition board card - Google Patents
Multi-protocol data acquisition board card Download PDFInfo
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- CN210488282U CN210488282U CN201921846505.4U CN201921846505U CN210488282U CN 210488282 U CN210488282 U CN 210488282U CN 201921846505 U CN201921846505 U CN 201921846505U CN 210488282 U CN210488282 U CN 210488282U
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- 238000002955 isolation Methods 0.000 claims description 5
- 230000005693 optoelectronics Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 description 9
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- 238000004458 analytical method Methods 0.000 description 1
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Abstract
The utility model discloses a multi-protocol data acquisition board card, which comprises a core board and an interface board; the core board comprises a PROFIBUS interface circuit, a CAN interface circuit, a digital input/output circuit, an indicating circuit, a mode setting circuit, a downloading debugging circuit and a first pin bank interface circuit which are respectively connected with the CPU circuit; the interface board comprises a 485 interface circuit, a DeviceNet interface circuit, a DC-DC circuit, an RJ45 interface circuit, a 4G \ LORA interface circuit and an analog input circuit which are respectively connected with the second pin header interface circuit; the first pin header interface circuit is connected with the pin header second interface circuit. The utility model discloses carry out data protocol conversion and real-time data acquisition to the equipment or the robot of the different data of different brands, solve equipment layer "data island" problem.
Description
Technical Field
The utility model relates to a data acquisition field especially relates to a multi-protocol data acquisition integrated circuit board.
Background
With the development of modern informatization, information technology promotes the rapid development of various industries, the requirements of industrial enterprises on informatization are gradually improved, and the rapid development of industrial informatization construction also occurs. Meanwhile, the field bus technology is rapidly developed in the industrial field, and besides a field device system comprising a bottom layer, a large number of comprehensive platforms and main control devices comprising an OPC interface service system, various robot communication interfaces, a PLC and the like are deployed in the field bus system. Information systems, robots, equipment and various comprehensive platforms deployed by industrial enterprises generate a large amount of information and data to form a plurality of data islands, which cannot be effectively used by the industrial enterprises. A large amount of data isolated islands bring many problems, including the fact that the running conditions of equipment such as robots cannot be known effectively in real time; when equipment such as a robot breaks down, timely alarming and early warning cannot be realized; data islands are numerous, so that management and integration are inconvenient; a large amount of core data is lost and large data analysis cannot be performed.
SUMMERY OF THE UTILITY MODEL
The defect that exists to above-mentioned prior art, the utility model provides a multi-protocol data acquisition integrated circuit board carries out data protocol conversion and real-time data acquisition to the equipment or the robot of the different data of different brands, solves equipment layer "data island" problem.
The utility model provides a multi-protocol data acquisition board card, its improvement lies in, including core plate and interface board;
the core board comprises a PROFIBUS interface circuit, a CAN interface circuit, a digital input/output circuit, an indicating circuit, a mode setting circuit, a downloading debugging circuit and a first pin bank interface circuit which are respectively connected with the CPU circuit;
the interface board comprises a 485 interface circuit, a DeviceNet interface circuit, a DC-DC circuit, an RJ45 interface circuit, a 4G \ LORA interface circuit and an analog input circuit which are respectively connected with the second pin header interface circuit;
the first pin header interface circuit is connected with the pin header second interface circuit.
Preferably, the core board includes a WIFI circuit; the WIFI circuit is connected with the CPU circuit.
Preferably, the RJ45 interface circuit includes a first RJ45 interface circuit and a second RJ45 interface circuit;
the first RJ45 interface circuit and the second RJ45 interface circuit are respectively connected with the first interface circuit.
Preferably, the CPU circuit includes a single chip microcomputer with a 32-bit Cotex M4 architecture.
Preferably, the DC-DC circuit comprises a DC-DC power supply; the voltage input range of the DC-DC power supply is 7-30V, and the current output range is 0-3A.
Preferably, the single chip microcomputer transmits signals to the digital input and output circuit through a photoelectric isolation circuit.
Preferably, the indicating circuit comprises an LED indicator light; the LED indicator light is connected with the output end of the single chip microcomputer.
The mode setting circuit includes a dial switch.
The technical scheme of the utility model wherein:
the utility model discloses collect the data of gathering and handle and present, support and the cloud system butt joint of more upper strata.
The utility model discloses an be equipped with the interface of different grade type, carry out unified form packing and sending through the equipment data to different agreement type interfaces, solved different equipment butt joint difficulty, data can not intercommunicate "data island" problem.
Drawings
Fig. 1 is the utility model discloses multiprotocol data acquisition integrated circuit board schematic diagram.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and by referring to preferred embodiments. It should be understood, however, that the numerous specific details set forth in the specification are merely set forth to provide a thorough understanding of one or more aspects of the present invention, which may be practiced without these specific details.
A schematic diagram of the multi-protocol data acquisition board card provided in this embodiment is shown in fig. 1, and specifically includes a core board and an interface board; the core board comprises a PROFIBUS interface circuit, a CAN interface circuit, a digital input/output circuit, an indicating circuit, a mode setting circuit, a downloading debugging circuit and a first pin bank interface circuit which are respectively connected with the CPU circuit; the interface board comprises a 485 interface circuit, a DeviceNet interface circuit, a DC-DC circuit, an RJ45 interface circuit, a 4G \ LORA interface circuit and an analog input circuit which are respectively connected with the second pin header interface circuit; the first pin header interface circuit and the pin header second interface circuit form a laminated structure in a pin header interface mode, and maintenance, expansion and replacement are facilitated. The core board of this embodiment may further include a WIFI circuit, and is connected to the CPU circuit.
Specifically, the method comprises the following steps:
the CPU circuit of the embodiment comprises a low-power consumption single chip microcomputer with a 32-bit Cotex M4 architecture. The CPU is used for encapsulating the acquired data, analyzing and converting the two different protocols and realizing the mutual data exchange of different interface protocol devices.
The PROFIBUS circuit of the present embodiment communicates with the peripheral device through the PROFIBUS interface of the peripheral device. The PROFIBUS chip carries out data interaction with the CPU circuit, and can select PROFIBUS terminal resistance through the dial switch to realize data acquisition and protocol conversion data interaction with peripheral equipment.
The mode setting circuit of this embodiment is composed of devices such as a dial switch and a resistor, and is connected to the CPU circuit, and 16 different operating modes can be configured by 4-way dial switch in the mode configuration, so as to implement different data protocol conversions, communication modes, operating modes, parameter configurations, and the like.
The download debugging circuit of the embodiment comprises 4 pin pins which are connected with the CPU circuit to realize program download and debugging information output.
The CAN circuit of this embodiment communicates with peripheral equipment through peripheral equipment's CAN interface, and the CAN circuit CAN realize CANopen master and slave station, when realizing the main website, CAN acquire other equipment data and conversion as the host computer, when as the slave station, CAN realize that different protocols convert the CANopen protocol into.
The WIFI circuit of this embodiment is connected with the CPU circuit, and the data that each interface gathered are uploaded to high in the clouds or local computer lab and are carried out data analysis.
The digital input and output circuit is composed of a photoelectric isolation chip and a triode device, is connected with the low-power singlechip through the photoelectric isolation circuit, and is sent to an interface of peripheral equipment through the digital input and output circuit after the singlechip sends an instruction. Or the digital input and output circuit transmits the acquired digital signals to the low-power-consumption singlechip through the photoelectric isolation circuit.
The indicating circuit of this embodiment includes the LED pilot lamp, and it is connected to the output of low-power consumption singlechip through resistance for indicating system operating condition and alarm information are reminded.
The 485 interface circuit of the embodiment communicates the signal of the low-power consumption singlechip with the peripheral equipment through the 485 interface of the peripheral equipment. Preferably, the 485 circuit can also realize Modbus RTU master and slave stations, when as the master station, can connect multichannel slave station equipment to communicate, when as the slave station, can convert other interface protocols into the MODBUS protocol, realizes the communication of different agreement equipment interconnection.
The RJ45 interface circuit of the present embodiment includes a first RJ45 interface circuit and a second RJ45 interface circuit; the first RJ45 interface circuit and the second RJ45 interface circuit are respectively connected with the second pin header interface circuit, wherein one path is used for transmitting acquired data to a server through the 4G \ LORA interface circuit, and the other path is used for communicating with other bottom-layer equipment. Each RJ45 circuit passes through PHY chip and peripheral equipment's RJ45 interface connection, and during the communication, RJ45 circuit both can realize data acquisition, also can send data to the high in the clouds simultaneously.
The DeviceNet circuit of the embodiment communicates with the CPU circuit through the second pin array interface circuit and the first pin array interface circuit, and the DeviceNet master-slave station can be used for communicating with other equipment and collecting data.
The 4G \ LORA interface circuit of the embodiment freely selects to use 4G or LORA, wherein under the condition of no 4G network coverage, other networks (WCDMA/TD-SCDMA/GSM) are automatically searched and switched.
The DC-DC circuit of this embodiment is used to supply power to the core board and the interface board, and mainly includes a DC-DC power supply, the voltage input range of which is 7-30V, and the current output range of which is 0-3A. Realizing wide input in industrial field.
The analog input circuit of the embodiment is used for converting the acquired analog signals into digital signals, and transmitting the digital signals to the low-power-consumption single chip microcomputer through the first pin header interface circuit and the second pin header interface circuit to acquire data. The device comprises a sampling resistor and a filter, wherein an AI1 channel supports acquisition of 4-20 mA analog quantity, an AI2 channel supports acquisition of 0-30V analog quantity, and the acquisition precision of AI1 is 1 per thousand; the acquisition precision of the channel AI2 voltage acquisition channel is 2 per mill;
the first pin header interface circuit and the second pin header interface circuit of the embodiment comprise pin header connectors and pin header connectors
The utility model discloses a various interfaces and replaceable interface board can pass through protocol conversion with the equipment of two kinds of different agreements and realize interconnection, can use an interface simultaneously with all kinds of equipment, the robot, the data of sensor etc. carry out acquisition analysis back and upload to the cloud platform through multiple mode and carry out big data analysis and fault model and build etc..
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. The multi-protocol data acquisition board card is characterized by comprising a core board and an interface board;
the core board comprises a PROFIBUS interface circuit, a CAN interface circuit, a digital input/output circuit, an indicating circuit, a mode setting circuit, a downloading debugging circuit and a first pin bank interface circuit which are respectively connected with the CPU circuit;
the interface board comprises a 485 interface circuit, a DeviceNet interface circuit, a DC-DC circuit, an RJ45 interface circuit, a 4G \ LORA interface circuit and an analog input circuit which are respectively connected with the second pin header interface circuit;
the first pin header interface circuit is connected with the pin header second interface circuit.
2. The board of claim 1, wherein the core board includes WIFI circuitry; the WIFI circuit is connected with the CPU circuit.
3. The board of claim 1, wherein the RJ45 interface circuits include a first RJ45 interface circuit and a second RJ45 interface circuit;
the first RJ45 interface circuit and the second RJ45 interface circuit are respectively connected with the first interface circuit.
4. The board of claim 3, wherein the CPU circuitry comprises a 32-bit Cotex M4 architecture single chip.
5. The board of claim 1, wherein the DC-DC circuit includes a DC-DC power supply;
the voltage input range of the DC-DC power supply is 7-30V, and the current output range is 0-3A.
6. The board of claim 4, wherein the single chip transmits signals to the digital input and output circuit through an optoelectronic isolation circuit.
7. The board card of claim 4, wherein the indicating circuit includes an LED indicator light;
the LED indicator light is connected with the output end of the single chip microcomputer.
8. The board of claim 4, wherein the mode setting circuit comprises a dial switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921846505.4U CN210488282U (en) | 2019-10-30 | 2019-10-30 | Multi-protocol data acquisition board card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921846505.4U CN210488282U (en) | 2019-10-30 | 2019-10-30 | Multi-protocol data acquisition board card |
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| Publication Number | Publication Date |
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| CN210488282U true CN210488282U (en) | 2020-05-08 |
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| CN201921846505.4U Expired - Fee Related CN210488282U (en) | 2019-10-30 | 2019-10-30 | Multi-protocol data acquisition board card |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116502585A (en) * | 2023-06-30 | 2023-07-28 | 中北大学 | Stacked high-capacity signal acquisition and transmission system and design method thereof |
-
2019
- 2019-10-30 CN CN201921846505.4U patent/CN210488282U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116502585A (en) * | 2023-06-30 | 2023-07-28 | 中北大学 | Stacked high-capacity signal acquisition and transmission system and design method thereof |
| CN116502585B (en) * | 2023-06-30 | 2023-08-29 | 中北大学 | Stacked high-capacity signal acquisition and transmission system and design method thereof |
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Effective date of registration: 20220407 Address after: Room 1703, 17 / F, building D, headquarters, No. 1188, fufu Road, Wuxing District, Huzhou City, Zhejiang Province 313000 Patentee after: Huzhou Yaobei Intelligent System Co.,Ltd. Address before: 17 / F, building D, headquarters Freeport, 1188 Qufu Road, Wuxing District, Huzhou City, Zhejiang Province, 313000 Patentee before: Huzhou Institute of International Innovation Harbin University of Technology Robot |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200508 |
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| CF01 | Termination of patent right due to non-payment of annual fee |