CN206162532U - Parallel arithmetic unit and concurrent operation system - Google Patents
Parallel arithmetic unit and concurrent operation system Download PDFInfo
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- CN206162532U CN206162532U CN201621053688.0U CN201621053688U CN206162532U CN 206162532 U CN206162532 U CN 206162532U CN 201621053688 U CN201621053688 U CN 201621053688U CN 206162532 U CN206162532 U CN 206162532U
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Abstract
The utility model discloses a parallel arithmetic unit and concurrent operation system to the row operation ware includes divider, first multiplier, second multiplier, first adder, second adder, first selector to the 5th selector, a data input mouth to the tenth data input mouth, a data output mouth to the 5th data output mouth, the concurrent operation system includes a plurality of parallel arithmetic unit, and connects through the mode realization communication of four -hole register set sharing between per two parallel arithmetic unit. Above -mentioned parallel arithmetic unit can operate by the corresponding addition subtraction multiplication and division of parallel execution, has improved the operational speed of arithmetic unit greatly, above -mentioned concurrent operation system has realized the data sharing between the different parallel arithmetic unit, and then has increaseed the data transmission flow, the calculation accuracy of many speed hardware at the real -time simulation in -process of ring has been guaranteed read and write the interactive method realization that can utilize corresponding data memory group to adopt the table tennis operation fashionably to external data to above -mentioned parallel computing ware in addition.
Description
Technical field
The utility model is related to Simulating technique in Electric Power System field, more particularly, it relates to a kind of parallel arithmetic unit and and
Row arithmetic system.
Background technology
With the popularization of intelligent grid, micro-capacitance sensor becomes the important component part of power system, its usual Jing power electronics
Current transformer, filter circuit and isolating transformer carry out grid-connected.To ensure safe operation of power system, power system real-time simulation is
Becoming carries out the important tool of power system experimental study, planning and designing, management and running and status safety assessment.
And during the real-time simulation of power system, it usually needs carry out substantial amounts of computing.It is used in prior art real
The device of computing, typically carries out successively every step calculating according to mathematic(al) representation during existing electric system simulation, such as mathematics
Expression formula is y=ax1+bx2, then by a, b, x1And x2Used as the input of arithmetic unit, arithmetic unit calculates successively ax1、bx2And
ax1+bx2, final output y.But, because during the real-time simulation of power system, the operand of needs is larger, if
Carry out in the manner described above calculating it successively, then arithmetic speed can be caused slower.
In sum, it is used to realize that the operational tool of calculation function is deposited in the simulation process of power system in prior art
In the problem that arithmetic speed is slower.
Utility model content
The purpose of this utility model is to provide a kind of parallel arithmetic unit and concurrent operation system, to solve prior art in use
In the problem that the arithmetic speed of the operational tool presence that calculation function is realized in the simulation process of power system is slower.
To achieve these goals, the utility model provides following technical scheme：
A kind of parallel arithmetic unit, including divider, the first multiplier, the second multiplier, first adder, the second addition
Device, first selector are to the 5th selector, the first data input port to the tenth data input port, the first data output to the 5th
Data output, wherein：
4th data input port and the 5th data input port are connected with the input of the divider, the divider it is defeated
Go out end to be connected with first selector, second selector and the first data output respectively；The input of the first selector with
6th data input port connects, and output end and the 7th data input port are connected with the first multiplier, the output of the first multiplier
End is connected respectively with third selector, the 4th selector and the 3rd data output；The input of third selector and the 9th number
Connect according to input port, output end is connected with the tenth data input port with the input of first adder, first adder it is defeated
Go out end to be connected with the 5th data output；The input of the 4th selector is connected with the 8th data input port, output end and the 5th
The output end of selector is connected with the input of second adder, and the output end of second adder connects with the 4th data output
Connect；The input of second selector is connected with the 3rd data input port, output end and the second data input port with the second multiplication
The input connection of device, it is equal with the first data input port while the output end of the second multiplier is connected with the second data output
It is connected with the input of the 5th selector.
Preferably, also including real-time voltage value input port, reference voltage input port, voltage comparator and voltage court verdict
Delivery outlet, wherein：
The real-time voltage value input port connects with the reference voltage input port with the input of the voltage comparator
Connect, the output end of the voltage comparator is connected with the voltage court verdict delivery outlet.
Preferably, it is also defeated including nonlinear data input port, line segment benchmark input port, non-linear decision device and line segment result
Outlet, wherein：
The nonlinear data input port and the line segment benchmark input port with the input of the non-linear decision device
Connection, nonlinear data of the non-linear decision device based on nonlinear data input port input is defeated with the line segment benchmark
The line segment benchmark of entrance input draws the line segment result of line segment residing for the nonlinear data, by the line segment result export to institute
State the line segment result delivery outlet of non-linear decision device connection.
Preferably, also include：
By the reading data control circuit that data to be calculated are obtained in corresponding data memory；
It is connected with the reading data control circuit, controls the data to be calculated by first data input port to the tenth
The total control circuit that data input port is input into.
Preferably, the institute that the total control circuit is connected respectively based on the control of corresponding selection benchmark with the total control circuit
State first selector to work to the 5th selector.
Preferably, also include：
By by the voltage court verdict delivery outlet being attached thereto respectively, the linear result delivery outlet, described first
Output data that data output to the 5th data output is obtained write corresponding data memory writes data control circuit.
Preferably, the corresponding data storage of the reading data control circuit includes two memory groups, and wherein each is deposited
Reservoir group includes that two are realized reading external number based on the memory group correspondence simulation step length using the exchange method of ping-pong operation
According to memory；The corresponding data storage of write data control circuit includes two memory groups, wherein each memory
Group includes that two are realized being write to external data based on the memory group correspondence simulation step length using the exchange method of ping-pong operation
Memory.
Preferably, also include：
By by the voltage court verdict delivery outlet being attached thereto respectively, the linear result delivery outlet, described first
The display that data output is shown to the output data that the 5th data output is obtained.
A kind of concurrent operation system, is applied to the real-time simulation of multi tate hardware in loop, including multiple as above any one institutes
The parallel arithmetic unit stated, wherein, realize leading to by way of four mouthfuls of register groups are shared between parallel arithmetic unit described in each two
News connection.
The utility model provide a kind of parallel arithmetic unit, the parallel arithmetic unit include divider, the first multiplier, second
Multiplier, first adder, second adder, first selector are to the 5th selector, the first data input port to the tenth data
Input port, the first data output to the 5th data output, wherein：4th data input port and the 5th data input port and institute
State the input connection of divider, the output end of the divider respectively with first selector, second selector and the first data
Delivery outlet connects；The input of the first selector is connected with the 6th data input port, output end and the 7th data input port
It is connected with the first multiplier, the output end of the first multiplier is defeated with third selector, the 4th selector and the 3rd data respectively
Outlet connection；The input of third selector is connected with the 9th data input port, and output end and the tenth data input port are with the
The input connection of one adder, the output end of first adder is connected with the 5th data output；The input of the 4th selector
End is connected with the 8th data input port, and output end is connected with the output end of the 5th selector with the input of second adder,
The output end of second adder is connected with the 4th data output；The input of second selector and the 3rd data input port connect
Connect, output end is connected with the second data input port with the input of the second multiplier, the output end of the second multiplier and second
Data output is connected with the first data input port while connection with the input of the 5th selector.By disclosure
Above-mentioned parallel arithmetic unit, can with the corresponding addition subtraction multiplication and division computing of executed in parallel, without the need for as in prior art to mathematical table
Every step calculating is carried out successively up to formula, thus, substantially increases the arithmetic speed of arithmetic unit；And the parallel arithmetic unit is used for into electric power
When in the simulation process of system, the requirement of concurrency in simulation process is disclosure satisfy that, effectively improve the calculating energy of real-time simulation
Power and simulation scale.The utility model additionally provides a kind of concurrent operation system, and the concurrent operation system includes multiple parallel fortune
Device is calculated, and realizes that communication connects by way of four mouthfuls of register groups are shared between parallel arithmetic unit described in each two.With it is above-mentioned
Parallel arithmetic unit is corresponding, the above-mentioned advantage that the concurrent operation system also has with parallel arithmetic unit, while can also realize
Data sharing between different parallel arithmetic units, and then increase data transfer throughput.
Description of the drawings
In order to be illustrated more clearly that the utility model embodiment or technical scheme of the prior art, below will be to embodiment
Or the accompanying drawing to be used needed for description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is embodiment of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, also
Other accompanying drawings can be obtained according to the accompanying drawing for providing.
A kind of the first structural representation for parallel arithmetic unit that Fig. 1 is provided for the utility model embodiment；
A kind of second structural representation of parallel arithmetic unit that Fig. 2 is provided for the utility model embodiment；
A kind of structural representation of concurrent operation system that Fig. 3 is provided for the utility model embodiment.
Specific embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment for being obtained, belongs to the scope of the utility model protection.
Fig. 1 is referred to, a kind of structural representation of parallel arithmetic unit of the utility model embodiment offer is provided,
In the structural representation, symbol represents divider for the device of ÷, and symbol represents first selector for the device of MUX1, and symbol is
The device of MUX2 represents second selector, and symbol represents third selector for the device of MUX3, and symbol is represented for the device of MUX4
4th selector, symbol represents the 5th selector for the device of MUX5, and symbol represents the first multiplier for the device of X1, and symbol is
The device of X2 represents the second multiplier, and symbol is that+1 device represents first adder, and symbol is that+2 device represents that second adds
Musical instruments used in a Buddhist or Taoist mass；In addition, corresponding two inputs of each selector are labeled with corresponding 0 and 1 in the figure, represent the selector by 1
One of them is chosen in corresponding input and 0 corresponding input as output, certainly, 0 and 1 sign in FIG is only this
A kind of specific embodiment of invention, can also according to actual needs carry out other settings, such as by 1 of same selector in Fig. 1
With 0 transposition etc., within protection scope of the present invention.Specifically, above-mentioned parallel fortune provided in an embodiment of the present invention
Calculating device can include divider, the first multiplier, the second multiplier, first adder, second adder, first selector to the
Five selectors, the first data input port to the tenth data input port, the first data output to the 5th data output, wherein：
4th data input port and the 5th data input port are connected with the input of divider, the output end difference of divider
It is connected with first selector, second selector and the first data output；The input of first selector and the 6th data input
Mouthful connection, output end and the 7th data input port are connected with the first multiplier, and the output end of the first multiplier is respectively with the 3rd
The connection of selector, the 4th selector and the 3rd data output；The input of third selector is connected with the 9th data input port,
Output end is connected with the tenth data input port with the input of first adder, the output end of first adder and the 5th data
Delivery outlet connects；The input of the 4th selector is connected with the 8th data input port, the output end of output end and the 5th selector
It is connected with the input of second adder, the output end of second adder is connected with the 4th data output；Second selector
Input be connected with the 3rd data input port, output end and the second data input port connect with the input of the second multiplier
Connect, while the output end of the second multiplier is connected with the second data output with the first data input port with the 5th selector
Input connection.
Wherein, the first data input port to the tenth data input port corresponds to the input port of data to be calculated, and corresponding
Obtained by first data output to the 5th data output is corresponded to and data to be calculated calculated using above-mentioned arithmetic unit
As a result delivery outlet.The determination of the corresponding divisor of divider and dividend can be determined according to actual needs, such as can be true
The data of fixed 5th data input port input are divisor, hereby it is achieved that the corresponding division arithmetic of the divider.By above-mentioned technology
Scheme, it is possible to achieve as shown in table 1 realizes 9 kinds of basic operations.Specifically, illustrated with arithmetic expression F=A*B+C
Bright, the input that can control the second multiplier is input into respectively A and B, and the 5th selector selects the number of the second multiplier output
That is A*B, the number is exported to second adder, and it is real by C to control another input input data of second adder
It is existing；For another example the data to be calculated of the first data input port to the tenth data input port correspondence input are expressed as into x0To x9, the
The data of one data output to the 5th data output correspondence output are expressed as y0To y4, when two of each selector
Input is indicated according to shown in Fig. 1, and third selector, the 4th selector, the 5th selector, first selector and second
When the input that selector is chosen corresponds to 110 ×× respectively, parallel arithmetic unit can simultaneously realize two signed magnitude arithmetic(al)s, i.e. y3=
x0+x7And y4=x8+x9, when two inputs of each selector are indicated according to shown in Fig. 1, and third selector, the 4th
When the input that selector, the 5th selector, first selector and second selector are chosen corresponds to 01101 respectively, parallel arithmetic unit
The cancellation computing (having the divider computing of identical operation data) of two colleagues, i.e. y can simultaneously be realized3=x7+x1·(x4/x3)
And y4=x9+x6·(x4/x3).In addition, compared with prior art, being realized using above-mentioned parallel arithmetic unit disclosed in the present application
When stating computing, without the need for carrying out every step calculating successively, and concurrent operation is can be achieved on, such as when the computing for realizing F=A*B+C*D
When, can pass through two multipliers simultaneously respectively realize the computing of A*B and C*D, and then be calculated F, it is parallel so as to pass through
Computing substantially increases arithmetic speed.
The basic operation of table 1
By above-mentioned parallel arithmetic unit disclosed in the present application, can be with the corresponding addition subtraction multiplication and division computing of executed in parallel, without the need for picture
Equally every step calculating is carried out successively to mathematic(al) representation in prior art, thus, substantially increase the arithmetic speed of arithmetic unit；And
When the parallel arithmetic unit is used in the simulation process of power system, the requirement of concurrency in simulation process is disclosure satisfy that, effectively
Improve the computing capability and simulation scale of real-time simulation.
A kind of parallel arithmetic unit that the utility model embodiment is provided, can also include real-time voltage value input port, benchmark
Voltage input, voltage comparator and voltage court verdict delivery outlet, wherein：
Real-time voltage value input port is connected with reference voltage input port with the input of voltage comparator, voltage comparator
Output end be connected with voltage court verdict delivery outlet.
The reference voltage and real-time voltage value input port being input into reference voltage input port by above-mentioned voltage comparator is defeated
The comparison of the real-time voltage value for entering can obtain corresponding voltage court verdict, and then can utilize the voltage in actual applications
Court verdict is controlled operation to corresponding equipment.Such as when voltage court verdict is that real-time voltage value is more than reference voltage,
Control corresponding disconnecting link to close, and when voltage court verdict is that real-time voltage value is less than or equal to reference voltage, control corresponding
Disconnecting link is opened, etc..It should be noted that voltage court verdict can be represented with 0 and 1, and when such as voltage court verdict is 1, table
Show real-time voltage value less than or equal to reference voltage, when voltage court verdict is 0, represent real-time voltage value more than reference voltage etc.,
Certainly other settings can also be according to actual needs carried out, within protection domain of the present utility model.
A kind of parallel arithmetic unit that the utility model embodiment is provided, can also include nonlinear data input port, line segment
Benchmark input port, non-linear decision device and line segment result delivery outlet, wherein：
Nonlinear data input port and line segment benchmark input port are connected with the input of non-linear decision device, non-linear to sentence
Certainly device is drawn non-based on the nonlinear data of nonlinear data input port input with the line segment benchmark that line segment benchmark input port is input into
The line segment result of line segment residing for linear data, the line segment result is exported to the line segment result output being connected with non-linear decision device
Mouthful.
For a nonlinear curve can be divided into multiple linearity ranges, above-mentioned nonlinear data can be with the embodiment of the present invention
For any point corresponding data on nonlinear curve, the data category can be determined based on linear reference by non-linear decision device
Which linearity range in nonlinear curve, referred to as line segment, and then corresponding line segment result is exported.Thus, without the need for
Staff is manually adjudicated according to nonlinear curve, and the respective devices that can be by above-described embodiment offer are automatically fast
The judging process for realizing nonlinear data of speed, improves efficiency, reduces cost of labor.
In addition, when a kind of parallel arithmetic unit provided in an embodiment of the present invention includes real-time voltage value input port, reference voltage
Input port, voltage comparator, voltage court verdict delivery outlet, nonlinear data input port, line segment benchmark input port, non-linear sentence
Certainly device, line segment result delivery outlet, read data control circuit, write data control circuit and its structural representation can during total control circuit
With as shown in Figure 2.
A kind of parallel arithmetic unit that the utility model embodiment is provided, can also include：
By the reading data control circuit that data to be calculated are obtained in corresponding data memory；
It is connected with data control circuit is read, controls data to be calculated and entered to the tenth data input port by the first data input port
The total control circuit of row input.
In the present embodiment, data control circuit can be read to the first data input port to the tenth by total control circuit control
Data input port carries out data input, specifically, as control each data to be calculated carried out by which data input port it is defeated
Enter, so as to pass through to control the input of data to be calculated, control different data inputs to be calculated to different arithmetic units, Jin Er
The computing with operation expression to be calculated is realized under the work of each arithmetic unit.In simple terms, total control circuit is according to fortune
Operator expression formula controls what data to be calculated were input into by different data input ports, so as to ensure that computing purpose is smoothly real
It is existing.
A kind of parallel arithmetic unit that the utility model embodiment is provided, total control circuit can be based on corresponding selection benchmark control
The first selector that system is connected respectively with total control circuit works to the 5th selector.
Wherein, benchmark is selected to set according to actual needs, in being stored in total control circuit, thus, total control circuit
In order to ensure the smooth realization of high in the clouds purpose, the work of first selector to the 5th selector can be controlled, i.e. control first is selected
The data that device to the 5th selector selects the input of which input in the data of input are selected, is illustrated as controlling with Fig. 1
Each selector exports 1 corresponding input or the 0 corresponding input conduct output that it is indicated, so as to realize corresponding meter
Calculate.
A kind of parallel arithmetic unit that the utility model embodiment is provided, can also include：
By by voltage court verdict delivery outlet, linear result delivery outlet, the first data output being attached thereto respectively extremely
The output data write corresponding data memory that 5th data output is obtained writes data control circuit.
Wherein, writing the corresponding data storage of data control circuit data storage corresponding with data control circuit is read can
With identical, it is also possible to different, specifically can be set according to actual needs, here is not limited.By writing Data Control electricity
Road can write corresponding data into corresponding data storage, obtain for staff or other devices, to a certain degree
On avoid the utility model embodiment offer a kind of parallel arithmetic unit gained operation result loss, it is ensured that data safety
Property.
A kind of parallel arithmetic unit that the utility model embodiment is provided, the corresponding data storage of the reading data control circuit
Device includes two memory groups, and wherein each memory group includes that two adopt table tennis based on the memory group correspondence simulation step length
The exchange method of operation realizes the memory of reading external data；The corresponding data storage of write data control circuit includes
Two memory groups, wherein each memory group include that two adopt ping-pong operation based on the memory group correspondence simulation step length
Exchange method realizes the memory to external data write.
Wherein, each memory group correspondence in two memory groups of data control circuit corresponding data memory is read different
Simulation step length, write in two memory groups of data control circuit corresponding data memory each memory group and also correspond to difference
Simulation step length, specifically, a group number-reading writes that data control circuit is corresponding to be deposited with one group according to control circuit correspondence memory group
Reservoir group one simulation step length of correspondence, another group number-reading writes data control circuit according to control circuit correspondence memory group and another group
Corresponding another simulation step length of correspondence memory group, specifically, can respectively correspond to the big step-length for arranging according to actual needs
And little step-length, and now when the calculating of simulation step length is realized, it is preferential to perform calculating corresponding with little step-length.This namely carry out
The multi tate during real-time simulation of multi tate hardware in loop in the real-time simulation of correspondence multi tate hardware in loop, and for memory
The use of group needs only to realize the read-write of data using memory group corresponding with current simulation step length.
In addition, the memory included in each memory group is specifically as follows RAM or register etc., specifically can basis
It is actually needed and is set.When the reading and write of data is realized using correspondence memory group, ping-pong operation can be adopted
Exchange method realization, realizes that digital independent is specifically described with any memory group, is deposited by this in emulation digital independent node
Memory (referred to as first memory) reading external data and store in reservoir group, when reaching next emulation digital independent knot
During point, using the data in first memory as data is activation to be calculated to reading data control circuit, and by another memory
(referred to as second memory) reading external data is simultaneously stored, by that analogy.The exchange method of above-mentioned ping-pong operation ensure that imitative
The accuracy calculated during true.In addition, data can also be realized in the above-mentioned numerical procedure of the utility model embodiment offer
Transmission inside parallel arithmetic unit, i.e., by reading data control circuit by the data for reading by transmission entrance input, the transmission
The data are write corresponding data storage by entrance with corresponding transmission outlet connection, transmission outlet by writing data control circuit
Device, so as to realize data transmitting without calculating inside parallel arithmetic unit.
A kind of parallel arithmetic unit that the utility model embodiment is provided, can also include：
By by voltage court verdict delivery outlet, linear result delivery outlet, the first data output being attached thereto respectively extremely
The display that the output data that 5th data output is obtained is shown.
Display is respectively with voltage court verdict delivery outlet, linear result delivery outlet, the first data output to the 5th number
Connect according to delivery outlet, after obtaining the data of above-mentioned each delivery outlet output, can be shown, thereby, it is possible to cause work
Making personnel can in time know the computing situation of parallel arithmetic unit, to realize respective operations.
The embodiment of the present invention additionally provides a kind of concurrent operation system, is applied to the real-time simulation of multi tate hardware in loop,
Concurrent operation system is illustrated in figure 3 comprising three parallel arithmetic unit (i.e. parallel arithmetic unit 1, parallel arithmetic unit 2 and concurrent operations
Device 3) when structural representation, corresponding with data control circuit the is write data storage of data control circuit is read in figure and is only included
Storage stack group and realized using RAM, wherein, RAM1 and RAM2 are corresponding for the reading data control circuit of parallel arithmetic unit 1
Memory group, RAM3 and RAM4 write the corresponding memory group of data control circuit for parallel arithmetic unit 1, and RAM5 and RAM6 is parallel
The reading data control circuit correspondence memory group of arithmetic unit 2, RAM7 and RAM8 writes data control circuit pair for parallel arithmetic unit 2
Answer memory group, RAM9 memory groups corresponding with the reading data control circuit that RAM10 is parallel arithmetic unit 3, RAM11 and RAM12
Data control circuit correspondence memory group is write for parallel arithmetic unit 3.The concurrent operation system can include multiple as above arbitrary
Parallel arithmetic unit described in, wherein, described in each two between parallel arithmetic unit by way of four mouthfuls of register groups are shared reality
Now communication connection.
Each four mouthfuls of register group can include 16 registers in wherein four mouthfuls register group sharing modes, each deposit
Device can be 64, and relative to the dual port RAM of traditional IP kernel, the shared communication modes of four adopted in the application mouthful register group add
Big data transfer throughput.Selection certainly for register can also according to actual needs carry out other settings, at this
Within bright protection domain.In addition to realize multi-rate simulating calculate, can make nonidentity operation device using different step-lengths with it is right
Data storage or other external equipments are answered to be communicated.And, in different parallel arithmetic units and realization and other concurrent operations
By reading data control circuit that it is included and data control circuit can be write realize during data interaction between device.With it is above-mentioned simultaneously
Row arithmetic unit is corresponding, the above-mentioned advantage that the concurrent operation system also has with parallel arithmetic unit, while can also realize not
With the data sharing between parallel arithmetic unit, and then increase data transfer throughput.
The foregoing description of the disclosed embodiments, enables those skilled in the art to realize or uses the utility model.
Various modifications to these embodiments will be apparent for a person skilled in the art, general original as defined herein
Reason can in other embodiments be realized in the case of without departing from spirit or scope of the present utility model.Therefore, this practicality is new
Type is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein and features of novelty phase
Consistent most wide scope.
Claims (9)
1. a kind of parallel arithmetic unit, it is characterised in that including divider, the first multiplier, the second multiplier, first adder,
Second adder, first selector are to the 5th selector, the first data input port to the tenth data input port, the first data output
Mouthful to the 5th data output, wherein：
4th data input port and the 5th data input port are connected with the input of the divider, the output end of the divider
It is connected with first selector, second selector and the first data output respectively；The input of the first selector and the 6th
Data input port connects, and output end and the 7th data input port are connected with the first multiplier, the output end point of the first multiplier
It is not connected with third selector, the 4th selector and the 3rd data output；The input of third selector is defeated with the 9th data
Entrance connects, and output end is connected with the tenth data input port with the input of first adder, the output end of first adder
It is connected with the 5th data output；The input of the 4th selector is connected with the 8th data input port, and output end is selected with the 5th
The output end of device is connected with the input of second adder, and the output end of second adder is connected with the 4th data output；
The input of second selector is connected with the 3rd data input port, output end and the second data input port with the second multiplier
Input connects, while the output end of the second multiplier is connected with the second data output and the first data input port is with the
The input connection of five selectors.
2. parallel arithmetic unit according to claim 1, it is characterised in that also including real-time voltage value input port, benchmark electricity
Pressure input port, voltage comparator and voltage court verdict delivery outlet, wherein：
The real-time voltage value input port is connected with the reference voltage input port with the input of the voltage comparator, institute
The output end for stating voltage comparator is connected with the voltage court verdict delivery outlet.
3. parallel arithmetic unit according to claim 2, it is characterised in that also including nonlinear data input port, line segment base
Quasi- input port, non-linear decision device and line segment result delivery outlet, wherein：
The nonlinear data input port and the line segment benchmark input port are connected with the input of the non-linear decision device,
Nonlinear data and the line segment benchmark input port of the non-linear decision device based on nonlinear data input port input
The line segment benchmark of input draws the line segment result of line segment residing for the nonlinear data, and the line segment result is exported to non-with described
The line segment result delivery outlet of linear decision device connection.
4. parallel arithmetic unit according to claim 3, it is characterised in that also include：
By the reading data control circuit that data to be calculated are obtained in corresponding data memory；
It is connected with the reading data control circuit, controls the data to be calculated by first data input port to the tenth data
The total control circuit that input port is input into.
5. parallel arithmetic unit according to claim 4, it is characterised in that the total control circuit is based on corresponding selection benchmark
Control works with the first selector that the total control circuit is connected respectively to the 5th selector.
6. parallel arithmetic unit according to claim 4, it is characterised in that also include：
By by the voltage court verdict delivery outlet being attached thereto respectively, the linear result delivery outlet, first data
Output data that delivery outlet to the 5th data output is obtained write corresponding data memory writes data control circuit.
7. parallel arithmetic unit according to claim 6, it is characterised in that the corresponding data of the reading data control circuit are deposited
Reservoir includes two memory groups, and wherein each memory group includes that two adopt table tennis based on the memory group correspondence simulation step length
The exchange method of pang operation realizes the memory of reading external data；The corresponding data storage bag of write data control circuit
Two memory groups are included, wherein each memory group includes that two adopt ping-pong operation based on the memory group correspondence simulation step length
Exchange method realize to external data write memory.
8. parallel arithmetic unit according to claim 3, it is characterised in that also include：
By by the voltage court verdict delivery outlet being attached thereto respectively, the linear result delivery outlet, first data
The display that delivery outlet is shown to the output data that the 5th data output is obtained.
9. a kind of concurrent operation system, it is characterised in that be applied to the real-time simulation of multi tate hardware in loop, including it is multiple as weighed
Profit requires the parallel arithmetic unit described in 1 to 8 any one, wherein, pass through four mouthfuls of registers described in each two between parallel arithmetic unit
The shared mode of group realizes communication connection.
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| CN201621053688.0U CN206162532U (en) | 2016-09-13 | 2016-09-13 | Parallel arithmetic unit and concurrent operation system |
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| CN201621053688.0U CN206162532U (en) | 2016-09-13 | 2016-09-13 | Parallel arithmetic unit and concurrent operation system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108196881A (en) * | 2017-12-01 | 2018-06-22 | 北京时代民芯科技有限公司 | A kind of fixed-point calculation accelerator module based on configurable technology |
| CN109426483A (en) * | 2017-08-30 | 2019-03-05 | Gsi 科技公司 | Concurrent multibit adder |
| CN109521977A (en) * | 2017-09-19 | 2019-03-26 | 卡西欧计算机株式会社 | Non-volatile memory medium, information processing method and electronic equipment |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109426483A (en) * | 2017-08-30 | 2019-03-05 | Gsi 科技公司 | Concurrent multibit adder |
| CN109426483B (en) * | 2017-08-30 | 2021-09-21 | Gsi 科技公司 | Concurrent multi-bit adder |
| CN109521977A (en) * | 2017-09-19 | 2019-03-26 | 卡西欧计算机株式会社 | Non-volatile memory medium, information processing method and electronic equipment |
| CN109521977B (en) * | 2017-09-19 | 2022-04-26 | 卡西欧计算机株式会社 | Nonvolatile storage medium, information processing method, and electronic device |
| CN108196881A (en) * | 2017-12-01 | 2018-06-22 | 北京时代民芯科技有限公司 | A kind of fixed-point calculation accelerator module based on configurable technology |
| CN108196881B (en) * | 2017-12-01 | 2020-10-16 | 北京时代民芯科技有限公司 | Fixed-point operation acceleration unit based on configurable technology |
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