CN206147116U - Novel mining dual -frenquency of high accuracy swashs electric receiver - Google Patents
Novel mining dual -frenquency of high accuracy swashs electric receiver Download PDFInfo
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- CN206147116U CN206147116U CN201621226935.2U CN201621226935U CN206147116U CN 206147116 U CN206147116 U CN 206147116U CN 201621226935 U CN201621226935 U CN 201621226935U CN 206147116 U CN206147116 U CN 206147116U
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Abstract
The utility model discloses a novel mining dual -frenquency of high accuracy swashs electric receiver includes signal conditioning module, AD conversion module, FPGA processing module, DSP processing module, display module and power module, power module gives signal conditioning module, AD conversion module, FPGA processing module, DSP processing module and display module power supply, FPGA processing module respectively with AD conversion module, DSP processing module and display module are connected, AD conversion module still is connected with signal conditioning module, has stability, the interference killing feature has the improvement of very big degree, the height of high accuracy is arrived in the ability simultaneous acquisition, low two frequency 's sharp voltage, and it is high, the synchronous precision of low frequency signals is high, the efficient advantage of data processing.
Description
Technical field
This utility model belongs to mineral detection technical field, and specifically a kind of novel high-precision is mining, and Dual-frequency Ip Method is received
Machine.
Background technology
At present, with the development of national economy, country is increasing to the demand of mineral resources.Through surveying for decades
Visit, the exploration environment of mineral resources becomes more and more severe, and the exploration to mineral resources is also more and more difficult.Therefore, raising is surveyed
The work efficiency of spy equipment, precision, safety, can greatly reduce unnecessary economic loss, improve the accuracy of exploration.
Mineral detection can be divided into time domain IP and frequency domain induced polarization method, and time domain IP actually studies mineral
The time dependent method of secondary electric potential after induced polarization, because the detecting devices of time domain IP is heavy, can hand over
Logical convenient plains region application, but the mountain area poor in grounding requirement, interference is big and orographic condition is poor, IP of time domain is just very
It is difficult.At present, mineral detection is all that, using frequency domain induced polarization method, frequency domain swashs electricity and IP of time domain in reflection underground polarization body
Ability on be suitable.But frequency domain swash electricity do not need power-off change different frequency electric current, detecting devices become light and flexible,
The advantages of improving capacity of resisting disturbance.In mineral detection frequency domain induced polarization method：(1) frequency variation method, the method is the feelings in not power-off
Under condition, using twice respectively supply low-frequency current and high frequency electric measure high and low frequency voltage difference, and calculate regarding Swing frequency, but this
The method of kind can not simultaneously collect the sharp piezoelectric voltage of two kinds of frequencies；(2) double-frequency induced polarization method, this method by Central South University what after
Although a kind of Dual-frequency Ip Method receiver of geophysical exploration method of kind academician's utility model can realize two kinds of frequency signals
Synchronous reception, and collect sharp piezoelectric voltage signal accordingly, but due to synchronization accuracy not enough, the conversion accuracy of a/d converter
It is low, a series of factor such as the interference of effect of induced polarization and electromagnetic coupling effect, the ability of data processing of processor are weaker,
Cause that the precision of relevant device is low, data-handling capacity is weak, a series of phenomenons such as data are unstable occur.
Utility model content
The purpose of this utility model is, to overcome the deficiencies in the prior art, and to provide a kind of mining double frequency of novel high-precision and swash
Electric receiver, the stability of the receiver, capacity of resisting disturbance have significant improvement, can collect simultaneously it is high-precision it is high,
The sharp piezoelectric voltage of low two kinds of frequencies, and high and low frequency signal synchronization accuracy is high, data-handling efficiency is high.
Realizing the technical scheme of this utility model purpose is：
A kind of novel high-precision is mining Dual-frequency Ip Method receiver, including Signal-regulated kinase, AD conversion module, FPGA process
Module, DSP processing modules, display module and power module, power module to Signal-regulated kinase, AD conversion module, FPGA at
Reason module, DSP processing modules and display module are powered, FPGA processing modules respectively with AD conversion module, DSP processing modules and aobvious
Show that module connects, AD conversion module is also connected with Signal-regulated kinase.
The effect of described Signal-regulated kinase is that the sharp piezoelectric voltage weak signal to receiving carries out pretreatment and obtains pure
Signal.
The effect of described AD conversion module is to be AD converted the pretreated purified signal of Signal-regulated kinase, will
Signal is converted into digital signal.
The effect of described FPGA processing modules is the digital signal data caching to A/D module conversion, and will have been cached
Batch data is sent to DSP processing modules, and to the normal control of modules.
The effect of described DSP processing modules is the data that the transmission of FPGA processing modules comes to be carried out at corresponding algorithm
Reason, then sends again the data obtained after algorithm process to FPGA processing modules, through the control of FPGA processing modules, finally
Data are shown in display module.
The connection of described FPGA processing modules and DSP processing modules is to be bi-directionally connected.
Described Signal-regulated kinase further include frontend amplifying circuit, high-frequency filter circuit, low-frequency filter circuit, 4/
8 multiplexers, detection integrating circuit and programme-controlled gain amplifying circuit；Frontend amplifying circuit respectively with high-frequency filter circuit and low
Frequency filter circuit one end connects, and 4/8 multiplexer is connected respectively with high-frequency filter circuit and the low-frequency filter circuit other end, and 4/
8 multiplexers are also connected with detection integrating circuit, and detection integrating circuit is also connected with programme-controlled gain amplifying circuit；Wherein：
The effect of described frontend amplifying circuit is that the faint sharp piezoelectric voltage signal to receiving is amplified process；Institute
The effect of the high-frequency filter circuit stated is to extract pure high frequency in the two-frequency signal in the sharp piezoelectric voltage signal from after amplification to swash
Piezoelectric voltage signal；The effect of described low-frequency filter circuit is extracted in the two-frequency signal in the sharp piezoelectric voltage signal from after amplification
Pure low frequency swashs piezoelectric voltage signal；The effect of 4/8 described multiplexer is to swash piezoelectric voltage signal to high and low frequency respectively to enter
Row control, realization switches to public output to one of 4 road signals；The effect of described detection integrating circuit is respectively to through 4/
The IP effects and EM effects interference signal that high and low frequency after 8 multiplexers is swashed in piezoelectric voltage signal carries out Processing for removing；It is described
Programme-controlled gain amplifying circuit effect be to detection integrating circuit process after signal carry out programme-controlled gain amplification, after making amplification
Signal processed by AD conversion module.
Described AD conversion module is 24 high accuracy delta sigma type A/D converters, 32 high accuracy delta sigma type A/D conversions
At least one in device.
The chip of 4/8 described multiplexer is ADG509FB chips.
Described frontend amplifying circuit chip selects accurate, twin-channel instrument amplifier AD526 chips.
The detection of described detection integrating circuit selects circuit from OPA2227 amplifier chips, and integrating circuit selects OPA602
Amplifier chip.
The beneficial effects of the utility model are：A kind of novel high-precision is mining Dual-frequency Ip Method receiver, by high accuracy, high
The substantial amounts of data of resolution acquisition, the complete secondary electric potential data for obtaining the high and low frequency after subsurface mineral induced polarization,
And data processing is fast and effectively carried out by FPGA processor and dsp processor, complete high frequency potential difference amplitude Δ VH, it is low
Frequency potential difference amplitude Δ VL, regarding Swing frequency FS, low frequency apparent resistivity ρSL, high frequency apparent resistivity ρSHEtc. the measurement of multinomial physical parameter
And display, from different electrically angle analysis with portray subsurface mineral structure.There is provided for accurate assaying species and content can
The data message for leaning on, has significant improvement with stability, capacity of resisting disturbance, can collect simultaneously high-precision high and low
The sharp piezoelectric voltage of two kinds of frequencies, and high and low frequency signal synchronization accuracy is high, the high advantage of data-handling efficiency, so as to improve exploration
Efficiency and reduce inaccurate causing unnecessary economic loss.
Description of the drawings
A kind of novel high-precisions of Fig. 1 are mining Dual-frequency Ip Method receiver system block diagram；
Fig. 2 Signal-regulated kinase block diagrams；
In figure, the 1. display module 5.DSP process of Signal-regulated kinase 2.AD modular converters 3.FPGA processing modules 4.
The multiplexer of 9. low-frequency filter circuit of module 6. power module, 7. frontend amplifying circuit, 8. high-frequency filter circuit 10.4/8
The programme-controlled gain amplifying circuit of 11. detection integrating circuit 12..
Specific embodiment
This utility model is further elaborated with reference to the accompanying drawings and examples, but is not to limit of the present utility model
It is fixed.
Embodiment
As shown in figure 1, a kind of mining Dual-frequency Ip Method receiver of novel high-precision, including Signal-regulated kinase 1, AD conversion mould
Block 2, FPGA processing modules 3, DSP processing modules 5, display module 4 and power module 6, power module 6 to Signal-regulated kinase 1,
AD conversion module 2, FPGA processing modules 3, DSP processing modules 5 and display module 4 are powered, and FPGA processing modules 3 turn respectively with AD
Mold changing block 2, DSP processing modules 5 and display module 4 connect, and AD conversion module 2 is also connected with Signal-regulated kinase 1, wherein：
The effect of described Signal-regulated kinase 1 is that the sharp piezoelectric voltage weak signal to receiving carries out pretreatment and obtains pure
Signal；The effect of described AD conversion module 2 is to be AD converted the pretreated purified signal of Signal-regulated kinase 1, will
Signal is converted into digital signal；The effect of described FPGA processing modules 3 is that the digital signal data to A/D module conversion 2 delays
Deposit, and the batch data for having cached is sent to into DSP processing modules 5, and to the normal control of modules；Described
The effect of DSP processing modules 5 is that the data for transmitting FPGA processing modules 3 carry out corresponding algorithm process, then by algorithm
The data obtained after process send again FPGA processing modules 3 to, and through the control of FPGA processing modules 3, most at last data are showing
Show in module 4 and show.
Connection between described FPGA processing modules 3 and DSP processing modules 5 is to be bi-directionally connected.
As shown in Fig. 2 described Signal-regulated kinase 1 further includes frontend amplifying circuit 7, high-frequency filter circuit 8, low
Frequency filter circuit 9,4/8 multiplexer 10, detection integrating circuit 11 and programme-controlled gain amplifying circuit 12；Frontend amplifying circuit 7
Be connected with high-frequency filter circuit 8 and the one end of low-frequency filter circuit 9 respectively, 4/8 multiplexer 10 respectively with high-frequency filter circuit 8
Connect with the other end of low-frequency filter circuit 9,4/8 multiplexer 10 is also connected with detection integrating circuit 11, detection integrating circuit
11 are also connected with programme-controlled gain amplifying circuit 12；Wherein：
The effect of described frontend amplifying circuit 7 is that the faint sharp piezoelectric voltage signal to receiving is amplified process；
The effect of described high-frequency filter circuit 8 is to extract pure high frequency in the two-frequency signal in the sharp piezoelectric voltage signal from after amplification
Sharp piezoelectric voltage signal；The effect of described low-frequency filter circuit 9 is in the two-frequency signal in the sharp piezoelectric voltage signal from after amplification
Extract pure low frequency and swash piezoelectric voltage signal；The effect of 4/8 described multiplexer 10 is to swash piezoelectric voltage to high and low frequency respectively
Signal is controlled, and realization switches to public output to one of 4 road signals；The effect of described detection integrating circuit 11 is difference
The IP effects and EM effect interference signals swashed to the high and low frequency after 4/8 multiplexer 10 in piezoelectric voltage signal disappears
Except process；The effect of described programme-controlled gain amplifying circuit 12 is to carry out program control increasing to the signal after the process of detection integrating circuit 11
Benefit is amplified, and makes the signal after amplification for being processed by AD conversion module 2.
Described AD conversion module 2 adopts 24 high accuracy delta-sigma type A/D converters.
The chip of 4/8 described multiplexer 10 selects ADG509FB chips.
Described frontend amplifying circuit 7 selects accurate, twin-channel instrument amplifier AD526 chips.
The detection of described detection integrating circuit 11 selects circuit from OPA2227 amplifier chips, and integrating circuit is selected
OPA602 amplifier chips.
When using, the premenstrual end amplifying circuit 7 of sharp piezoelectric voltage signal to receiving is amplified after process, through high frequency filter
Wave circuit 8 and low-frequency filter circuit 9, then selection output is carried out to the sharp piezoelectric voltage signal of high and low frequency through 4/8 multiplexer 10
Control, eliminates afterwards the impact of IP effects and EM effect interference signals into detection integrating circuit 11, finally puts to programme-controlled gain
Big circuit 12, to signal programme-controlled gain amplification is carried out；Purified signal after amplification is by using 24 high accuracy, high-resolution
The a/d converter module 2 of delta-sigma type A/D converter, the high frequency potential difference amplitude Δ V after conversionHWith low frequency potential difference amplitude Δ VL
Data are passed in FPGA processing modules, under the control of Jing FPGA processing modules 3, batch data are transferred to into DSP processing modules 5
In, according to regarding Swing frequency computing formula：Low frequency calculation formula of apparent resistivity：Wherein K is
Electrode coefficient, ILFor low frequency power supply electric current；High calculation formula of apparent resistivity again and again：Wherein K is electrode coefficient,
IHFor high supply current again and again.Algorithm process by more than, calculates regarding good fortune frequency, low frequency apparent resistivity, high frequency apparent resistance
Rate.Finally by the control of FPGA module 3, high frequency potential difference, low frequency potential difference after DSP processing modules 5 are processed, regarding amplitude-frequency
Rate, apparent resistivity data show in display module 4.
Claims (9)
1. the mining Dual-frequency Ip Method receiver of a kind of novel high-precision, it is characterised in that including Signal-regulated kinase, AD conversion mould
Block, FPGA processing modules, DSP processing modules, display module and power module, power module is to Signal-regulated kinase, AD conversion
Module, FPGA processing modules, DSP processing modules and display module are powered, FPGA processing modules respectively with AD conversion module, DSP
Processing module and display module connect, and AD conversion module is also connected with Signal-regulated kinase.
2. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 1, it is characterised in that described signal is adjusted
The effect of reason module is that sharp piezoelectric voltage weak signal to receiving carries out pretreatment and obtains purified signal.
3. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 1, it is characterised in that described AD conversion
The effect of module is to be AD converted the pretreated purified signal of Signal-regulated kinase, converts the signal into digital signal.
4. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 1, it is characterised in that at described FPGA
The effect of reason module is the digital signal data caching to A/D module conversion, and the batch data for having cached is sent to into DSP
Processing module, and to the normal control of modules.
5. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 1, it is characterised in that at described DSP
The effect of reason module is that the data that the transmission of FPGA processing modules comes are carried out into corresponding algorithm process, then will be obtained after algorithm process
To data send FPGA processing modules to again, through the control of FPGA processing modules, most at last data show in display module
Illustrate and.
6. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 1, it is characterised in that at described FPGA
Connection between reason module and DSP processing modules is to be bi-directionally connected.
7. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 1, it is characterised in that described AD conversion
Module is at least one in 24 high accuracy delta sigma type A/D converters, 32 high accuracy delta sigma type A/D converters.
8. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 1, it is characterised in that described signal is adjusted
Reason module further includes frontend amplifying circuit, high-frequency filter circuit, low-frequency filter circuit, 4/8 multiplexer, detection integration
Circuit and programme-controlled gain amplifying circuit；Frontend amplifying circuit is connected respectively with high-frequency filter circuit and low-frequency filter circuit one end,
4/8 multiplexer is connected respectively with high-frequency filter circuit and the low-frequency filter circuit other end, 4/8 multiplexer also with detection
Integrating circuit connects, and detection integrating circuit is also connected with programme-controlled gain amplifying circuit；Wherein：
The effect of described frontend amplifying circuit is that the faint sharp piezoelectric voltage signal to receiving is amplified process；Described
The effect of high-frequency filter circuit is to extract pure high frequency in the two-frequency signal in the sharp piezoelectric voltage signal from after amplification to swash electricity electricity
Pressure signal；The effect of described low-frequency filter circuit is to extract pure in the two-frequency signal in the sharp piezoelectric voltage signal from after amplification
Low frequency swash piezoelectric voltage signal；The effect of 4/8 described multiplexer is to swash piezoelectric voltage signal to high and low frequency respectively to control
System, realization switches to public output to one of 4 road signals；The effect of described detection integrating circuit is respectively to through more than 4/8
The IP effects and EM effects interference signal that high and low frequency after path multiplexer is swashed in piezoelectric voltage signal carries out Processing for removing；Described
The effect of programme-controlled gain amplifying circuit is to carry out programme-controlled gain amplification to the signal after the process of detection integrating circuit, after making amplification
Signal for being processed by AD conversion module.
9. the mining Dual-frequency Ip Method receiver of novel high-precision according to claim 8, it is characterised in that more than described 4/8
The chip of path multiplexer is ADG509FB chips；The chip of described frontend amplifying circuit amplifies for accurate, twin-channel instrument
Device AD526 chips；The detecting circuit of described detection integrating circuit uses OPA2227 amplifier chips, integrating circuit to be transported with OPA602
Put chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621226935.2U CN206147116U (en) | 2016-11-15 | 2016-11-15 | Novel mining dual -frenquency of high accuracy swashs electric receiver |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621226935.2U CN206147116U (en) | 2016-11-15 | 2016-11-15 | Novel mining dual -frenquency of high accuracy swashs electric receiver |
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| CN206147116U true CN206147116U (en) | 2017-05-03 |
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| CN201621226935.2U Expired - Fee Related CN206147116U (en) | 2016-11-15 | 2016-11-15 | Novel mining dual -frenquency of high accuracy swashs electric receiver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106646619A (en) * | 2016-11-15 | 2017-05-10 | 桂林电子科技大学 | Novel high-precision mine double-frequency induced polarization receiver |
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2016
- 2016-11-15 CN CN201621226935.2U patent/CN206147116U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106646619A (en) * | 2016-11-15 | 2017-05-10 | 桂林电子科技大学 | Novel high-precision mine double-frequency induced polarization receiver |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20170503 Termination date: 20191115 |