CN206058696U - Realize the FPGA brassboards of independent debugging checking - Google Patents

Abstract

This utility model provides a kind of FPGA brassboards for realizing independent debugging checking.FPGA brassboards in the present embodiment include：Toggle switch, key switch, fpga chip, the peculiar input block for being input into control signal, the screen output unit that the internal data that control signal is produced is run for display control signal and fpga chip are installed on FPGA brassboards；Toggle switch and key switch are electrically connected with fpga chip on FPGA brassboards respectively；Fpga chip is electrically connected with peculiar input block and screen output unit on FPGA brassboards respectively.User can be made to see the control signal of oneself input, can also allow user that the debugging result of self-designed FPGA circuitry is directly intuitively seen on FPGA brassboards, so as to realize that effectively debugging checking is independently carried out on one piece of FPGA brassboard, and complete to verify and debug without computer, reduce the cost needed for debugging.

Description

Realize the FPGA brassboards of independent debugging checking

Technical field

This utility model is related to digital integrated electronic circuit technology, more particularly to a kind of FPGA experiments for realizing independent debugging checking Plate.

Background technology

With the continuous improvement of integrated circuit technology, field programmable gate array (Field-Programmable Gate Array, referred to as：FPGA) as special IC (Application-Specific Integrated Circuit, letter Referred to as：ASIC a kind of semi-custom circuit) in field and occur, the logical block of FPGA and connection can be according to the needs of user And change, so the logic function required for FPGA can be completed.

In FPGA teaching systems, completed after circuit written in code using hardware program language (verilog or VHDL), it is past It is past to rest on the software emulation stage.Upper plate is verified and the means of debugging are weaker, is preferably at most loaded into circuit code After FPGA brassboards, FPGA brassboards are connected to equipped with joint test working group (Joint Test by JTAG cables Action Group, referred to as：JTAG) the computer of debugging software, then by software on computers to being burnt to FPGA experiments Design circuit on plate is verified and is debugged.

When by the way the design circuit on FPGA brassboards being verified and debugged, needs have come by computer Into checking and the process debugged, realize that cost is larger, and independently cannot carry out effectively debugging on FPGA brassboards verifying.

Utility model content

This utility model embodiment provides a kind of FPGA brassboards for realizing independent debugging checking, to overcome in prior art Needs are completed to verify by computer and realize that cost is big caused by debugging, it is impossible to independent effectively to be adjusted on FPGA brassboards The technical problem of test card.

This utility model first aspect provides a kind of FPGA brassboards for realizing independent debugging checking, including：Described Be provided with FPGA brassboards toggle switch, key switch, on-site programmable gate array FPGA chip, for being input into control signal Peculiar input block, for showing that the input control signal and the fpga chip are run in the control signal produces The screen output unit of portion's data；

The toggle switch and the key switch are electrically connected with the fpga chip on the FPGA brassboards respectively；

The fpga chip is single with the peculiar input block and screen output respectively on the FPGA brassboards Unit's electrical connection.

Optionally, the fpga chip is built-in with for debugging the FPGA circuits to be debugged verified.

Optionally, also include：Controller；The controller respectively with the fpga chip, the peculiar input block and The screen output unit electrical connection.

Optionally, the controller is central processor CPU.

Optionally, the input block is matrix keyboard.

Optionally, the screen output unit is display screen.

Optionally, the input block and the screen output unit are to have input and the touch of output function concurrently to show Screen.

Optionally, the screen output unit is LED or charactron.

FPGA brassboards in the present embodiment include：FPGA brassboards include：Dial-up is installed on FPGA brassboards to open Pass, key switch, on-site programmable gate array FPGA chip, the peculiar input block for being input into control signal, for showing The screen output unit of the internal data that control signal and fpga chip operation control signal are produced；Toggle switch and key switch Electrically connected with fpga chip on FPGA brassboards respectively；Fpga chip on FPGA brassboards respectively with peculiar input block and Screen output unit is electrically connected.Wherein, by be provided with FPGA brassboards and meanwhile can show input control signal and The screen output unit of the internal data that fpga chip operation control signal is produced, so as to user not only can be made to see certainly The control signal of oneself input, can also allow user that self-designed FPGA circuitry is directly intuitively seen on FPGA brassboards Debugging result, so as to realize it is independent effectively debugging checking is carried out on one piece of FPGA brassboard, and come without computer Into checking and debugging, the cost needed for debugging is reduced.

Description of the drawings

In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, below will be to embodiment Or accompanying drawing to be used is briefly described needed for description of the prior art, it should be apparent that, drawings in the following description are Some embodiments of the present utility model, for those of ordinary skill in the art, in the premise for not paying creative labor Under, can be with according to these other accompanying drawings of accompanying drawings acquisition.

Fig. 1 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure one；

Fig. 2 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure two；

Fig. 3 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure three；

Fig. 4 show screen display unit display schematic diagram；

Fig. 5 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure four.

Specific embodiment

It is to make purpose, technical scheme and the advantage of this utility model embodiment clearer, new below in conjunction with this practicality Accompanying drawing in type embodiment, is clearly and completely described to the technical scheme in this utility model embodiment, it is clear that retouched The embodiment stated is a part of embodiment of this utility model, rather than the embodiment of whole.Based on the enforcement in this utility model Example, the every other embodiment obtained under the premise of creative work is not made by those of ordinary skill in the art are belonged to The scope of this utility model protection.

This utility model provides a kind of FPGA brassboards for realizing independent debugging checking, is provided with FPGA brassboards Toggle switch, key switch, on-site programmable gate array FPGA chip, the peculiar input block for being input into control signal, use The screen output unit of the internal data produced in display control signal and fpga chip operation control signal；And toggle switch and Key switch is electrically connected with fpga chip on FPGA brassboards respectively；Fpga chip is defeated with peculiar respectively on FPGA brassboards Enter unit and the electrical connection of screen output unit.Wherein, screen output unit includes but is not limited to the display function of touch display screen, Peculiar input block includes but is not limited to the touch function of touch display screen, matrix keyboard etc..Screen output unit can show The control signal that user is input into by peculiar input block, and the inside that fpga chip operation control signal is produced can be shown Data.The effect that debugging checking is just can reach using single FPGA brassboards is so reached, and the FPGA brassboards need not Computer is connected by cable, the independent debugging effect for departing from computer is reached.And easy-to-use, friendly debugging checking circle can be provided Face.

The technical solution of the utility model is described in detail with specifically embodiment below.These are specific below Embodiment can be combined with each other, for same or analogous concept or process may be repeated no more in certain embodiments.

Fig. 1 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure one, as shown in figure 1, the FPGA brassboards that the present embodiment is provided include：Toggle switch is installed on the FPGA brassboards 1st, key switch 2, on-site programmable gate array FPGA chip 3, the peculiar input block 4 for being input into control signal, for showing Show the screen output unit 5 of the internal data that input control signal and the operation control signal of fpga chip 3 are produced；

Wherein, toggle switch 1 and key switch 2 are electrically connected with fpga chip 3 on FPGA brassboards respectively；

Fpga chip 3 is electrically connected with peculiar input block 4 and screen output unit 5 on above-mentioned FPGA brassboards respectively Connect.

Specifically, after user designs FPGA circuit 31 to be debugged by hardware program language, by the FPGA circuitry It is loaded onto in fpga chip 3, during fpga chip 3 runs, some internal datas can be produced, now, because being right The fpga chip 3 performs checking and the process debugged, what needs were produced during going to gather the operation control signal of fpga chip 3 Internal data, and the internal data is shown on the screen of screen display unit, to allow user to see self-designed FPGA Whether the function of circuit is realized.

For screen display unit：

Above-mentioned internal data is the signal in the FPGA circuits to be debugged 31 of the needs observation interested to user, this A little signals are the current state of the state machine in fpga chip 3, the value latched in internal register, or latch in internal register Value of the value after one or more levels logical gate operations.

That is, above-mentioned screen output unit 5 can show the internal data of collection, there is provided very friendly observation circle Face, and the unbounded size system of the internal data to gathering.

Preferably, the internal data of above-mentioned collection is the binary number of multidigit, and what above-mentioned screen output unit 5 showed is The number of M systems corresponding with the binary number of the multidigit for collecting, wherein M are similarly the positive integer more than or equal to 1.

And FPGA brassboards are typically connected to the computer equipped with JTAG debugging softwares by JTAG cables by prior art, FPGA circuitry to being burned onto on FPGA brassboards by way of emulating on computers is verified and is debugged again.By above-mentioned When mode is verified and debugged to the FPGA circuitry on FPGA brassboards, need the debugging software of specialty is installed on computers, And final debugging result is embodied in the form of waveform.

Due to the final waveform for showing, the only people with stronger Professional knowledge can just understand, and user utilizes FPGA When brassboard is tested and debugged, due to lacking Professional knowledge, it is impossible to the very clear result that debugging is known by waveform, That is, debugging software cannot intuitively represent the function needed for whether the circuit designed with hardware program language has reached.And this The internal data for collecting can be shown as the data that user is apparent that the M systems for seeing in utility model, so as to can To make the more clear blunt function of seeing self-designed FPGA circuitry of user whether correct, user's body is effectively increased Test.

For example, the internal data of collection be 2 binary numbers 11, and screen output unit 5 arrange to show For metric number, then what is shown on screen output unit 5 is just 3, such that it is able to being that observer more intuitively can see Whether the internal data of operation is correct.

In prior art, although also including input block and output unit on FPGA brassboards, user passes through Input block input control signal cannot show from output unit, that is, user cannot see oneself be input into What information fpga chip 3 is, so as to user cannot learn oneself be input into fpga chip 3 control signal whether just Really, finally, if debugging result is not inconsistent with expection, then user clearly cannot be known as oneself input error causes , or really as self-designed FPGA circuitry is wrong and caused.

Based on the problems referred to above, in this utility model, when user is by toggle switch 1, key switch 2 or specific input list When unit is to the input control signal of fpga chip 3, screen output unit 5 can show the control signal of user input, now, use Person can intuitively see the control signal of oneself input, when user sees oneself input error, can be opened by dial-up Close 1, key switch 2 or specific input block goes to change the content being input into, so as to avoid in prior art, user cannot The input of oneself is can be visually seen, so as to produce due to user input error and caused debugging result and expection be not inconsistent Situation occurs, and so as to avoid user erroneous judgement, effectively improves Consumer's Experience.

Fig. 2 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure two, as shown in Fig. 2 in a kind of attainable mode of the present utility model, be also built-in with above-mentioned fpga chip 3 for The FPGA circuits to be debugged 31 of debugging checking.

In a kind of attainable mode, behind the good FPGA of user design circuit 31 to be debugged, the circuit is burned onto In fpga chip 3.

And during the fpga chip 3 for referring in above-described embodiment runs, some internal datas can be produced, specifically For：During built-in FPGA circuits 31 to be debugged run in fpga chip 3, some internal datas can be produced.

Fig. 3 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure three, as shown in figure 3, in another kind of attainable mode of the present utility model, above-mentioned FPGA brassboards also include：Control Device 6, the controller 6 are electrically connected with fpga chip 3, peculiar input block 4 and screen output unit 5 respectively.

In actual applications, above-mentioned controller 6 can (Central Processing Unit be simple for central processing unit Referred to as：CPU).

Continue according to above-mentioned example：

After user designs FPGA circuitry by hardware program language, and the FPGA circuitry is loaded onto into fpga chip In 3, to complete the checking and debugging of FPGA circuits to be debugged 31, during FPGA circuitry runs, can produce in some Portion's data, now, because being to perform checking and the process debugged to FPGA circuits 31 to be debugged, in this utility model Fpga chip 3 or controller 6 can go to gather FPGA 31 runnings of circuit to be debugged in the internal data that produces, and will collection Internal data send to the screen output unit 5 being arranged on same FPGA brassboards, when screen output unit 5 is received After the internal data that fpga chip 3 or controller 6 send, just the internal data is shown on screen, to allow user to see certainly Whether the function of the FPGA circuits to be debugged 31 of oneself design is realized.

Specifically, when fpga chip 3 or controller 6 collect what is produced after FPGA circuits 31 to be debugged run control signal The internal data, after internal data, can be converted to the number of some system shown required by screen display unit first, so After determine the corresponding dot matrix of the number, and the dot matrix is sent to into screen display unit as output signal, so that screen output is single Unit 5 shows the internal data for collecting according to the output signal.

Continue according to above-mentioned example, it is assumed that screen output unit 5 arrange for be shown for metric number, when After the internal data of fpga chip 3 or the collection of controller 6 is 2 binary numbers 11, fpga chip 3 or controller 6 can be by two The 11 of system are converted to metric 3, then as shown in figure 3, as screen display unit is made up of 7 row, 4 row, 28 dot matrix, By lighting different points, screen output unit 5 can show different numbers, now, screen output unit 5 it is to be shown for 3, adjust Examination unit just determines that screen output unit 5 will show 3, and that is accomplished by lighting second point of the 2nd row and the 3rd point, the third line the Three points, second point of fourth line and the 3rd point, the 3rd point of fifth line, the 6th point of row the 3rd and the 3rd point, then Those data as output signal, are sent to screen output unit 5 by fpga chip 3 or controller 6, when screen output unit 5 After receiving the output signal, according to point to be lighted indicated in data signal, corresponding point is lighted, so as to defeated in screen Go out.

Further, the toggle switch 1 or key switch 2 shown in Fig. 1 is normal on FPGA brassboards of the prior art Input equipment, can also include other input equipments commonly used in the prior art, for example certainly：Button switch.

By taking toggle switch 1 as an example, user can realize input by toggle switch, and now, user is opened by dial-up The control signal for closing 1 input can be directly to above-mentioned FPGA circuits to be debugged 31.In this kind of implementation, in above-described embodiment Fpga chip 3 or controller 6 can not possess function control signal being input into FPGA circuits to be debugged 31, but FPGA cores Piece 3 or controller 6 are provided with controlling to include in screen user by the control signal that toggle switch 1 or key switch 2 are input into The function of curtain display unit.

For example, have 3 toggle switch 1 on FPGA brassboards, toggle switch 1 push first position interval scale input for 1, Toggle switch 1 push the input of second position interval scale for 0, if first toggle switch 1 and second toggle switch 1 are dialled To first position, and the 3rd toggle switch 1 pushes the second position, then the control that now user is input into by toggle switch 1 Signal processed is 110, namely is now directly input into circuit 31 to be debugged to FPGA by 110, to carry out to FPGA circuits to be debugged 31 Debugging and verification.

For peculiar input block 4：

Fig. 5 show the structural representation of the FPGA brassboards of the independent debugging checking of realization of this utility model embodiment offer Figure four, as shown in figure 5, in the present embodiment, above-mentioned peculiar input block 4 can include following several implementations：

In the first implementation, the peculiar input block 4 in this utility model can be matrix keyboard, screen output Unit 5 is display screen (not shown).

This kind of matrix keyboard and display screen, similar to the mobile phone for having button before.

In second implementation, the peculiar input block 4 and screen output unit 5 in this utility model is defeated to have concurrently Enter the touch display screen with output function.

In above two implementation, as matrix keyboard is needed by scanning come key range, to confirm user The data of input, and gather the coordinate of user touch point to recognize touch area to confirm after touch display screen needs initialization The data of user input, so user is cannot be used directly for by the control signal that matrix keyboard or touch display screen are input into The input that FPGA circuits to be debugged 31 can be received, now, can pass through fpga chip 3 or controller 6 and user is passed through matrix The control signal of keyboard or touch display screen input is converted to the related code of the receivable input of FPGA circuits 31 to be debugged.

Optionally, user can be input into many secondary control signals by above-mentioned peculiar input block 4, now fpga chip 3 or controller 6 many secondary control signals that peculiar input block 4 is input into are combined as the input signal of a multidigit, and will combination The input signal of multidigit be converted to the signal that can make the identification of FPGA circuits 31 to be debugged, and send to be debugged to FPGA Circuit 31.

For example：By taking matrix keyboard as an example, the digital 1 corresponding button in user presses matrix keyboard for continuous 3 times, and press Lower OK keys, represent that input is completed, and the control signal being now input into fpga chip 3 or controller 6 is respectively 1,1 and 1, now, Three control signals can be combined the input of the N systems number 111 for obtaining 3 for fpga chip 3 or controller 6, Fpga chip 3 or controller 6 can be converted into corresponding binary number after N systems number 111 is obtained, also, and to be sent to FPGA to be debugged Circuit 31, so that FPGA circuits 31 to be debugged run the binary number.

Screen output unit 5 in this utility model can also be light emitting diode (Light Emitting Diode, letter Referred to as：) or charactron LED.

The FPGA brassboards of the independent debugging checking of realization in the present embodiment include：Dial-up is installed on FPGA brassboards Switch, key switch, on-site programmable gate array FPGA chip, the peculiar input block for being input into control signal, for showing Show the screen output unit of the internal data that control signal and fpga chip operation control signal are produced；Toggle switch and button are opened Pass is electrically connected with fpga chip on FPGA brassboards respectively；Fpga chip on FPGA brassboards respectively with peculiar input block Electrically connect with screen output unit.Wherein, by being provided with FPGA brassboards while the control signal of input can be shown The screen output unit of the internal data that control signal is produced is run with fpga chip, so as to see not only can user The control signal of oneself input, can also allow user directly intuitively to see that self-designed FPGA is electric on FPGA brassboards The debugging result on road, so as to realize that effectively debugging checking is independently carried out on one piece of FPGA brassboard, and comes without computer Complete to verify and debug, reduce the cost needed for debugging, and improve teaching efficiency.

Input mode of the prior art can only be input into simple several binary signals substantially, and such as, user is dialled A upper toggle switch 1, FPGA circuits to be debugged 31 bring into operation, and dial the lower toggle switch 1, and FPGA circuits to be debugged 31 stop Operation.

Can also be acted on by those toggle switch 1 simultaneously by tens toggle switch 1 of somewhat complex design in prior art Input block same FPGA experiments are not encapsulated in into also in the binary data of input several to tens, but current product On plate so that user easily can be used.

And peculiar input block 4 is encapsulated in the FPGA brassboards of the independent debugging checking of realization that this utility model is provided In FPGA brassboards, and in real time the control signal that user is input into can be shown by screen display unit, and energy Deleted in input error, just the input method on much like existing smart mobile phone, so input mode very hommization.

That is, this utility model provides very friendly inputting interface (input of similar smart mobile phone), the peculiar input Unit 4 can cause user to be input into the data of any digit, for example：The binary data of 32.

And in this utility model, user can see the data of oneself input.

As the FPGA brassboards of the independent debugging checking of the realization provided in this utility model can show debugging in real time As a result, therefore, the FPGA brassboards of the independent debugging checking of the realization that this utility model is provided can also complete debugging breakpoints, equally may be used To complete the debugging of other functions, such as：Realize that the FPGA brassboards of independent debugging checking can be input into multigroup Arbitrary Digit in real time The input signal of value so that can be the input signal of the FPGA feeding of circuit 31 any numbers to be debugged, work(is fully verified with this The correctness of energy.

For example, FPGA circuits 31 to be debugged are a circuit for realizing 32 bit addition and subtraction functions, in existing skill In art due to be difficult input 32 bits, therefore often can only in FPGA circuits 31 to be debugged built-in several groups 32 two enter Number processed, only verifies when being loaded onto on FPGA brassboards whether several groups of built-in 32 bit phase plus and minus calculations are correct, And cannot verify that other data are mutually added and subtracted.

The FPGA brassboards of the independent debugging checking of realization provided by this utility model can then be input into any number With this, two source operands, verify whether any 32 bit phase plus and minus calculation is correct, fully checking FPGA electricity to be debugged The correctness of 31 addition and subtraction function of road.

It should be noted that the FPGA circuits 31 to be debugged as user described in this utility model is self-designed FPGA circuitry.

Further, in actual applications, debugging can be divided into artificial debugging and upper plate debugging.

Artificial debugging need not be loaded into user self-designed FPGA circuitry on fpga chip.It is to make The step of self-designed FPGA circuitry of user is loaded on fpga chip before.Generally step is that user is self-designed FPGA circuitry is finished writing, comprehensive directly to see whether function is correct with software emulation on computers into netlist, incorrect to be accomplished by repairing Change the self-designed FPGA circuitry of user, the debugging of this kind of mode is referred to as artificial debugging.After emulation passes through, then by user certainly The FPGA circuitry of oneself design is loaded on fpga chip to be verified and is debugged, and this kind of mode is referred to as upper plate debugging.

In prior art, the debugging side that the mode of upper plate debugging is provided by the debugging of software on computer after being mainly upper plate Method and Debugging interface, the debugging of the much like simulation stage of this kind of upper plate debud mode so that user is not felt by being actually The result that plate runs, experiences relatively low, and Debugging interface is not succinct directly perceived enough, it is desirable to have certain specialty requirement could use suitable Profit, the more difficult left-hand seat of user.

And the FPGA brassboards of the independent debugging checking of realization provided by this utility model, without using computer, but Directly the self-designed FPGA circuitry of user is run on FPGA brassboards, so that user can experience user The result of the actual upper plate operation of self-designed FPGA circuitry, user experience is higher, and the realization that this utility model is provided is only The number of the N systems that can be understood for any user that the final debugging result of the vertical FPGA brassboards for debugging checking shows According to so that user is easier to left-hand seat.

In sum, this utility model has advantages below：

(1). computer end need not be connected during debugging checking, it is not necessary to the support of special-purpose software；

(2). CPU core is included in the circuit that need not be designed, it is all very applicable for large, medium and small design circuit；

(3). " output unit " includes display screen, can be particularly shown out the numerical value of the data of collection, there is provided very friendly Observing interface, and there is no the restriction of the size of gathered data；

(4). " input block " can support the input of touch screen, now then can easily be input into any digit any The data of numerical value are used to control debugging.

(5). " input block " is after good tissue, it is possible to achieve single step is performed, the function such as insertion breakpoint, realizes easy With, friendly Debugging interface.

(6). in this utility model, " debugging call unit " main part is all that designed in advance is good, and user only needs to letter The single connection unit and " FPGA circuits to be debugged ", then interactive controlling signal, and gathered data greatly reduces use The complexity of person's debugging.

It should be noted that the electrical connection described in this utility model, refers to that (part can be first device by two parts Part, unit, module, chip or component) between all modes for coupling together, wherein, all modes include being directly connected to, indirectly Connection, inductively connection, wirelessly connection and wired connection etc..

Finally it should be noted that：Various embodiments above is only illustrating the technical solution of the utility model, rather than which is limited System；Although being described in detail to this utility model with reference to foregoing embodiments, one of ordinary skill in the art should Understand：Which still can be modified to the technical scheme described in foregoing embodiments, or to which part or whole Technical characteristic carries out equivalent；And these modifications or replacement, do not make the essence of appropriate technical solution depart from this practicality new The scope of each embodiment technical scheme of type.

Claims (7)

1. it is a kind of to realize the independent FPGA brassboards for debugging checking, it is characterised in that to include：Install on the FPGA brassboards Have toggle switch, key switch, on-site programmable gate array FPGA chip, the peculiar input block for being input into control signal, For showing that the control signal and the fpga chip run the screen output list of the internal data that the control signal is produced Unit；

The toggle switch and the key switch are electrically connected with the fpga chip on the FPGA brassboards respectively；

The fpga chip is electric with the peculiar input block and the screen output unit respectively on the FPGA brassboards Connection；

The peculiar input block is matrix keyboard.

2. FPGA brassboards according to claim 1, it is characterised in that the fpga chip is built-in with for debugging checking FPGA circuits to be debugged.

3. FPGA brassboards according to claim 1, it is characterised in that also include：Controller；

The controller is electrically connected with the fpga chip, the peculiar input block and the screen output unit respectively.

4. FPGA brassboards according to claim 3, it is characterised in that the controller is central processor CPU.

5. according to the arbitrary described FPGA brassboards of claim 1-4, it is characterised in that the screen output unit is display screen Curtain.

6. FPGA brassboards according to any one of claim 1-4, it is characterised in that the peculiar input block and described Screen output unit is the touch display screen for having input and output function concurrently.

7. FPGA brassboards according to any one of claim 1-4, it is characterised in that the screen output unit is luminous Diode (LED) or charactron.