CN206038876U - A power source detection circuit for passive RFID tag - Google Patents
A power source detection circuit for passive RFID tag Download PDFInfo
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- CN206038876U CN206038876U CN201620751062.0U CN201620751062U CN206038876U CN 206038876 U CN206038876 U CN 206038876U CN 201620751062 U CN201620751062 U CN 201620751062U CN 206038876 U CN206038876 U CN 206038876U
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- pmos
- power
- circuit
- phase inverter
- nmos tube
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Abstract
The utility model provides a pair of a power source detection circuit for passive RFID tag, including partial pressure sampling circuit I1, schmidt trigger circuit I2 and reset pulse production circuit I3, the power VCC of input supplies power to whole power source detection circuit, the utility model discloses a power source detection circuit can directly detect input power supply voltage, need not the 2nd mains operated, is applicable to passive RFID tag's power detecting for solve the problem that mains voltage detected among the passive RFID tag, the utility model discloses a power source detection circuit simple structure adopts CMOS technology to realize, and is easy to be integrated to the low -power consumption can be realized, the low energy consumption requirement of passive RFID tag chip is satisfied.
Description
Technical field
The utility model is related to a kind of power sense circuit, and in particular to a kind of power detecting for passive RF label
Circuit.
Background technology
RF identification (Radio Frequency Identification) be it is a kind of be applied in short range it is non-
The wireless communication technology of contact automatic identification, is widely used in logistics, gate inhibition, Automated condtrol, identification, quick payment
Deng numerous areas.RF tag is one of important component part of radio-frequency recognition system.
Radio frequency tag chip include it is active and passive two kinds, passive RF label have internal power supply, its work
It is the radiofrequency signal that will be received as power supply, rectified mu balanced circuit is obtained after processing, and the supply voltage is needed in experience one
Can be only achieved after the process of liter and stablize, therefore passive RF label chip needs the power supply of power sense circuit detection voltage-stablizer output
Operating voltage needed for whether reaching, and before supply voltage reaches and stablizes, reseting pulse signal is produced to following digital
Circuit is resetted.As the digital circuits section in label chip is firstly the need of could start normal work after being resetted,
And in order to tackle the situation for causing coil voltage to decline suddenly by some cause specifics, need to produce a power-off reset letter
Number to allow numerical portion to make corresponding data protection action.Therefore power sense circuit needs to complete to reply by cable on label simultaneously
Position and the function of power-off reset.
The content of the invention
The utility model provides a kind of power sense circuit for passive RF label, can be directly to input supply voltage
Detected, powered without the need for second source, it is adaptable to the power detecting of passive RF label, to solve in passive RF label
The problem of supply voltage detection.Power sense circuit simple structure of the present utility model, is realized using CMOS technology, easy of integration；
And power sense circuit of the present utility model is capable of achieving low-power consumption, meets the low energy consumption requirement of passive RF label chip.
A kind of power sense circuit for passive RF label that the utility model is provided, including pressure sampling circuit
I1, Schmidt trigger circuit I2 and reset pulse produce circuit I 3, and the power supply VCC of input powers to whole power sense circuit,
It is characterized in that：The pressure sampling circuit I1 is powered by VCC, exports two voltage division signals Vp and Vn；Vp and Vn voltages are distinguished
The PMOS and NMOS tube size of current in the Schmidt trigger circuit I2, and then the upset of controlled output signal is controlled, then
Through phase inverter out-put supply detection signal EN；The Schmidt trigger circuit I2 is used for controlling power supply electrifying and detection of power loss
Threshold level；The reset pulse produces circuit I 3 and produces reset pulse by way of delay circuit and XOR gate compare, and makes
Obtain whole passive RF label system to be reset in power or power-down.
The pressure sampling circuit that described pressure sampling circuit I1 is combined with resistance for metal-oxide-semiconductor, the source of the first PMOS MP1
Pole connects input power VCC, the grid of the first PMOS MP1, the drain electrode of the first PMOS MP1 and the source of the second PMOS MP2
Pole connects；The grid of the second PMOS MP2, the drain electrode of the second PMOS MP2 are connected with one end of first resistor R1；First resistor
The other end ground connection GND of R1.
The Schmidt trigger circuit I2 includes three PMOSs, three NMOS tubes and two phase inverters, the 3rd PMOS
The source electrode of MP3 and the 4th PMOS MP4 connects the grid of input power VCC, the 3rd PMOS MP3 and the 4th PMOS MP4 and connects
The grid of one PMOS MP1 forms mirror image circuit, and the drain electrode of the 3rd PMOS MP3 connects the drain electrode of the first NMOS tube MN1, and the 4th
The drain electrode of PMOS MP4 connects the source electrode of the 5th PMOS MP5；The grid of the 5th PMOS MP5, the grid of the second NMOS tube MN2
Output with the first phase inverter INV1 connects, the drain electrode of the 5th PMOS MP5, the drain electrode of the second NMOS tube MN2, the 3rd PMOS
The drain electrode of MP3, the drain electrode of the first NMOS tube MN1 are connected with the input of the first phase inverter INV1；The source electrode of the second NMOS tube MN2 connects
The drain electrode of the 3rd NMOS tube MN3；The one of the grid of the first NMOS tube MN1, the grid of the 3rd NMOS tube MN3 and first resistor R1
End, the drain electrode of the second PMOS MP2 connect；The source ground GND of the source electrode of the first NMOS tube MN1 and the 3rd NMOS tube MN3；The
The output of the input first phase inverter INV1 of termination of two phase inverter INV2, the output of the second phase inverter INV2 connect the 3rd phase inverter
The input of INV3；3rd phase inverter INV3 out-put supply detection signal EN, power detection signal EN are other circuits of system
The enable signal of module.
The reset pulse produces circuit I 3 includes a delay unit, a biconditional gate and a phase inverter.First
The input of delay unit Delay1 connects the output EN signals of the 3rd phase inverter INV3, and the output of the first delay unit Delay1 connects
One input vi2 of one biconditional gate Xnor1；Another input vi1 of the first biconditional gate Xnor1 connects the 3rd phase inverter INV3's
Output EN signals, the output of the first biconditional gate Xnor1 connect the input of the 4th phase inverter INV4, and the 4th phase inverter INV4's is defeated
Go out as reset signal output port POR.
The pressure sampling circuit that power sense circuit of the present utility model is combined with resistance using metal-oxide-semiconductor, relative to tradition
Electric resistance partial pressure sample circuit, the utility model can reduce circuit in the case of the space wastage not brought by multiple big resistance
Quiescent dissipation；The utility model controls the threshold value electricity of power supply electrifying detection and detection of power loss using Schmidt trigger principle
It is flat, realize the upper and lower electro-detection time lag of supply voltage, the electricity that the power detection signal for so exporting can be brought against power-supply fluctuation
It is flat unstable.Adopt Logical Design more the utility model, the power consumption penalty that power sense circuit work brings can be reduced.
Description of the drawings
Fig. 1 is power sense circuit structured flowchart of the present utility model；
Fig. 2 is the physical circuit figure that the utility model is implemented；
Fig. 3 is the groundwork sequential chart that the utility model is implemented；
Fig. 4 is the upper and lower electric time lag curve synoptic diagram of the utility model power sense circuit.
Specific embodiment
Fig. 1 is the structured flowchart of the power sense circuit scheme of embodiment of the present utility model.As shown in figure 1, this practicality
New power detecting module includes that pressure sampling circuit I1, Schmidt trigger circuit I2 and reset pulse produce circuit I 3.
Fig. 2 is the physical circuit figure of the power sense circuit scheme of the utility model embodiment.As shown in Fig. 2 described
Pressure sampling circuit I1 is the pressure sampling circuit that metal-oxide-semiconductor is combined with resistance, including two PMOSs and a resistance.First
The source electrode connection input power VCC of PMOS MP1, the grid of the first PMOS MP1, the drain electrode of the first PMOS MP1 and second
The source electrode connection of PMOS MP2；One end of the grid of the second PMOS MP2, the drain electrode of the second PMOS MP2 and first resistor R1
Connect；The other end ground GND of first resistor R1.
The Schmidt trigger circuit I2 includes three PMOSs, three NMOS tubes and two phase inverters.3rd PMOS
The source electrode of MP3 and the 4th PMOS MP4 connects the grid of input power VCC, the 3rd PMOS MP3 and the 4th PMOS MP4 and connects
The grid of one PMOS MP1 forms mirror image circuit, and the drain electrode of the 3rd PMOS MP3 connects the drain electrode of the first NMOS tube MN1, and the 4th
The drain electrode of PMOS MP4 connects the source electrode of the 5th PMOS MP5；The grid of the 5th PMOS MP5, the grid of the second NMOS tube MN2
Output with the first phase inverter INV1 connects, the drain electrode of the 5th PMOS MP5, the drain electrode of the second NMOS tube, the 3rd PMOS MP3
Drain electrode, the drain electrode of the first NMOS tube MN1 connected with the input of the first phase inverter INV1；The source electrode of the second NMOS tube MN2 connects
The drain electrode of three NMOS tubes MN3；The grid of the first NMOS tube MN1, one end of the grid of the 3rd NMOS tube MN3 and first resistor R1,
The drain electrode of the second PMOS MP2 connects；The source ground GND of the source electrode of the first NMOS tube MN1 and the 3rd NMOS tube MN3；Second
The output of the input first phase inverter INV1 of termination of phase inverter INV2, the output of the second phase inverter INV2 meet the 3rd phase inverter INV3
Input；3rd phase inverter INV3 out-put supply detection signal EN (the enable letters of passive RF label system other circuit modules
Number).
The reset pulse produces circuit I 3 includes a delay unit, a biconditional gate and a phase inverter.First
The input of delay unit Delay1 connects the output EN signals of the 3rd phase inverter INV3, and the output of the first delay unit Delay1 connects
One input vi2 of one biconditional gate Xnor1；Another input vi1 of the first biconditional gate Xnor1 connects the 3rd phase inverter INV3's
Output EN signals, the output of the first biconditional gate Xnor1 connect the input of the 4th phase inverter INV4, the output of the 4th phase inverter INV4
As reset signal output port POR.
The concrete operating principle of the utility model embodiment：
As shown in the specific embodiment circuit diagram of Fig. 2, when input supply voltage VCC is raised, the in pressure sampling circuit
The leakage current of one PMOS MP1 and the second PMOS MP2 can be raised, and the electric current for flowing through first resistor R1 is equally raised, such vn
Voltage will be raised, and as the first PMOS MP1 is using the connected mode of diode, after conducting, metal-oxide-semiconductor resistance is smaller, but
First resistor value is typically designed must be than larger, much larger than the conducting resistance of the first PMOS MP1, so being managed by IC design
By understanding, when VCC is raised, when flowing through the electric current increase of pressure sampling circuit, the VCC-Vp changes of overdriving of the first PMOS MP1
It is smaller, and the change of Vn is substantially very big.In the case that supply voltage VCC is very low, the magnitude of voltage of Vp and Vn is all smaller；This
When, the electric current that the third and fourth PMOS MP3, MP4 in Schmidt trigger circuit flows through is significantly greater, and flows through a NMOS
The electric current of pipe MN1 then very little, and the grid of the second NMOS tube MN2 is controlled by the first phase inverter INV1 outputs, supply voltage VCC
In the case of relatively low, the second NMOS tube MN2 cannot pass through electric current substantially, so in the case that supply voltage VCC is relatively low, the
The input (can regard as high level) substantially consistent with the voltage swing of power supply VCC of one phase inverter INV1, so through phase inverter
Power detection signal EN exported after INV1, INV2, INV3 is low level.
After input supply voltage VCC is increased to given threshold, the leakage current of the first NMOS tube MN1 of Vn controls is more than Vp
Control the 3rd the 4th PMOS MP3, MP4 leakage current sum, at this moment the input current potential of the first phase inverter INV1 be pulled down to
Close to zero (low level), power detection signal EN exported after phase inverter INV1, INV2, INV3 is high level.
When declining (power down) for input supply voltage VCC, the work of the utility model embodiment power sense circuit is former
Reason is similar.The effect of Schmidt trigger circuit is the threshold level for controlling the detection of supply voltage VCC raising and lowerings, realizes power supply
The upper and lower electric time lag of voltage, the power detection signal of output error when preventing VCC from shaking.The present embodiment circuit controls detection threshold value
The method of level is the breadth length ratio for adjusting the 4th PMOS MP4 or the 3rd NMOS tube MN3, when the breadth length ratio of the 4th PMOS MP4
During increase, the threshold level of power supply electrifying detection is raised；And when the breadth length ratio of the 3rd NMOS tube MN3 is raised, power supply power-fail detection
Threshold level can reduce.It is to the time delay of power detection signal EN, then by XOR that reset pulse produces circuit operation principle
Not gate Xnor1 compares one reset pulse of generation so that whole passive RF label system can be answered in power or power-down
Position, resetting time can be obtained by adjusting the time delay of the first delay unit Delay1.Specifically refer to of the present utility model
The groundwork sequential chart of power sense circuit, as shown in Figure 3.
The utility model is not limited to specific embodiment described here, can be based on this reality to those skilled in the art
Various obvious changes are carried out with new design, are readjusted and are substituted all without departing from protection domain of the present utility model.Cause
This, above example is simply described in further detail to the utility model, but the utility model be not limited only to
Upper embodiment, in the case where conceiving without departing from the utility model, can also include more other Equivalent embodiments.
Claims (4)
1. a kind of power sense circuit for passive RF label, including pressure sampling circuit (I1), Schmidt trigger circuit
(I2) and reset pulse produces circuit (I3), the power supply VCC of input powers to whole power sense circuit, it is characterised in that：Institute
State pressure sampling circuit (I1) to be powered by VCC, export two voltage division signals Vp and Vn；Vp and Vn voltages apply close described in controlling respectively
PMOS and NMOS tube size of current in special triggers circuit (I2), and then the upset of controlled output signal, then through phase inverter
Out-put supply detection signal EN；Schmidt trigger circuit (I2) is used for controlling the threshold value electricity of power supply electrifying and detection of power loss
It is flat；The reset pulse produces circuit (I3) and produces reset pulse by way of delay circuit and XOR gate compare so that whole
Individual passive RF label system can be reset in power or power-down.
2. power sense circuit according to claim 1, is characterized in that：Described pressure sampling circuit (I1) is metal-oxide-semiconductor
The pressure sampling circuit combined with resistance, the source electrode connection input power VCC of the first PMOS (MP1), the first PMOS (MP1)
Grid, the drain electrode of the first PMOS (MP1) is connected with the source electrode of the second PMOS (MP2)；The grid of the second PMOS (MP2)
Pole, the drain electrode of the second PMOS (MP2) are connected with one end of first resistor (R1)；The other end ground connection GND of first resistor (R1).
3. power sense circuit according to claim 2, is characterized in that：Schmidt trigger circuit (I2) includes three
The source electrode of PMOS, three NMOS tubes and two phase inverters, the 3rd PMOS (MP3) and the 4th PMOS (MP4) connects input electricity
The grid of source VCC, the 3rd PMOS (MP3) and the 4th PMOS (MP4) connects the grid of the first PMOS (MP1) and forms mirror image electricity
Road, the drain electrode of the 3rd PMOS (MP3) connect the drain electrode of the first NMOS tube (MN1), and the drain electrode of the 4th PMOS (MP4) connects the 5th
The source electrode of PMOS (MP5)；The grid of the 5th PMOS (MP5), the grid of the second NMOS tube (MN2) and the first phase inverter
(INV1) output connects, the drain electrode of the 5th PMOS (MP5), the drain electrode of the second NMOS tube (MN2), the 3rd PMOS (MP3)
Drain electrode, the drain electrode of the first NMOS tube (MN1) connected with the input of the first phase inverter (INV1)；The source of the second NMOS tube (MN2)
Pole connects the drain electrode of the 3rd NMOS tube (MN3)；The grid of the first NMOS tube (MN1), the 3rd NMOS tube (MN3) grid it is electric with first
One end of resistance (R1), the drain electrode of the second PMOS (MP2) connect；The source electrode of the first NMOS tube (MN1) and the 3rd NMOS tube (MN3)
Source ground GND；The input of the second phase inverter (INV2) terminates the output of the first phase inverter (INV1), the second phase inverter
(INV2) output connects the input of the 3rd phase inverter (INV3)；3rd phase inverter (INV3) exports power detection signal EN,
Power detection signal EN is the enable signal of other circuit modules of system.
4. power sense circuit according to claim 3, is characterized in that：The reset pulse produces circuit (I3) includes one
Individual delay unit, a biconditional gate and a phase inverter；The input of the first delay unit (Delay1) connects the 3rd phase inverter
(INV3) the power detection signal EN signal for exporting, the output of the first delay unit (Delay1) connect the first biconditional gate
(Xnor1) an input vi2；Another input vi1 of the first biconditional gate (Xnor1) connects what the 3rd phase inverter (INV3) was exported
The power detecting EN signals, the output of the first biconditional gate (Xnor1) connect the input of the 4th phase inverter (INV4), and the 4th is anti-phase
The output of device (INV4) is used as reset signal output port POR.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620751062.0U CN206038876U (en) | 2016-07-15 | 2016-07-15 | A power source detection circuit for passive RFID tag |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620751062.0U CN206038876U (en) | 2016-07-15 | 2016-07-15 | A power source detection circuit for passive RFID tag |
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| Publication Number | Publication Date |
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| CN206038876U true CN206038876U (en) | 2017-03-22 |
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| CN201620751062.0U Expired - Fee Related CN206038876U (en) | 2016-07-15 | 2016-07-15 | A power source detection circuit for passive RFID tag |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106054087A (en) * | 2016-07-15 | 2016-10-26 | 上海璜域光电科技有限公司 | Power supply detection circuit used for passive radio frequency tag |
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2016
- 2016-07-15 CN CN201620751062.0U patent/CN206038876U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106054087A (en) * | 2016-07-15 | 2016-10-26 | 上海璜域光电科技有限公司 | Power supply detection circuit used for passive radio frequency tag |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170322 Termination date: 20170715 |