CN205982599U

CN205982599U - Nuclear magnetic resonance apparatus gradient pre -emphasis adjusting device

Info

Publication number: CN205982599U
Application number: CN201621041387.6U
Authority: CN
Inventors: 谢晨; 郑振耀; 陈忠
Original assignee: Xiamen University
Current assignee: Xiamen University
Priority date: 2016-09-07
Filing date: 2016-09-07
Publication date: 2017-02-22
Anticipated expiration: 2026-09-07

Abstract

The utility model provides a nuclear magnetic resonance apparatus gradient pre -emphasis adjusting device, relates to nuclear magnetic resonance apparatus. Be equipped with FPGA control module, digital analog conversion circuit, preemphasis circuit, FPGA from adaptation module, differential circuit and gradient amplifier, FPGA control module is through the inside CPU connection control FPGA who generates from adaptation module and through SPI serial bus interface configuration digital analog conversion circuit and preemphasis circuit, the digital analog conversion circuit comprises the AD5764R chip to the input of connecting the three routes preemphasis circuit by VOUTA, VOUTB, VOUTC three -ouput end respectively, FPGA is connected from adaptation module's input to the output of preemphasis circuit, and FPGA carries out the signal feedback from adaptation module to the preemphasis circuit, FPGA connects the input of differential circuit from adaptation module's output, and the input of gradient amplifier is connected to the output of differential circuit. But the accuracy of signal is ensured in the output of avoiding error signal.

Description

A kind of nuclear magnetic resonance analyser gradient pre-emphasis adjusting means

Technical field

This utility model is related to nuclear magnetic resonance analyser, especially relates to a kind of nuclear magnetic resonance analyser gradient pre-emphasis adjusting means.

Background technology

In nuclear magnetic resonance spectrometer and nuclear magnetic resonance imaging instrument, because magnet (vertical magnetic field) must have two pieces of pole plates, when Gradient coil during quick on-off, according to Faraday law of electromagnetic induction, can induce transient state electricity in gradient fields in these metals Stream is come the complementary field in the primary current magnetic field that to create antagonism.These spuious transient currents are known as being vortexed (eddy current). Vortex is substantially the electric current decayed in time, and there is retroaction in magnetic field produced by it to original magnetic field, and magnetic resonance can be made to believe Number produce phase dispersion, lead to selective exitation error it is impossible to make phase of echo meet again completely, in wave spectrum and imaging, show as letter Number disappearance or distortion.The presence of vortex will have a strong impact on gradient fields change so as to waveform Severe distortion.Current MRI system Developing direction is to improve image taking speed, is obtained with the time the shortest and has excellent resolution rate, signal to noise ratio and required Characteristic Contrast degree Image.The impact of vortex makes system be difficult to shorten the echo time, and eddy current decay needs the long period simultaneously.Even if using very The method of time-consuming increase stacking fold is it is also difficult to obtain preferable resolution and signal to noise ratio it is more difficult to the feature pair that obtained Degree of ratio.Therefore, MRI system wants the image having obtained it is necessary to resolve problem (the Richard L to image contributions for the vortex Stoll.The analysis of eddy currents.Clarendon Press OXFORD, 1974).

Content of the invention

The purpose of this utility model is for magnetic resonance device miniaturization, digitized growth requirement, provides a kind of nuclear-magnetism altogether Vibration Meter gradient pre-emphasis adjusting means.

This utility model is provided with FPGA (Field-Programmable Gate Array is field programmable gate array) control Molding block, D/A converting circuit, preemphasis circuit, FPGA adaptation module, difference channel and gradient amplifier；

The CPU that described FPGA control module passes through to be internally generated connects control FPGA adaptation module and passes through SPI serial EBI configuration D/A converting circuit and preemphasis circuit；

Described D/A converting circuit is made up of AD5764R chip, and by VOUTA, VOUTB, VOUTC No. tri- outfan respectively Connect the input of three road preemphasis circuits；The outfan of described preemphasis circuit connects the input of FPGA adaptation module, FPGA adaptation module carries out signal feedback to preemphasis circuit；

The outfan of described FPGA adaptation module connects the input of difference channel, and the outfan of difference channel connects ladder The input of degree amplifier.

This utility model mainly adopts digital analog mixed technology, and described FPGA adaptation module can be to institute after preemphasis Signal carry out Resurvey and compare with desired output signal, that is, by preemphasis circuit have the open loop change of script in order to Closed loop system, if the error of gained output signal is more than 8%, then FPGA can control and again carry out pre-add to input signal Process again, until the error of produced actual preemphasized signal output signal and theory signal is less than 8%, so can avoid The output of rub-out signal, ensure that the accuracy of signal significantly.

Brief description

Fig. 1 is the circuit composition frame chart of this utility model embodiment.

Fig. 2 has 2 rank preemphasis circuit schematic diagrams for this utility model embodiment.

Fig. 3 is the differential output circuit schematic diagram of this utility model embodiment.

Fig. 4 is gradient waveform change contrast schematic diagram before and after this utility model embodiment preemphasis.In the diagram, abscissa For time t (s), vertical coordinate is voltage magnitude U (V)；(a) be preferable gradient waveform, (b) be due to eddy current effect produce abnormal The waveform becoming, (c) is the waveform after preemphasis process, and (d) is the final waveform ideally obtaining.

Specific embodiment

Referring to Fig. 1, this utility model embodiment is provided with FPGA, and (Field-Programmable Gate Array is scene Programmable gate array) control module 1, D/A converting circuit 2, preemphasis circuit 3, FPGA adaptation module 4, difference channel 5 and Gradient amplifier 6；

The CPU that described FPGA control module 1 is passed through to be internally generated is connected control FPGA adaptation module 4 and is gone here and there by SPI Row bus interface configuration D/A converting circuit 2 and preemphasis circuit 3；

Described D/A converting circuit 2 is made up of AD5764R chip, and by VOUTA, VOUTB, VOUTC No. tri- outfan X, Y, Z connect the input of three road preemphasis circuits 3 respectively；The outfan of described preemphasis circuit 3 connects FPGA adaptation module 4 Input, FPGA adaptation module 4 carries out signal feedback to preemphasis circuit 3；

The outfan of described FPGA adaptation module 4 connects the input of difference channel 5, and the outfan of difference channel 5 is even Connect the input of gradient amplifier 6.

In this utility model, FPGA control module controls analog-digital chip AD5764R and enters gradient pulse data Row parallel-serial conversion, because gradient pulse signal includes tri- passages of X, Y, Z, respectively selects layer, frequency coding and phase code, because This this analog-digital chip can fully meet conversion requirements.Then send gradient pulse data and drive analog-digital chip to enter Row digital-to-analogue conversion, then after preemphasis is processed, signal is delivered to difference channel, gradient is carried out by the signal that difference channel exports Power amplification.

Referring to Fig. 2, input as original gradient pulse signal V_in, export the gradient pulse signal V after preemphasis_out.R1、 R2, C1 and R3, R4, C2 separately constitute one group of preemphasis circuit.Taking C1 group as a example this circuit is analyzed understanding, by an electricity Hold the voltage signal that the RC circuit network forming with two variable resistances can obtain e index functional form, wherein variable resistance R1 and R2 is respectively used to adjust amplitude constant and the time constant of waveform.

Referring to Fig. 3, gradient pulse signal is delivered to gradient power amplifier after preemphasis process and is amplified processing, by In gradient amplifier for Differential Input it is therefore desirable to gradient pulse signal is converted into differential signal output.The present embodiment adopts The ADA4922-1 chip U4 of ADI company is realizing gradient signal by the single-ended conversion to difference output.In figure, IN pin is single End signal input pin, OUT+ and OUT- is difference output pin, and REF is input signal reference voltage pin, and DIS pin is core Piece disables pin, draws high to keep in service in design.

Signal input signal memory module RAM being exported by preemphasis circuit is stored, and the signal transmission of storage is given by mistake Difference computing module, input signal and ideal signal are carried out Error Calculation, if the data error after calculating is larger be input to by mistake Difference data memory module is stored, if the signal after error less directly output preemphasis.

Before and after this utility model embodiment preemphasis, gradient waveform change contrast schematic diagram is referring to Fig. 4.

Claims

1. a kind of nuclear magnetic resonance analyser gradient pre-emphasis adjusting means is it is characterised in that be provided with FPGA control module, digital-to-analogue conversion electricity Road, preemphasis circuit, FPGA adaptation module, difference channel and gradient amplifier；

The CPU that described FPGA control module passes through to be internally generated connects control FPGA adaptation module and passes through SPI universal serial bus Interface configuration D/A converting circuit and preemphasis circuit；

Described D/A converting circuit is made up of AD5764R chip, and is connected respectively by VOUTA, VOUTB, VOUTC No. tri- outfan The input of three road preemphasis circuits；The outfan of described preemphasis circuit connects the input of FPGA adaptation module, FPGA Adaptation module carries out signal feedback to preemphasis circuit；

The outfan of described FPGA adaptation module connects the input of difference channel, and the outfan of difference channel connects gradient and puts The input of big device.