CN205944065U - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN205944065U
CN205944065U CN201620734996.3U CN201620734996U CN205944065U CN 205944065 U CN205944065 U CN 205944065U CN 201620734996 U CN201620734996 U CN 201620734996U CN 205944065 U CN205944065 U CN 205944065U
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China
Prior art keywords
layer
semiconductor
oxide
semiconductor device
end process
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CN201620734996.3U
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Chinese (zh)
Inventor
姜成根
元秋亨
金因瑞
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Imark Technology Co
Amkor Technology Inc
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Imark Technology Co
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Priority claimed from KR1020160003231A external-priority patent/KR101753512B1/en
Application filed by Imark Technology Co filed Critical Imark Technology Co
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Publication of CN205944065U publication Critical patent/CN205944065U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Semiconductor device. The utility model discloses a semiconductor device, semiconductor device can be used for forming input output pad's region and increase easily through the increase input output pad's figure for distribution layer forms to extending up to sealing the thing again. In one embodiment, semiconductor device contains: distribution layer again, back end processing procedure (BEOL) layer, the BEOL layer is electrically connected to distribution layer again, semiconductor die, semiconductor die is electrically connected to the BEOL layer, oxide layer, oxide layer covers semiconductor die's a surface, seal the thing, seal the thing and seal oxide layer, semiconductor die, BEOL layer and distribution layer's a surface again, and conductive projection, the conductive projection is formed at another of distribution layer again on the surface and be electrically connected to distribution layer again.

Description

Semiconductor device
Cross-Reference to Related Applications
The application quote the 10-2016-0003231 korean patent application that on January 11st, 2016 submits, advocate described The priority of korean patent application simultaneously advocates the rights and interests of described korean patent application, the content here of described korean patent application with The mode introducing in full is incorporated herein.
Technical field
Some embodiments of the present utility model are related to a kind of semiconductor device.
Background technology
In general, semiconductor device comprises by process chip and forms integrated circuit (IC) on chip and manufacture Semiconductor die.
In the case that semiconductor die is used as RF device, when semiconductor device passes through radio-frequency transmission signals, may Because wafer substrates retain and cause the loss of power after processing chip, and it is likely to the leakage that electric current occurs.
Utility model content
This utility model provides a kind of semiconductor device and its manufacture method a kind of, described semiconductor device and its manufacturer Method can be by increasing for forming the region of I/o pad and easily increasing the number of I/o pad so that dividing again Layer of cloth is formed as extending up to encapsulation object.
This utility model also provides a kind of semiconductor device and its manufacture method a kind of, by using being formed to cover half The oxide skin(coating) of semiconductor die to remove the wafer substrates of reservation completely, and described semiconductor device and its manufacture method are prevented from Current leakage and power loss can be reduced.
By clear of the present utility model above-mentioned described in the following description in preferred embodiment or from following description and its Its purpose.
According to one side of the present utility model, provide a kind of manufacture method of semiconductor device, described manufacture method bag Contain：Prepare chip by sequentially forming oxide skin(coating), semiconductor layer and back-end process (BEOL) layer on the wafer substrates；Cutting Chip is to be divided into individual semiconductor chip by chip；Remove wafer substrates by upset semiconductor chip and from semiconductor chip Semiconductor chip is arranged on a surface of carrier；A surface and semiconductor chip using encapsulation object encapsulation vehicle And then remove carrier；Form the redistributing layer waiting the BEOL layer being electrically connected to outside exposure while removing carrier；And Form the conductive projection waiting to be electrically connected to redistributing layer to be electrically connected to.
According to other side of the present utility model, provide a kind of semiconductor device, described semiconductor device comprises：Divide again Layer of cloth；Back-end process (BEOL) layer, described BEOL layer is electrically connected to redistributing layer；Semiconductor die, described semiconductor die electricity It is connected to described BEOL layer；Oxide skin(coating), described oxide skin(coating) covers a surface of semiconductor die；Encapsulation object, described bag Envelope thing encapsulating oxide skin(coating), a surface of semiconductor die, BEOL layer and redistributing layer；And conductive projection, described lead Electric projection is formed on another surface of redistributing layer and is electrically connected to redistributing layer.
As described above, in semiconductor device and its manufacture method, can be by increasing for forming I/o pad Region and easily increase the number of I/o pad so that redistributing layer is formed as extending up to encapsulation object.
In addition, in semiconductor device and its manufacture method, by using being formed to cover the oxidation of semiconductor die Nitride layer to remove the wafer substrates of reservation completely, is prevented from current leakage and can reduce power loss.
Brief description
Fig. 1 is the flow chart of the manufacture method illustrating the semiconductor device according to embodiment of the present utility model；
Fig. 2A to 2J is the cross-sectional view of the various steps of the manufacture method illustrating the semiconductor device shown in Fig. 1；
Fig. 3 is the flow chart of the manufacture method illustrating the semiconductor device according to another embodiment of the present utility model；With And
Fig. 4 A to 4F is the cross-sectional view of the various steps of the manufacture method illustrating the semiconductor device shown in Fig. 3.
Specific embodiment
Various aspects of the present utility model can be implemented in many different forms and be not intended to be limited to institute herein The example embodiment illustrating.In fact, providing these example embodiment of the present utility model to be in order that this utility model will be Abundant and complete, and various aspects of the present utility model will be passed on to those skilled in the art.
In the drawings, for the sake of clarity it is exaggerated the thickness in layer and region.Herein, similar reference numerals refer to Similar component.As used herein, term "and/or" comprise any of one or more of associated Listed Items and All combinations.In addition, term used herein is not limiting as merely for the sake of the purpose of description specific embodiment This utility model.As used herein, unless the context clearly, otherwise singulative is also intended to comprise plural shape Formula.Will be further understood that, term " inclusion ", "comprising" specify when for this specification stated feature, number, step, Operation, the presence of element and/or assembly, but it is not excluded that one or more of the other feature, number, step, operation, element, The presence of assembly and/or its group or interpolation.
Although it should be understood that term first, second etc. can herein be used for describing various parts, element, region, layer And/or section, but these parts, element, region, layer and/or section should not be limited by these terms.These terms are only used In one part of differentiation, element, region, layer and/or section and another part, element, region, layer and/or section.Therefore, example As the first component, the first element, first area, ground floor and/or the first section that are discussed herein below may be referred to as second Part, the second element, second area, the second layer and/or the second section are without deviating from teaching of the present utility model.To join in detail now Examine present example of the present utility model, illustrate the example of described embodiment in the accompanying drawings.
With reference to Fig. 1, show flow chart, described flow process illustrates the semiconductor device according to embodiment of the present utility model (100) manufacture method.
As shown in fig. 1, the manufacture method of semiconductor device (100) comprises：Prepare chip (S1), grinding back surface (S2), Cut (S3), semiconductor chip (S4) is installed, removes wafer substrates (S5), encapsulating (S6), form redistributing layer (S7), formed and lead Electric projection (S8) and separation (S9).
With reference to Fig. 2A to 2J, show cross-sectional view, described cross-sectional view illustrates the semiconductor device shown in Fig. 1 (100) the various steps of manufacture method.
Hereinafter, the manufacture method of semiconductor device will be described with reference to Fig. 1 and Fig. 2A to 2J.
As shown in Figure 2 A, in preparing wafer process (S1), chip is prepared on wafer substrates 10, described chip comprises Oxide skin(coating) 110, semiconductor layer 120 and back-end process (BEOL) layer 130 sequentially forming on the wafer substrates.
Oxide skin(coating) 110 can be formed to predetermined thickness on the first surface 10a of wafer substrates 10.Wafer substrates 10 can To be silicon substrate, but each side of the present utility model are not limited to this.Oxide skin(coating) 110 can be silicon oxide layer, have by Good interface characteristic between wafer substrates 10 that silicon is made and semiconductor layer 120 subsequently to be described,.Using selected from following The a kind of of the group of composition forms oxide skin(coating) 130 in the whole top area of wafer substrates 10：Thermal oxide, chemical vapor deposition Long-pending (CVD), physical vapour deposition (PVD) (PVD) and its equivalent.Oxidation can be inserted between semiconductor layer 120 and wafer substrates 10 Nitride layer 110.Oxide skin(coating) 110 can be provided to prevent current leakage.
Semiconductor layer 120 is the quasiconductor wherein with multiple integrated circuits, and can be generally shaped to plate shape. Terminal 121 could be for the interface of the multiple integrated circuits in semiconductor layer 120.Terminal 121 may be electrically connected to BEOL layer 130 the first redistributing layer 132.Semiconductor layer 120 may be inserted between oxide skin(coating) 110 and BEOL layer 130.
BEOL layer 130 comprises the first dielectric layer 131 and the first redistributing layer 132.BEOL layer 130 is formed as being completely covered half The first surface 120a of conductor layer 120.
BEOL layer 130 comprises to be formed as being completely covered the first dielectric layer 131 of semiconductor layer 120, passes through Lithography Etching work The open area of skill and/or laser technology formation and the first redistributing layer being formed in the exposed region of open area 132.Herein, terminal 121 can be exposed by open area, and the first redistributing layer 132 can be formed at semiconductor layer 120 With on the first dielectric layer 131 to contact with terminal 121 or terminal to be electrically connected to 121.First redistributing layer 132 can various figures Case is formed to be electrically connected to the terminal 121 of semiconductor layer 120, and can include multiple first redistributing layers.
First dielectric layer 131 can be a kind of dielectric layer selected from the group consisting of：Silicon oxide layer, silicon nitride layer And its equivalent, but each side of the present utility model are not limited to this.First redistributing layer can be formed by following technique 132：For the electroless plating technique of the crystal seed layer being made up of gold, silver, nickel, titanium and/or tungsten, using the electroplating technology of copper etc., with And the Lithography Etching technique using photoresist, but each side of the present utility model are not limited to this.
In addition, the first redistributing layer 132 can not only be made of copper, but also by selected from the one of group consisting of Plant material to make：Copper alloy, aluminum, aluminium alloy, ferrum, ferroalloy and its equivalent, but each side of the present utility model are not limited to This.Furthermore, it is possible to the technique that forms first dielectric layer 131 and first redistributing layer 132 is repeatedly performed a plurality of times, thus complete tool There is the BEOL layer 130 of multiple structure.In an example, the first redistributing layer 132 can be included by the first dielectric layer 131 The joint sheet that open area exposes.In addition, BEOL layer 130 is by manufacturing the redistributing layer that (FAB) technique is formed.Especially, First redistributing layer 132 can be formed with fine linewidth or thickness.
As shown in Figure 2 B, overleaf (S2) in process of lapping, the second surface 10b of grinding wafers substrate 10 can be passed through Remove described second surface 10b, described second surface with form oxide skin(coating) 110, semiconductor layer 120 and BEOL layer above 130 first surface 10a is contrary.With cut crystal substrate 10 to produce individual semiconductor chip 100x, and then can grind Described wafer substrates make it retain predetermined thickness to contribute to processing.The predetermined thickness of the wafer substrates 10 retaining can be equivalent to During removing wafer substrates, (S5) passes through the thickness of the wafer substrates 10 that etching removes, and is described later.
As shown in FIG. 2 C, in cutting process (S3), cut oxide skin(coating) 110, semiconductor layer 120 and BEOL layer 130 stackings wafer substrates 10 thereon, wafer substrates 10 are divided into individual semiconductor chip 100x.That is, In cutting process (S3), cutting semiconductor layer 120 is to be then divided into comprising partly leading individually of individual semiconductor nude film 120 Body chip 100x (throughout the specification, is interchangeably used and indicates different terms, example by identical reference number As, semiconductor layer and semiconductor die.) further, since semiconductor chip 100x, wafer substrates 10, oxygen are separated by cutting The outer surface of compound layer 110, semiconductor die 120 and BEOL layer 130 can be placed on same plane.Can be cut by blade Cut or execute cutting using cutting device, but each side of the present utility model are not limited to this.Semiconductor die 120 can be penetrated Frequently (RF) device.
As illustrated in fig. 2d, during semiconductor chip is installed (S4), can be by multiple individual semiconductor chip 100x Being spaced turns up the soil is arranged on carrier 20.Carrier 20 has the first surface 20a and contrary with first surface 20a of plane Two surface 20b, and individual semiconductor chip 100x may be mounted on the first surface 20a of carrier 20, is spaced apart from each other pre- Set a distance.Herein, corresponding semiconductor chip 100x can be overturn so that BEOL layer 130 is directed to the first surface with carrier 20 20a contacts and then installs on the carrier.Carrier 20 can be made up of a kind of material selected from the group consisting of： Silicon, low-grade silicon, glass, carborundum, sapphire, quartz, pottery, metal-oxide, metal and its equivalent, but this utility model Each side be not limited to this.
As shown in fig. 2e, during removing wafer substrates (S5), remove chip lining from multiple semiconductor chip 100x Bottom 10, thus makes oxide skin(coating) 110 outwards expose.That is, remove wafer substrates 10 so that oxide skin(coating) 110 first Surface 110a outwards exposes.During removing wafer substrates (S5), can be moved completely by dry type and/or wet etch process Except the wafer substrates 10 retaining.Wafer substrates 10 can be removed in this way, thus prevent wafer substrates 10 emergent power from losing.
As shown in Fig. 2 F and 2G, in encapsulation process (S6), it is arranged on many on carrier 20 by encapsulation object 140 encapsulating The individual semiconductor chip 100x and first surface 20a of carrier 20, to be completely covered the plurality of semiconductor chip and described First surface.Encapsulation object 140 is formed as being completely covered the first surface 20a of carrier 20, oxide skin(coating) 110, semiconductor die 120 And BEOL layer 130.That is, encapsulation object 140 is formed on the first surface 20a of carrier 20, it is arranged on being completely covered Individual semiconductor chip 100x on the first surface 20a of carrier 20.Encapsulation object 140 have plane first surface 140a and Second surface 140b that is contrary with first surface 140a and contacting with the first surface 20a of carrier 20.Be spaced apart from each other is multiple Semiconductor chip 100x can be prevented by external environment influence by encapsulation object 140 electric protection.
Encapsulating (S6) can be executed by a kind of method selected from the group consisting of：General transfer moudling, pressure Contracting method of molding, injection molding and its equivalent, but each side of the present utility model are not limited to this.Encapsulation object 140 can be General epoxy resin, thin film, pastel and its equivalent, but each side of the present utility model are not limited to this.
In addition, after forming encapsulation object 140, removing carrier 20 and connect with the first surface 20a of carrier 20 so that being directed to The second surface 140b of the second surface 130b of tactile BEOL layer 130 and encapsulation object 140 outwards exposes.
As shown in fig. 2h, during forming redistributing layer (S7), redistributing layer 150 is formed as covering BEOL layer 130 Second surface 130b and encapsulation object 140 second surface 140b to be electrically connected to the BEOL layer 130 of outside exposure.Divide again Layer of cloth 150 comprises the second dielectric layer 151 and the second redistributing layer 152.
By forming second Jie of the second surface 140b of the second surface 130b covering BEOL layer 130 and encapsulation object 140 Electric layer 151, open area is formed by Lithography Etching technique and/or laser technology and is outwards being exposed by open area Region in form the second redistributing layer 152, form redistributing layer 150.Herein, the first redistributing layer 132 of BEOL layer 130 leads to Cross open area to expose.In addition, the second redistributing layer 152 can be formed on the second surface 130b of BEOL layer 130 to be drawn Contact and be electrically connected to described first redistributing layer to by the first redistributing layer 132 that open area outwards exposes.In addition, The second redistributing layer 152 being electrically connected to the first redistributing layer 132 extends to the second surface 140b of encapsulation object 140.The Two redistributing layers 152 can be formed with various patterns to be electrically connected to BEOL layer 130 and can include multiple second redistributing layers. In addition, redistributing layer 150 can be formed as extending to the second surface 140b of encapsulation object 140.Can be naked by changing quasiconductor The position of joint sheet 121 of piece 120 or change input/output (I/O) number that pads and to form redistributing layer 150.Further, since Redistributing layer 150 is formed as extending to the second surface 140b of encapsulation object 140, therefore can be used for forming I/O pad by increase Region and easily increase the number of I/O pad.
Second dielectric layer 151 can be a kind of dielectric layer selected from the group consisting of：Silicon oxide layer, silicon nitride layer And its equivalent, but each side of the present utility model are not limited to this.Second dielectric layer 151 can prevent in the second redistributing layer Electrical short between each of 152.Second redistributing layer 152 can be formed by following technique：For by gold, silver, nickel, The electroless plating technique of the crystal seed layer that titanium and/or tungsten are made, using the electroplating technology of copper etc., and the photoengraving using photoresist Carving technology, but each side of the present utility model are not limited to this.
In addition, the second redistributing layer 152 can not only be made of copper, but also by selected from the one of group consisting of Plant material to make：Copper alloy, aluminum, aluminium alloy, ferrum, ferroalloy and its equivalent, but each side of the present utility model are not limited to This.Second redistributing layer 152 can be exposed to the second surface 150b of redistributing layer 150.Furthermore, it is possible to repeatedly be performed a plurality of times Form the second dielectric layer 151 and the technique of the second redistributing layer 152, thus complete the redistributing layer 150 with multiple structure.
As shown in Fig. 2 I, during forming conductive projection (S8), multiple conductive projections 160 are formed as and are exposed to Multiple second redistributing layers 152 of the second surface 150b of distribution layer 150 contact or are electrically connected to the plurality of second redistribution Layer.Conductive projection 160 passes through redistributing layer 150 and BEOL layer 130 is electrically connected to semiconductor die 120.Conductive projection 160 is permissible Comprise conductive filler, copper gasket, conducting sphere, solder ball or copper ball, but each side of the present utility model are not limited to this.
When semiconductor device 100 is arranged on the external device (ED)s such as such as base plate, conductive projection 160 can serve as partly leading Arrangements of electric connection between body device 100 and external device (ED).
As shown in fig. 2j, in separation process (S9), cutting encapsulation object 140 and redistributing layer 150 are to be divided into There is the individual semiconductor device 100 of one or more semiconductor dies 120.
Semiconductor device 100 can be used for forming the region of I/O pad and easily increasing the number of I/O pad by increasing, Redistributing layer 150 is made to be formed as extending to the second surface 140b of encapsulation object 140.In addition, semiconductor device 100 can be from oxygen Compound layer 110 removes the wafer substrates of reservation completely, thus prevents current leakage and reduces power loss.
With reference to Fig. 3, show flow chart, described flow process illustrates the quasiconductor according to another embodiment of the present utility model The manufacture method of device.
The manufacture method of the semiconductor device (200) shown in Fig. 3 comprises：Prepare chip (S1), grinding back surface (S2), cut Cut (S3), semiconductor chip (S4) is installed, removes wafer substrates (S5), oxidation (S5a), encapsulating (S6), form redistributing layer (S7), form conductive projection (S8) and separate (S9).
Preparation chip (S1) shown in Fig. 3, grinding back surface (S2), cutting (S3), install semiconductor chip (S4) and Remove wafer substrates (S5) identical with the corresponding step of the manufacture method of the semiconductor device 100 shown in Fig. 1 and 2 A to 2E.Cause This, below description will focus on oxidation (S5a), encapsulating (S6), forms redistributing layer (S7), forms conductive projection (S8) and divide Step from (S9).
With reference to Fig. 4 A to 4F, cross-sectional view shows the manufacture method of the semiconductor device (200) shown in Fig. 3, comprises Oxidation (S5a), encapsulating (S6), formation redistributing layer (S7), each step forming conductive projection (S8) and separating (S9).? Hereinafter, the manufacture method of the semiconductor device (200) shown in Fig. 3 is described with reference to Fig. 4 A to 4F.
As shown in Figure 4 A, during oxidation (S5a), to the multiple semiconductor chips removing wafer substrates 10 from it 100x is aoxidized, and thus forms additional oxide layer 211 on the outer surface of oxide skin(coating) 110 and semiconductor die 120.Make For the result of oxidation, additional oxide layer 211 can be in the first surface 110a of the oxide skin(coating) 110 being made up of silicon oxide with outward Be formed as predetermined thickness on side surface 110c and on the outer surface 110c of semiconductor die 120.Therefore, by aoxidizing shape The additional oxide layer 211 becoming can be formed with the oxide skin(coating) 110 of semiconductor chip 110x.That is, oxidation Oxide skin(coating) 110 and the additional oxide layer 211 being formed by oxidation that nitride layer 210 comprises semiconductor chip 110x, and Be formed as the first surface 120a of semiconductor die 120 and outer surface 120c is completely covered.
As shown in figure 4 b and 4 c, in encapsulation process (S6), by encapsulation object 140 encapsulating be arranged on many on carrier 20 The individual semiconductor chip 200x and first surface 20a of carrier 20, to be completely covered the plurality of semiconductor chip and described First surface.Encapsulation object 140 is formed as being completely covered first surface 20a, oxide skin(coating) 210 and the BEOL layer 130 of carrier 20. That is, encapsulation object 140 is formed on the first surface 20a of carrier 20, so that first table that be arranged on carrier 20 is completely covered Individual semiconductor chip 200x on the 20a of face.Encapsulation object 140 have plane first surface 140a and with first surface 140a Second surface 140b that is contrary and contacting with the first surface 20a of carrier 20.The multiple semiconductor chip 200x being spaced apart from each other Can be prevented by external environment influence by encapsulation object 140 electric protection.
Encapsulating (S6) can be executed by a kind of method selected from the group consisting of：General transfer moudling, pressure Contracting method of molding, injection molding and its equivalent, but each side of the present utility model are not limited to this.Encapsulation object 140 can be General epoxy resin, thin film, pastel and its equivalent, but each side of the present utility model are not limited to this.
In addition, after forming encapsulation object 140, removing carrier 20 and connect with the first surface 20a of carrier 20 so that being directed to The second surface 140b of the second surface 130b of tactile BEOL layer 130 and encapsulation object 140 outwards exposes.
As shown in fig.4d, during forming redistributing layer (S7), redistributing layer 150 is formed as covering BEOL layer 130 Second surface 130b and encapsulation object 140 second surface 140b to be electrically connected to the BEOL layer 130 of outside exposure.Divide again Layer of cloth 150 comprises the second dielectric layer 151 and the second redistributing layer 152.Technique for forming redistributing layer 150 can be with Fig. 2 H Shown in formation redistributing layer (S7) identical.
As shown in figure 4e, during forming conductive projection (S8), multiple conductive projections 160 are formed as and are exposed to Multiple second redistributing layers 152 of the second surface 150b of distribution layer 150 contact or are electrically connected to the plurality of second redistribution Layer.Technique for forming conductive projection 160 can be identical with the formation conductive projection (S8) shown in Fig. 2 I.
As shown in Fig 4 F, in separation process (S9), cutting encapsulation object 140 and redistributing layer 150 are to be divided into There is the individual semiconductor device 200 of one or more semiconductor dies 120.
Semiconductor device 200 can be used for forming the region of I/O pad and easily increasing the number of I/O pad by increasing, Redistributing layer 150 is made to be formed as extending to the second surface 140b of encapsulation object 140.In addition, semiconductor device 200 can be from oxygen Compound layer 210 removes the wafer substrates of reservation completely and semiconductor die 120 is completely covered, thus prevent current leakage and Reduce power loss.
Although the embodiment by reference to some supports describes the quasiconductor dress according to various aspects of the present utility model Put and its manufacture method, but those skilled in the art will appreciate that, this utility model is not limited to disclosed being embodied as Example, but, all embodiments that this utility model will comprise to fall within the scope of the accompanying claims.

Claims (14)

1. a kind of semiconductor device is it is characterised in that include：
Redistributing layer；
Back-end process layer, described back-end process layer is electrically connected to described redistributing layer；
Semiconductor layer, described semiconductor layer includes integrated circuit and is electrically connected to described back-end process layer；
Cap oxide layer, described cap oxide layer covers the top surface of described semiconductor layer；
Encapsulation object, described encapsulation object is at least partially enveloping described cap oxide layer, described semiconductor layer, described back-end process Layer and the top surface of described redistributing layer；And
Conductive projection, described conductive projection is formed on the basal surface of described redistributing layer and is electrically connected to described redistribution Layer.
2. semiconductor device according to claim 1 it is characterised in that：
Described integrated circuit includes radio-frequency unit.
3. semiconductor device according to claim 1 it is characterised in that：
Described redistributing layer is electrically connected to described back-end process layer and covers the basal surface of described encapsulation object.
4. semiconductor device according to claim 1 is it is characterised in that further include：
It is formed at the lateral oxidation nitride layer on the side wall of described semiconductor layer.
5. semiconductor device according to claim 4 it is characterised in that：
Described lateral oxidation nitride layer covers described cap oxide layer further.
6. semiconductor device according to claim 1 it is characterised in that：
Described encapsulation object contacts the top oxide surface on described cap oxide layer.
7. semiconductor device according to claim 1 it is characterised in that：
Described cap oxide layer includes bottom oxide surface；And
Described semiconductor layer is formed on the oxide surface of described bottom.
8. semiconductor device according to claim 1 it is characterised in that：
Described cap oxide layer is the conductor oxidate of the oxide different from described semiconductor layer.
9. a kind of semiconductor device is it is characterised in that include：
Integrated circuit die, described integrated circuit die includes：
Back-end process layer, described back-end process layer includes the first back-end process surface and the second back-end process surface；
Semiconductor layer, described semiconductor layer is in the rear in section process layer and include the first semiconductor surface and the second quasiconductor Surface, and include integrated circuit；
Oxide skin(coating), described oxide skin(coating) and includes the first oxide surface and the second oxide table on described semiconductor layer Face；And
Joint sheet, described joint sheet passes through described back-end process layer and exposes, wherein
Described first back-end process surface attachment is to described first semiconductor surface；And
Described first oxide surface is attached to described second semiconductor surface；
And
Conductive projection, described conductive projection is electrically coupled to described joint sheet；
Wherein the region from the top surface of described semiconductor device to described second oxide surface does not contain semi-conducting material.
10. semiconductor device according to claim 9 is it is characterised in that further include：
Redistribution structure, described redistribution structure includes：
Redistribution dielectric layer；
Redistribution pattern layer；And
First redistribution structure side and the second redistribution structure side,
Wherein said conductive projection：
It is attached to described second redistribution structure side；And
It is electrically coupled to the described joint sheet of described integrated circuit die by described redistribution pattern layer.
11. semiconductor devices according to claim 10 it is characterised in that：
Described redistribution structure is formed on described second back-end process surface.
12. semiconductor devices according to claim 10 are it is characterised in that further include：
Encapsulation object, described encapsulation object is encapsulated described integrated circuit die and is included：
Laterally offset and the encapsulation object surface parallel to described second back-end process surface；
Wherein：
Described second back-end process surface is not encapsulated by described encapsulation object；
Described first redistribution structure side extends on described second back-end process surface and on described encapsulation object surface； And
Described conductive projection is located on described encapsulation object surface and from described second back-end process surface offsets.
13. semiconductor devices according to claim 9 are it is characterised in that further include：
Oxide, described oxide be different from described oxide skin(coating) and be attached to one of following or both：
The side wall of described semiconductor layer；And/or
Described second oxide surface of described oxide skin(coating).
14. semiconductor devices according to claim 9 it is characterised in that：Described semiconductor layer is formed at described first oxygen On compound surface.
CN201620734996.3U 2016-01-11 2016-07-13 Semiconductor device Active CN205944065U (en)

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KR10-2016-0003231 2016-01-11
US15/149,038 2016-05-06
US15/149,038 US20170200686A1 (en) 2016-01-11 2016-05-06 Semiconductor device and manufacturing method thereof

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