CN205942501U

CN205942501U - Bipolar transistor and electric current bias circuit

Info

Publication number: CN205942501U
Application number: CN201620649566.1U
Authority: CN
Inventors: 王钊
Original assignee: Wuxi Zhonggan Microelectronics Co Ltd
Current assignee: Wuxi Zhonggan Microelectronics Co Ltd
Priority date: 2016-06-27
Filing date: 2016-06-27
Publication date: 2017-02-08
Anticipated expiration: 2026-06-27

Abstract

The utility model provides a bipolar transistor and electric current bias circuit, bipolar transistor includes: the substrate with be located the positive trap region of substrate, the conductivity type of trap region with the conductivity type of substrate is opposite the trap region with the surface of the contact surface of substrate is equipped with a plurality of first active areas the trap region peripheral ring is around there being the second active area, first active area is the same with the conductivity type of second active area, electric current bias circuit adopts above -mentioned bipolar transistor to realize. The trap region can be shareed to a plurality of first active areas in this application, and the base of sharing can be regarded as to the trap region, and a plurality of first active area in the trap region can form two projecting poles, and the collecting electrode of sharing can be regarded as to the outer second active area of trap region to can reduce shared area of ambipolar diode and reduction chip cost through the sharing region.

Description

A kind of bipolar transistor and current biasing circuit

Technical field

The application is related to electronic chip technology field, more particularly, to a kind of bipolar transistor and current biasing circuit.

Background technology

At present, current biasing circuit has been widely used in various analog circuits.Fig. 1 shows in prior art and is based on The bias circuit construction schematic diagram of PNP, as illustrated, PMOS MP1, MP2, NMOS tube MN1, MN2, ambipolar crystalline substance can be included Body pipe PNP1, PNP2 and resistance R1, this circuit can provide current offset, for example：There is provided current offset for operational amplifier.Its In, so that A point voltage is equal to B point voltage, therefore, the electric current that current biasing circuit produces can be for MN1 and MN2 adjustmentWherein Δ V_beFor the difference of the base emitter voltage of two PNP, R is the resistance value of resistance R1；MP1 and MP2 composition electricity Stream mirror, to ensure that the emitter current of PNP1 and PNP2 is equal.In order to ensure there is suitable Δ V between PNP1 and PNP2_be, one As by 8: 1 realize, that is, PNP1 is formed with PNP2 identical PNP pipe by 8.

Fig. 2 shows the domain schematic diagram of traditional PNP1 and PNP2, as illustrated, in order to realize preferable matching, Typically adopt nine grids arrangement mode, middle PNP is PNP2, and remaining 8 are PNP1.To each PNP pipe, by three part groups Become：Colelctor electrode, base stage, emitter stage.Solid wire frame is N well region, is base stage.Oblique line filling region in N well region has for P+ Source region, is emitter stage.Oblique line filling region outside N well region is also P+ active area, is colelctor electrode.

Prior art deficiency is：

The chip area of existing bipolar transistor is larger, and chip cost is higher.

Content of the invention

The embodiment of the present application proposes a kind of bipolar transistor and current biasing circuit, to solve PNP in prior art The area of domain is larger, the higher technical problem of chip cost.

One side, the embodiment of the present application provides a kind of bipolar transistor, including：Substrate and be located at described substrate The well region in front, the conduction type of described well region is contrary with the conduction type of described substrate, in described well region and described substrate The surface of contact surface is provided with multiple first active areas, is surrounded with the second active area, described first active area in described well region periphery Identical with the conduction type of the second active area.

In enforcement, described well region is N-type well region, and described first active area and the second active area are P+ active area.

In enforcement, described well region is enclosed construction.

In enforcement, described enclosed construction is cube structure.

In enforcement, symmetrical centered on the plurality of first active area.

In enforcement, the size and shape of the plurality of first active area is identical.

In enforcement, described bipolar transistor forms the first transistor and transistor seconds, and described have positioned at multiple first First active area of the mid portion of source region is the emitter stage of transistor seconds, the described surrounding portion positioned at multiple first active areas The emitter stage that the first active area dividing is connected as the first transistor, described the first transistor and transistor seconds share as base The well region of pole, described the first transistor and transistor seconds share the second active area as colelctor electrode.

In enforcement, described first active area is 9, and described 9 the first active areas are distributed with Central Symmetry, described 9 the It is located at the emitter stage that the first middle active area is transistor seconds, remaining 8 the first active areas are connected conduct in one active area The emitter stage of the first transistor.

Second aspect, the embodiment of the present application provides a kind of current biasing circuit using above-mentioned bipolar transistor, The emitter stage of described the first transistor is connected with the source electrode of the first NMOS tube MN1 through first resistor R1, the current collection of the first transistor Pole is connected with the substrate of substrate, the substrate of described MN1 and the second NMOS tube MN2 with substrate, transistor seconds colelctor electrode, described The grid of MN1 is connected with the drain electrode of the grid, drain electrode and the second PMOS MP2 of MN2 respectively, the drain electrode of described MN1 respectively with The grid of the drain electrode of the first PMOS MP1, grid and MP2 is connected, the source electrode of described MP1 and substrate, the source electrode of described MP2 and Substrate is all connected with voltage VIN end, described well region ground connection.

In enforcement, described the first transistor and described transistor seconds are PNP transistor.

Have the beneficial effect that：

The bipolar transistor being provided by the embodiment of the present application and current biasing circuit, described bipolar transistor bag The well region including substrate and being located at described substrate face, the conduction type of described well region is contrary with the conduction type of described substrate, Described well region is provided with multiple first active areas with the surface of the contact surface of described substrate, and being surrounded with second in described well region periphery has Source region, described first active area is identical with the conduction type of the second active area, and multiple first active areas can share well region, well region Can be used as shared base stage, multiple first active areas in well region can form two emitter stages, and second outside well region is active Area can be as shared colelctor electrode, such that it is able to reduce bipolar diode occupied area and reduction by shared region Chip cost.

Brief description

The specific embodiment of the application is described below with reference to accompanying drawings, wherein：

Fig. 1 shows the bias circuit construction schematic diagram in prior art based on PNP；

Fig. 2 shows the domain schematic diagram of traditional PNP1 and PNP2；

Fig. 3 shows the structural representation of bipolar transistor in the embodiment of the present application；

Fig. 4 shows the generalized section of bipolar transistor in the application enforcement.

Specific embodiment

In order that the technical scheme of the application and advantage become more apparent, exemplary to the application below in conjunction with accompanying drawing Embodiment is described in more detail it is clear that described embodiment is only a part of embodiment of the application, rather than The exhaustion of all embodiments.And in the case of not conflicting, the embodiment in this explanation and the feature in embodiment can be mutual Combine.

For the deficiencies in the prior art, the embodiment of the present application proposes a kind of bipolar transistor and current biasing circuit, Reduce the area of bipolar transistor, thus reducing chip cost, additionally, also improve between bipolar transistor simultaneously Matching.

Embodiment one,

The embodiment of the present application provides a kind of bipolar transistor, can include：Substrate and be located at described substrate face Well region, the conduction type of described well region can be contrary with the conduction type of described substrate, in connecing of described well region and described substrate The surface of contacting surface can be provided with multiple first active areas, can be surrounded with the second active area in described well region periphery, and described first Active area can be identical with the conduction type of the second active area.

When being embodied as, described well region can be P type trap zone, and described first active area and the second active area can be N-type Active area or N+ active area.

In enforcement, described well region can be N-type well region (or referred to as NWell), described first active area and the second active area Can be p-type active area or P+ active area.

In enforcement, described well region can be enclosed construction.

Described enclosed construction can be circular, square or other are irregularly shaped.

In enforcement, described enclosed construction can be cube structure.

Described cube structure can be the structures such as square, cuboid.

In enforcement, the plurality of first active area can centered on symmetrical.

The plurality of first active area can be distributed with center for axial symmetry, for example：The forms such as 3*3 matrix, 5*5 matrix.

In enforcement, the size and shape of the plurality of first active area can be identical.

In enforcement, described bipolar transistor can form the first transistor and transistor seconds, described positioned at multiple First active area of the mid portion of one active area be transistor seconds emitter stage, described positioned at the four of multiple first active areas The emitter stage that first active area of circumferential portion is connected as the first transistor, described the first transistor and transistor seconds share to be made For the well region of base stage, described the first transistor and shared the second active area as colelctor electrode of transistor seconds.

First active area of the described mid portion positioned at multiple first active areas can be in these the first active areas First active area (such as can be 1) at center, as the emitter stage of transistor seconds, described positioned at multiple first active areas The first active area of peripheral portion can be then remaining first active area；The described pars intermedia positioned at multiple first active areas The first active area dividing can also be the first active area in addition to the first active area positioned at these the first active area outermost (can be for example multiple), as the emitter stage of transistor seconds, the of the described peripheral portion positioned at multiple first active areas One active area can be then the first active area of these the first active area outermost.

In enforcement, described first active area can be 9, and described 9 the first active areas can be distributed with Central Symmetry, institute State and in 9 the first active areas, be located at the emitter stage that the first middle active area can be transistor seconds, remaining 8 first active Area is connected can be used as the emitter stage of the first transistor.

Embodiment two,

Below taking PNP transistor as a example, to the application, the bipolar transistor being proposed and current biasing circuit are said Bright.

Fig. 3 shows the structural representation of bipolar transistor in the embodiment of the present application, as illustrated, described ambipolar crystalline substance Body pipe can include：Substrate and the N trap being located at described substrate face, at same N well region (as shown in wire frame solid in Fig. 3) Middle form 9 P+ active areas (as shown in the oblique lattice filling region in N well region in Fig. 3), the centre in this 9 P+ active areas that Individual P+ active area can be connected to the B node in Fig. 1 as the emitter stage of PNP2；Remaining 8 P+ active area forms sending out of PNP1 Emitter-base bandgap grading, is connected together and to the A node in Fig. 1.

In the embodiment of the present application, the first transistor (PNP1) and transistor seconds (PNP2) can share a N trap, that is, Common base, and it is connected to ground potential；In addition, in the embodiment of the present application, PNP1 and PNP2 can be with common collector, that is, P+ active area (as shown in the oblique lattice filling region outside N trap in Fig. 3) outside N trap, so, can reduce chip by shared region Area.

In addition, according to matching principle, if these devices are at a distance of nearer, when producing in enormous quantities, the thing of its local Reason characteristic (include various levels of doping content, depth etc.) is more nearly identical, and that is, matching is more preferable.PNP1 and PNP2 is more Join, the electric current that current biasing circuit produces is more accurate, that is, when producing in enormous quantities, the deviation of chip chamber is less.

Fig. 4 show the application implement in bipolar transistor generalized section, as shown in the figure it can be seen that multiple P+ Active area is located in N trap, the situation of shared N trap.P+ active area in N trap forms the emitter stage of PNP1 and PNP2.N trap is formed The base stage that PNP1 and PNP2 shares.P+ active area outside N trap forms the colelctor electrode that PNP1 and PNP2 shares.

Embodiment three,

Based on same inventive concept, in the embodiment of the present application, additionally provide a kind of electric current using above-mentioned bipolar transistor Biasing circuit, is illustrated below.

Described current biasing circuit can include：

The emitter stage of described the first transistor is connected with the source electrode of the first NMOS tube MN1 through first resistor R1, first crystal The colelctor electrode of pipe and the substrate of substrate, transistor seconds colelctor electrode and substrate, the substrate of described MN1 and the second NMOS tube MN2 It is connected, the grid of described MN1 is connected with the drain electrode of the grid, drain electrode and the second PMOS MP2 of MN2 respectively, the leakage of described MN1 Pole is connected with the grid of the drain electrode, grid and MP2 of the first PMOS MP1 respectively, the source electrode of described MP1 and substrate, described MP2 Source electrode be all connected with voltage VIN end with substrate, described well region ground connection.

In enforcement, the first transistor described in described the first transistor and described transistor seconds can be all positive-negative-positive crystal Pipe.

Because the current biasing circuit that the embodiment of the present application provides uses above-mentioned bipolar transistor, above-mentioned ambipolar Transistor reduces chip area by shared region, and, due to the first transistor in bipolar transistor and the second crystalline substance Body pipe at a distance of relatively near, matching preferably, therefore, electric current that current biasing circuit produces compared to existing technology more accurately so that During production in enormous quantities, the current deviation of chip chamber reduces.

Although having been described for the preferred embodiment of the application, those skilled in the art once know basic creation Property concept, then can make other change and modification to these embodiments.So, claims are intended to be construed to including excellent Select embodiment and fall into being had altered and changing of the application scope.

Claims

1. a kind of bipolar transistor is it is characterised in that include：Substrate and the well region being located at described substrate face, described well region Conduction type contrary with the conduction type of described substrate, be provided with multiple on the surface of described well region and the contact surface of described substrate First active area, is surrounded with the second active area, the conductive-type of described first active area and the second active area in described well region periphery Type is identical.

2., it is characterised in that described well region is N-type well region, described first is active for bipolar transistor as claimed in claim 1 Area and the second active area are P+ active area.

3. bipolar transistor as claimed in claim 1 is it is characterised in that described well region is enclosed construction.

4. bipolar transistor as claimed in claim 3 is it is characterised in that described enclosed construction is cube structure.

5. bipolar transistor as claimed in claim 1 is it is characterised in that symmetrically divide centered on the plurality of first active area Cloth.

6. bipolar transistor as claimed in claim 5 is it is characterised in that the size and shape of the plurality of first active area Identical.

7. bipolar transistor as claimed in claim 1 is it is characterised in that described bipolar transistor forms the first transistor And transistor seconds, the first active area of the described mid portion positioned at multiple first active areas is the transmitting of transistor seconds Pole, the connected emitter stage as the first transistor of the first active area of the described peripheral portion positioned at multiple first active areas, institute State the first transistor and transistor seconds shares well region, described the first transistor and the shared conduct of transistor seconds as base stage Second active area of colelctor electrode.

8. bipolar transistor as claimed in claim 7 is it is characterised in that described first active area is 9, described 9 the One active area is distributed with Central Symmetry, and being located at the first middle active area in described 9 the first active areas is transistor seconds Emitter stage, the emitter stage that remaining 8 the first active areas are connected as the first transistor.

9. a kind of current biasing circuit using bipolar transistor as claimed in claim 7 is it is characterised in that described first The emitter stage of transistor is connected with the source electrode of the first NMOS tube MN1 through first resistor R1, the colelctor electrode of the first transistor and substrate, Transistor seconds colelctor electrode is connected with the substrate of substrate, the substrate of described MN1 and the second NMOS tube MN2, the grid of described MN1 Pole is connected with the drain electrode of the grid, drain electrode and the second PMOS MP2 of MN2 respectively, the drain electrode of described MN1 respectively with a PMOS The grid of the drain electrode of pipe MP1, grid and MP2 is connected, the source electrode of described MP1 and substrate, the source electrode of described MP2 and substrate all with Voltage VIN end is connected, described well region ground connection.

10. current biasing circuit as claimed in claim 9 is it is characterised in that described the first transistor and described second crystal Pipe is PNP transistor.