CN205912049U - At multi -thread device of eliminating near -end cross in to copper line transmission - Google Patents
At multi -thread device of eliminating near -end cross in to copper line transmission Download PDFInfo
- Publication number
- CN205912049U CN205912049U CN201620945400.4U CN201620945400U CN205912049U CN 205912049 U CN205912049 U CN 205912049U CN 201620945400 U CN201620945400 U CN 201620945400U CN 205912049 U CN205912049 U CN 205912049U
- Authority
- CN
- China
- Prior art keywords
- thread
- end cross
- data
- local side
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The utility model discloses an at multi -thread device of eliminating near -end cross in to copper line transmission, including the local side and rather than the matched with user side, still include: the setting is in local side one side for the signal generator that have rising edge and falling edge synchronized clock signal is produced to each local side, the setting each local side and with signal generator connects to according to the field programmable gate array FPGA chip of received synchronized clock signal control local side data transmission state, it is connected to the user side, with the storage mechanism that the FPGA chip is connected. The utility model provides an at multi -thread device of eliminating near -end cross in to copper line transmission reaches the method of using the device, has guaranteed the copper line transmission system sent simultaneously and the received signal of different wire pairs, has avoided sending signal interference " near -end " receiving terminal, has improved the effective transmission bandwidth, promotes residential customer, commercial user's etc. Access capability.
Description
Technical field
This utility model is related to a kind of method of the elimination near-end cross using in the case of communications.More specifically
Say, this utility model be related to a kind of in the case of coexisting in same a bundle cable multi-thread to copper transmission in eliminate near-end crosstalk
The device and method disturbed.
Background technology
Copper transmission system has developed rapidly and has accessed into most widely used, most successful fixed broadband.Carry with accessing
The steeply rising of wide demand, the circuit frequency range of copper transmission system is also improving constantly, and the high band of part system has reached tens
Mhz, or even mhz up to a hundred, between line, near-end cross problem is further prominent, leads to signal to noise ratio to decline, reduces line speed or increasing
The big bit error rate even goes offline, and has a strong impact on stability and the customer experience of system, and cross-interference issue has become restriction copper transmission system
The principal element of system performance.
And near-end cross is the interference between the upward signal of not collinear pair and downstream signal, as shown in Figure 1, therefore existing
Have in dsl system to eliminate near-end cross frequently with wave filter, this technology be directed to interfering line pair sending signal with disturbed
The frequency division multiplexing mode of the different frequency range that the receipt signal of line pair uses is highly effective.But for uplink/downlink circuit frequency range phase
Same Transmission system, wave filter can not eliminate near-end cross well, therefore in copper transmission system, because of the receipts of not collinear pair
Sending out frequency is identical, if a line pair is asynchronous with the transceiving data of another line pair, arises that serious near-end cross, and why
The copper transmission system that lashing wire pair realized by sample realizes transceiving data synchronization, is this utility model key problems-solving.
Therefore, how to reduce the near-end cross of copper transmission system, improve effective transmission bandwidth, lifting residential customer, business
The access capability of industry user etc. becomes a very real technical barrier.
Utility model content
A purpose of the present utility model is to solve at least the above and/or defect, and provides and at least will be described later
Advantage.
This utility model it is also an object that provide a kind of multi-thread to copper transmission in eliminate near-end cross device,
It introduces signal generator in a device, and then the rising edge by external clock and trailing edge are as local side transceiving data
Reference, and then the sequential of transceiving data is controlled by fpga, then use user data after buffer-stored with memory combination
To be forwarded accordingly, and then guaranteeing that all system transceiving datas are synchronous, thus eliminating near-end cross impact, utilizing outer simultaneously
Put ddr data storage, in conjunction with synchronizing signal edge, the storage that fpga realizes user data forwards.External clock frequency can
Adjustment, meets the transmission delay demand of user.
This utility model is it is also an object that eliminate the method for near-end cross device so as to copper cash can be based on by application
Transmission system, provides a transceiving data synchronizing signal by unified to all local sides, so that each local side is according to synchronizing signal
Rising edge and trailing edge be managed collectively the transceiving data sequential of local side and user side, ensure that the copper transmission of not collinear pair
System sends and receives signal simultaneously, it is to avoid sending signal interference " near-end " receiving terminal, improves effective transmission bandwidth, lifting
The access capability of residential customer, commercial user etc..
In order to realize according to these purposes of the present utility model and further advantage, there is provided one kind is multi-thread to copper transmission
The middle device eliminating near-end cross, including for realizing multi-thread multiple local sides to copper transmission in same a bundle cable, and
The user side being matched therewith, also includes:
It is arranged on local side side, there is rising edge and the signal of trailing edge synchronizing clock signals is sent out in order to produce to each local side
Raw device；
It is arranged on each local side and is connected with described signal generator, to control local side according to the synchronizing clock signals receiving
The field programmable gate array fpga chip of data transmission state, it connects to user side；
It is connected with described fpga chip when local side is in transmission information state, row cache is entered with to be forwarded to its data
Storing mechanism.
Preferably, wherein, described fpga chip passes through a data filtering coupling unit and then be connected with user side, with
With build in a bundle cable realize multi-thread to copper transmission link.
Preferably, wherein, described data filtering coupling unit includes:
One is connected with described fpga chip, with the upstream data transmitting through it or downlink data are carried out digital-to-analogue conversion,
Analog front-end chip afe1230 of filtering；
It is arranged on the circuit coupling mechanism of described afe1230 signal output part；
It is arranged between described afe1230 signal output part and circuit coupling mechanism, with the signal to input to afe1230
The filter filter being filtered for the first time or filter circuit.
Preferably, wherein, described fpga is passed through data transmission interface mii and then is connected with ether net unit, to build
Network data transmission system.
Preferably, wherein, described fpga by parallel bus be connected with one to its principal and subordinate, speed, transmitting-receiving gain enter
The microprocessor cpu of row relevant parameter configuration.
Preferably, wherein, described storing mechanism is external ddr memorizer.
Preferably, wherein, also include with as cpu, fpga and afe1230 provide 5.0v, 3.3v, 1.8v, 1.1v work
Make the power module of voltage.
The purpose of this utility model can further by a kind of application described multi-thread to copper transmission in eliminate near
The method of end crosstalk device is realizing, comprising:
Described signal generator produces has rising edge and trailing edge synchronizing clock signals accordingly；
The fpga of each described local side, based on the synchronizing clock signals detecting, is judged current to determine each local side
Sequential is in rising edge or trailing edge；
If current sequential is in rising edge, each local side is both configured to send data mode, and corresponding each user
End is then configured to receiving data state；
Conversely, then each local side is both configured to receiving data state, and corresponding each user side is then configured to send out
Send data mode, realize the transmitting-receiving sequential of local side and user side is managed collectively, with the copper transmission system of not collinear pair
In system, each local side, the sending signal of each user side or receiving state signal are uniformly controlled, and then avoid the up letter of near-end
Crosstalk number and downstream signal between.
Preferably, wherein, described fpga passes through the data message of mii interface ether net unit transmission, and completes
To the protocol conversion of serial data, then by the storing mechanism being connected with fpga it is received to data message enter row buffering delay
Deposit, when the clock sync signal sequential that it detects is in rising edge, to send corresponding data message to user side, described
The output clock frequency of signal generator is configured to f=(n × 1) khz, wherein n ∈ (1,2 ..., 1000).
Preferably, wherein, if described fpga real-time detection to clock sync signal sequential be not rising edge,
It is not trailing edge, then before executing, corresponding serial data is to the conversion of mii or mii to the conversion of serial data.
This utility model at least includes following beneficial effect: first, this utility model provides one kind multi-thread to copper cash biography
The defeated middle device eliminating near-end cross, it introduces signal generator in a device, and then the rising edge by external clock and
Trailing edge is as the reference of local side transceiving data, and then controls the sequential of transceiving data by fpga, then with memory combination
Forwarded accordingly after buffer-stored using user data, and then guaranteed that all system transceiving datas are synchronous, thus disappearing
Except near-end cross impact, utilize external ddr data storage, in conjunction with synchronizing signal edge, fpga realizes user data simultaneously
Storage forwards, external clock frequency adjustable, meet the transmission delay demand of user, have can implementation result good, application
By force, adaptability is good, the stable effect of transmission performance.
Second, this utility model is it is also an object that eliminate the method for near-end cross device so as to can base by application
In the transmission mechanism of copper transmission system, provide a transceiving data synchronizing signal by unified to all local sides, so that each
Local side is managed collectively the transceiving data sequential of local side and user side according to the rising edge of synchronizing signal and trailing edge, ensure that not
The copper transmission system of collinear pair sends and receives signal simultaneously, it is to avoid sending signal interference " near-end " receiving terminal, improves
Effectively transmission bandwidth, the access capability of lifting residential customer, commercial user etc..
Part is embodied by further advantage of the present utility model, target and feature by description below, and part also will be passed through
Research of the present utility model and practice are understood by the person skilled in the art.
Brief description
Fig. 1 explanation is to produce near-end cross between the upward signal of not collinear pair and downstream signal in transmitting procedure
Schematic diagram；
Fig. 2 be in an embodiment of the present utility model multi-thread to copper transmission in eliminate near-end cross device company
Connect principle schematic；
Fig. 3 is that the device of application elimination near-end cross in an embodiment of the present utility model is realized in same a bundle cable
The transmitting-receiving synchronization principles figure of copper transmission system line；
Fig. 4 is the flow chart of data processing of fpga in the device eliminate in another embodiment of the present utility model near-end cross
Figure.
Specific embodiment
Below in conjunction with the accompanying drawings this utility model is described in further detail, to make those skilled in the art with reference to explanation
Book word can be implemented according to this.
It should be appreciated that used herein such as " have ", "comprising" and " inclusion " term do not allot one or many
The presence of individual other element or a combination thereof or interpolation.
Fig. 2-3 show according to of the present utility model a kind of multi-thread to copper transmission in eliminate the device of near-end cross
Way of realization, including for realizing multi-thread multiple local sides 1 to copper transmission in same a bundle cable, and is matched with it
The user side 2 closing, also includes:
It is arranged on local side side, there is rising edge and the signal of trailing edge synchronizing clock signals is sent out in order to produce to each local side
Raw device 3, it is used for providing a reference signal to the fpga of local side；
It is arranged on each local side and is connected with described signal generator, to control local side according to the synchronizing clock signals receiving
The field programmable gate array fpga chip 11 of data transmission state, it connects to user side, and the function of described fpga is mainly wrapped
Include the synchronizing signal for detecting transceiving data, and determine the sequential of transceiving data according to the edge of synchronizing signal；And then to
Family end sends the control character of transceiving data sequential；
It is connected with described fpga chip when local side is in transmission information state, row cache is entered with to be forwarded to its data
Storing mechanism 12, it is in the sequential of transceiving data as needed to user data after buffer-stored, to send out
Data time sequence is sent to be forwarded accordingly when arriving.Cooperation between three is passed through using this scheme, and then guarantees all systems
System transceiving data is synchronous, thus eliminating near-end cross impact, utilizes external ddr data storage, in conjunction with synchronizing signal side simultaneously
Edge, the storage that fpga realizes user data forwards, can adjust of external clock frequency, meets the transmission delay demand of user, tool
Have can implementation result good, application is strong, and adaptability is good, the stable benefit of transmission performance.And, this mode is one
Plant the explanation of preferred embodiments, but be not limited thereto.When implementing this utility model, can be carried out suitably according to user demand
Replacement and/or modification.
As shown in figure 1, in another kind of example, described fpga chip pass through a data filtering coupling unit 13 so that with
Family end connects, with build in same a bundle cable realize multi-thread to copper transmission link.Adopt this scheme with to being transmitted across
Transceiving data in journey carries out filtering, processes so that its transmission performance is stable, have can implementation result good, laser propagation effect is stable
The strong benefit of property.And, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.Implementing this reality
When using new, suitable replacement and/or modification can be carried out according to user demand.
As shown in figure 1, in another kind of example, described data filtering coupling unit includes:
One is connected with described fpga chip, with the upstream data transmitting through it or downlink data are carried out digital-to-analogue conversion,
Analog front-end chip afe 1,230 14 of filtering, it is mainly used in realizing the da/ad conversion of data and line filter, driving etc.
Function, and coordinate fpga to interact the clock of correlation, data message；
It is arranged on the circuit coupling mechanism 15 of described afe1230 signal output part, such as: coupling unit, it is used for will
Signal through the output of fpga chip is coupled in copper twisted pairs, and then realizes entering row information by copper cash between local side and user side
Transmission；
It is arranged between described afe 1230 signal output part and circuit coupling mechanism, with the letter to input to afe1230
Number the filter filter 16 being filtered for the first time or filter circuit, the signal that it is used for transmitting user side is filtered
Filter exports to afe 1230 after arranging.Using this scheme have can implementation result good, data transfer lead to stable favourable it
Place.And, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.When implementing this utility model, permissible
Suitable replacement and/or modification are carried out according to user demand.
As shown in figure 1, in another kind of example, described fpga pass through data transmission interface mii so that with ether net unit 4
Connect, to build network data transmission system, complete the conversion of rgmii data and serial data；Wherein fpga carries out serial ports number
According to encoding and decoding and conversion, and cache to memorizer, to realize to the data transfer in Ethernet.Using this scheme tool
Having can good, the workable benefit of implementation result.And, this mode is a kind of explanation of preferred embodiments, but simultaneously
It is not limited to this.When implementing this utility model, suitable replacement and/or modification can be carried out according to user demand.
As shown in figure 1, in another kind of example, described fpga by parallel bus be connected with one to its principal and subordinate, speed,
Transmitting-receiving gain carries out the microprocessor cpu 17 of relevant parameter configuration, and the function of described cpu is included according to cpu configuration order pair
Fpga carries out the configurations such as principal and subordinate, speed, transmitting-receiving gain, is sending principal and subordinate, speed, transmitting-receiving increasing by parallel bus to fpga simultaneously
Benefit etc. order it is also desirable to according to user data transmission the demand to time delay, adjustment external clock frequency with reduce transmission system
The delay of system is it is ensured that Consumer's Experience.Using this scheme, can need its time delay etc. is carried out according to using to make it have
Adjustment, complies with and uses needs accordingly, having can good, the workable benefit of implementation result.And, it is this
Mode is a kind of explanation of preferred embodiments, but is not limited thereto.When implementing this utility model, can be according to user need
Ask and carry out suitable replacement and/or modification.
In another kind of example, described storing mechanism is external ddr memorizer.Adopt this scheme to make it easier to reality
Existing, structure is simple, beneficial to the benefit of later maintenance.And, this mode is a kind of explanation of preferred embodiments, but not
It is confined to this.When implementing this utility model, suitable replacement and/or modification can be carried out according to user demand.
As shown in figure 1, in another kind of example, also include with as cpu, fpga and afe1230 provide 5.0v, 3.3v,
The power module 18 of 1.8v, 1.1v running voltage.Using this scheme, each part of device is provided with accordingly stable work electricity
Source, to guarantee its stable working state, having can good, the workable benefit of implementation result.And, this mode is only
It is a kind of explanation of preferred embodiments, but be not limited thereto.When implementing this utility model, can be carried out according to user demand
Suitable replacement and/or modification.
As shown in Figure 3-4, a kind of application described multi-thread to copper transmission in eliminate the method for near-end cross device
Implementation, comprising:
Described signal generator produces has rising edge and trailing edge synchronizing clock signals accordingly；
The fpga of each described local side, based on the synchronizing clock signals detecting, is judged current to determine each local side
Sequential is in rising edge or trailing edge；
If current sequential is in rising edge, each local side is both configured to send data mode, and corresponding each user
End is then configured to receiving data state；
Conversely, then each local side is both configured to receiving data state, and corresponding each user side is then configured to send out
Send data mode, realize the transmitting-receiving sequential of local side and user side is managed collectively, with the copper transmission system of not collinear pair
In system, each local side, the sending signal of each user side or receiving state signal are uniformly controlled, and then avoid the up letter of near-end
Crosstalk number and downstream signal between.Using the method for this scheme, it is based on copper transmission system, by uniting to all local sides
One one transceiving data synchronizing signal of offer, so that each local side is according to the rising edge of synchronizing signal and trailing edge unified management office
End and the transceiving data sequential of user side, are sent and received signal with the copper transmission system that ensure that not collinear pair simultaneously, keep away
Exempt from sending signal interference " near-end " receiving terminal, improve effective transmission bandwidth, lifting residential customer, commercial user etc. have accessed energy
The benefit of power.And, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.Implementing this practicality
When new, suitable replacement and/or modification can be carried out according to user demand.
As shown in figure 4, in another kind of example, described fpga passes through the data of mii interface ether net unit transmission
Information, and it is accomplished to the protocol conversion of serial data, then by the storing mechanism being connected with fpga, it is received to data message
Enter row buffering caching, when the clock sync signal sequential that it detects is in rising edge, to send to user side and to count accordingly
It is believed that ceasing, the output clock frequency of described signal generator is configured to f=(n × 1) khz, wherein n ∈ (1,2 ..., 1000).
Adopt this scheme under different sequential, data transfer to be preserved to coordinate, prevent the adverse effect that its loss causes, with
When the design parameter of signal generator is illustrated, allow it to make the copper transmission system of not collinear pair in transceiving data
When keep synchronous, it is to avoid a line disturbs another line to receipt signal to sending signal near-end, thus avoiding near-end cross, tool
Having can good, the workable benefit of implementation result.And, this mode is a kind of explanation of preferred embodiments, but simultaneously
It is not limited to this.When implementing this utility model, suitable replacement and/or modification can be carried out according to user demand.
As shown in figure 4, in another kind of example, if the clock sync signal sequential that described fpga real-time detection arrives is i.e. not
Be rising edge, be not trailing edge, then before executing corresponding serial data to the conversion of mii or mii turning to serial data
Change.Adopt this scheme adapting to specifically operate needs, have can implementation result, workable, adaptability is good, transporting
The stable benefit of energy.And, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.Implementing this
During utility model, suitable replacement and/or modification can be carried out according to user demand.
Number of devices described herein and treatment scale are used to simplify explanation of the present utility model.To this utility model
Multi-thread to copper transmission in eliminate the application of device and method of near-end cross, modifications and variations to those skilled in the art
It is obvious for member.
Although embodiment of the present utility model is disclosed as above, it is not restricted in description and embodiment
Listed utilization.It can be applied to various suitable fields of the present utility model completely.For those skilled in the art,
It is easily achieved other modification.Therefore under the general concept being limited without departing substantially from claim and equivalency range, this reality
It is not limited to specific details with new and shown here as the legend with description.
Claims (7)
1. a kind of multi-thread to copper transmission in eliminate near-end cross device, including multi-thread for realizing in same a bundle cable
Multiple local sides to copper transmission, and the user side being matched therewith is it is characterised in that also include:
It is arranged on local side side, occur in order to produce the signal with rising edge and trailing edge synchronizing clock signals to each local side
Device；
It is arranged on each local side and is connected with described signal generator, to control office data according to the synchronizing clock signals receiving
The field programmable gate array fpga chip of transmission state, it connects to user side；
It is connected with described fpga chip when local side is in transmission information state, row cache is entered to its data and is deposited with to be forwarded
Storage mechanism.
2. as claimed in claim 1 multi-thread to copper transmission in eliminate the device of near-end cross it is characterised in that described
Fpga chip is passed through a data filtering coupling unit and then is connected with user side, is realized multi-thread with structure in same a bundle cable
To copper transmission link.
3. as claimed in claim 1 multi-thread to copper transmission in eliminate the device of near-end cross it is characterised in that described number
Include according to filter-coupler unit:
One is connected with described fpga chip, to carry out digital-to-analogue conversion, filtering to the upstream data transmitting through it or downlink data
Analog front-end chip afe1230；
It is arranged on the circuit coupling mechanism of described afe1230 signal output part；
It is arranged between described afe1230 signal output part and circuit coupling mechanism, carried out with the signal to input to afe1230
The first filter filter filtering or filter circuit.
4. as claimed in claim 1 multi-thread to copper transmission in eliminate the device of near-end cross it is characterised in that described
Fpga is passed through data transmission interface mii and then is connected, to build network data transmission system with ether net unit.
5. as claimed in claim 2 multi-thread to copper transmission in eliminate the device of near-end cross it is characterised in that described
Fpga is connected with one by parallel bus and carries out the microprocessor of relevant parameter configuration to its principal and subordinate, speed, transmitting-receiving gain
cpu.
6. as claimed in claim 1 multi-thread to copper transmission in eliminate the device of near-end cross it is characterised in that described deposit
Storage mechanism is external ddr memorizer.
7. as claimed in claim 5 multi-thread to copper transmission in eliminate the device of near-end cross it is characterised in that also including
With as cpu, fpga and afe1230 provide 5.0v, 3.3v, 1.8v, 1.1v running voltage power module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620945400.4U CN205912049U (en) | 2016-08-25 | 2016-08-25 | At multi -thread device of eliminating near -end cross in to copper line transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620945400.4U CN205912049U (en) | 2016-08-25 | 2016-08-25 | At multi -thread device of eliminating near -end cross in to copper line transmission |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205912049U true CN205912049U (en) | 2017-01-25 |
Family
ID=57800561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620945400.4U Active CN205912049U (en) | 2016-08-25 | 2016-08-25 | At multi -thread device of eliminating near -end cross in to copper line transmission |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205912049U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209165A (en) * | 2016-08-25 | 2016-12-07 | 四川灵通电讯有限公司 | Multi-thread to copper transmission in eliminate the device and method of near-end cross |
-
2016
- 2016-08-25 CN CN201620945400.4U patent/CN205912049U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209165A (en) * | 2016-08-25 | 2016-12-07 | 四川灵通电讯有限公司 | Multi-thread to copper transmission in eliminate the device and method of near-end cross |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100499872C (en) | Voice-over IP communication without echo cancellation | |
| CN101707544B (en) | E1 channel multidirectional network bridge transmission method | |
| EP1520374A4 (en) | Wireless internet access system | |
| CN106209165B (en) | It is multi-thread to copper transmission in eliminate near-end cross device and method | |
| CN105099954A (en) | Transformer substation process layer message networking-sharing port-sharing transmission system | |
| CN205912049U (en) | At multi -thread device of eliminating near -end cross in to copper line transmission | |
| CN105553795B (en) | A method of the transmission standard Ethernet data in Industrial Ethernet | |
| CN205829667U (en) | A kind of communication gate of RTEX Yu DeviceNET | |
| US7293123B2 (en) | Asymmetric data path media access controller | |
| CN110166340A (en) | T-NET full system type pictorial single line multi-source data acquiring and transmission system | |
| CN114257245A (en) | Multichannel AD acquisition system based on DSP-FPGA | |
| CN103618656A (en) | Master-slave nodes of networked logging downhole instrument and data processing method thereof | |
| CN108667706A (en) | The adjustable Ethernet serial server of serial ports quantity dynamic and its data transmission method | |
| CN203554447U (en) | Gigabit intelligent type optical fiber transceiver | |
| CN104267312A (en) | Embedded travelling wave distance measuring device based on LVDS high-speed sampling | |
| CN101562488B (en) | Method for utilizing frame gap to transmit in-phase clock information in gigabit Ethernet | |
| CN208015747U (en) | Non-intervention type multiprotocol network data acquisition device | |
| CN202817898U (en) | Power distribution terminal based on EtherCAT industrial Ethernet | |
| CN202353828U (en) | System on programmable chip (SOPC)-based wireless bridge module | |
| CN101771617B (en) | Method and system for following point-to-point bandwidth, remote terminal equipment and home terminal equipment | |
| CN209627384U (en) | A kind of system for realizing remote POE transmission | |
| CN202127418U (en) | Composite network card integrating gigabit Ethernet and ten gigabit Ethernet | |
| CN207612262U (en) | A kind of device controlling frequency converter with dual network | |
| CN209151300U (en) | A kind of T-type distribution Ethernet line concentrator | |
| CN102611615B (en) | FPGA (Field Programmable Gate Array)-based integrated system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |