CN205880554U - Network cascades inefficacy control circuit and equipment - Google Patents
Network cascades inefficacy control circuit and equipment Download PDFInfo
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- CN205880554U CN205880554U CN201620885452.7U CN201620885452U CN205880554U CN 205880554 U CN205880554 U CN 205880554U CN 201620885452 U CN201620885452 U CN 201620885452U CN 205880554 U CN205880554 U CN 205880554U
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Abstract
The utility model belongs to communication and electronics field provide the inefficacy controlling means that a network cascades, the inefficacy controlling means that the network cascades includes: first circuit, second circuit, tertiary circuit, fourth circuit and control chip. The application provides a technical scheme has reliability height, the stable advantage of network.
Description
Technical Field
The utility model belongs to communication and electron field especially relate to a network cascade failure control circuit and equipment.
Background
In the rail transit application of the people, on trains such as subways, trams, high-speed rails and the like, several to dozens of devices in each carriage need to communicate with a server, the server sends contents such as pictures, characters, videos, station information and the like to each client device through a network, and the client need to work independently without mutual influence. On the train, due to the limitations of space, wiring convenience and the like, a reliable, simple and practical wiring mode which is easy to install is needed.
Disclosure of Invention
An object of the utility model is to provide a cascaded failure control device of network aims at solving the stability of communication between server and a plurality of customer ends on the track traffic, reliable problem.
The application provides a cascaded failure control device of network, cascaded failure control device of network includes: the circuit comprises a first circuit, a second circuit, a third circuit, a fourth circuit and a control chip; wherein
The first circuit includes: a resistor, a capacitor, a diode, a first relay LS 1; wherein,
the GPOP1 of the control chip is connected with one end of a third resistor, the other end of the third resistor is connected with the base electrode of a first triode, the collector electrode of the first triode is connected with the pin No. 8 of a first relay LS1, the pin No. 1 of LS1 is connected with the other end of a first resistor, one end of the first resistor is connected with a voltage source, the anode of the first diode is connected with the collector electrode of the first triode, the cathode of the first diode is connected with the other end of the first resistor, one end of a first capacitor is connected with the other end of the first resistor, and the other end of the first capacitor is connected with the collector electrode of the first triode; no. 6 pin of the first relay LS1 is connected with a LAN1_ TXN signal end, No. 3 pin of the first relay LS1 is connected with a LAN1_ TXP signal end, No. 7 pin of the first relay LS1 is connected with a LAN2_ TXN signal end, No. 2 pin of the first relay LS1 is connected with a LAN2_ TXP signal end, No. 5 pin of the first relay LS1 is connected with a PA _ TXN signal end, and No. 4 pin of the first relay LS1 is connected with a PA _ TXN signal end; one end of the fifth resistor is connected with the other end of the third resistor, the other end of the fifth resistor is grounded, and the emitting electrode of the first triode Q1 is grounded;
the second circuit includes: a resistor, a capacitor, a diode, a second relay LS 2; wherein,
GPOP1 of the control chip) is connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the base electrode of a second triode, the collector electrode of the second triode is connected with the pin No. 8 of a second relay LS2, the pin No. 1 of LS2 is connected with the other end of a second resistor, one end of the second resistor is connected with a voltage source, the anode of a second diode is connected with the collector electrode of the second triode, the cathode of the second diode is connected with the other end of the second resistor, one end of a second capacitor is connected with the other end of the second resistor, and the other end of the second capacitor is connected with the collector electrode of the second triode; a pin No. 6 of a second relay LS2 is connected with a LAN1_ RXN signal end, a pin No. 3 of a second relay LS2 is connected with a LAN1_ RXP signal end, a pin No. 7 of the second relay LS2 is connected with a LAN2_ RXN signal end, a pin No. 2 of a second relay LS2 is connected with a LAN2_ RXP signal end, a pin No. 5 of the second relay LS2 is connected with a PA _ RXN signal end, and a pin No. 4 of the second relay LS2 is connected with a PA _ RXN signal end; one end of the sixth resistor is connected with the other end of the fourth resistor, the other end of the sixth resistor is grounded, and an emitting electrode of the second triode is grounded;
the third circuit includes: a resistor, a capacitor, a diode, a third relay LS 3; wherein,
the GPOP2 of the control chip is connected with one end of a ninth resistor, the other end of the ninth resistor is connected with the base electrode of a third triode, the collector electrode of the third triode is connected with the pin No. 8 of a third relay LS3, the pin No. 1 of LS3 is connected with the other end of a seventh resistor, one end of the seventh resistor is connected with a voltage source, the anode of a fourth diode is connected with the collector electrode of the third triode, the cathode of the fourth diode is connected with the other end of the seventh resistor, one end of a fourth capacitor is connected with the other end of the seventh resistor, and the other end of the fourth capacitor is connected with the collector electrode of the third triode; pin 6 of the third relay LS3 is connected with a PA _ TXN signal end, pin 3 of the third relay LS3 is connected with a PA _ TXP signal end, pin 7 of the third relay LS3 is disconnected, pin 2 of the third relay LS3 is disconnected, pin 5 of the third relay LS3 is connected with a LAN2_ TXN signal end, and pin 4 of the third relay LS3 is connected with a LAN2_ TXP signal end; one end of an eleventh resistor R11 is connected with the other end of the ninth resistor, the other end of the eleventh resistor is grounded, and an emitter of the third triode is grounded;
the fourth circuit includes: a resistor, a capacitor, a diode, a fourth relay LS 4; wherein,
the GPOP2 of the control chip is connected with one end of a tenth resistor, the other end of the tenth resistor is connected with the base electrode of a fourth triode, the collector electrode of the fourth triode is connected with the pin No. 8 of a fourth relay LS4, the pin No. 1 of LS4 is connected with the other end of the tenth resistor, one end of the tenth resistor is connected with a voltage source, the anode of a third diode is connected with the collector electrode of the fourth triode, the cathode of the third diode is connected with the other end of the tenth resistor, one end of a third capacitor is connected with the other end of an eighth resistor, and the other end of the fourth capacitor is connected with the collector electrode of the third triode; no. 6 pin of the fourth relay LS4 is connected with a PA _ RXN signal end, No. 3 pin of the fourth relay LS4 is connected with a PA _ RXP signal end, No. 7 pin of the fourth relay LS4 is disconnected, No. 2 pin of the fourth relay LS4 is disconnected, No. 5 pin of the fourth relay LS4 is connected with a LAN2_ RXN signal end, No. 4 pin of the fourth relay LS4 is connected with a LAN2_ RXP signal end, one end of a twelfth resistor is connected with the other end of a tenth resistor, the other end of the twelfth resistor is grounded, and an emitter of a fourth triode is grounded.
The application provides a network device, which comprises the network cascade failure control device.
In the embodiment of the utility model, the utility model provides an in the technical scheme whether the network state of any single equipment in the cascade equipment is normal, all not influence the network equipment of its next grade and connect, so it has the stability of communication between a plurality of customer ends, reliable advantage.
Drawings
Fig. 1 is a first circuit diagram of a network cascade failure control device according to a first preferred embodiment of the present invention;
fig. 2 is a second schematic circuit diagram of a network cascade failure control device according to a first preferred embodiment of the present invention;
fig. 3 is a third schematic circuit diagram of a network cascade failure control device according to a first preferred embodiment of the present invention;
fig. 4 is a fourth circuit diagram of the network cascade failure control apparatus according to the first preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A first preferred embodiment of the present invention provides a network cascade failure control device, which comprises a first circuit, a second circuit, a third circuit, a fourth circuit, a control chip, and a voltage source, referring to fig. 1, fig. 2, fig. 3, and fig. 4, wherein,
the first circuit comprises (as shown in fig. 1): a resistor, a capacitor, a diode and a first relay LS1 (model: G6J-2P-Y-5V); wherein,
a GPOP1 (No. 1 universal input and output pin) of the control chip is connected with one end of a third resistor R3, the other end of the third resistor R3 is connected with a base electrode of a first triode Q1, a collector electrode of a first triode Q1 is connected with a No. 8 pin of a first relay LS1, a No. 1 pin of an LS1 is connected with the other end of a first resistor R1, one end of the first resistor R1 is connected with a voltage source, an anode of a first diode D1 is connected with a collector electrode of the first triode Q1, a cathode of a first diode D1 is connected with the other end of a first resistor R1, one end of a first capacitor C1 is connected with the other end of a first resistor R1, and the other end of a first capacitor C1 is connected with a collector electrode of a first triode Q39; no. 6 pin of the first relay LS1 is connected with a LAN1_ TXN signal end, No. 3 pin of the first relay LS1 is connected with a LAN1_ TXP signal end, No. 7 pin of the first relay LS1 is connected with a LAN2_ TXN signal end, No. 2 pin of the first relay LS1 is connected with a LAN2_ TXP signal end, No. 5 pin of the first relay LS1 is connected with a PA _ TXN signal end, and No. 4 pin of the first relay LS1 is connected with a PA _ TXN signal end; one end of the fifth resistor R5 is connected with the other end of the third resistor R3, the other end of the fifth resistor R5 is grounded, and the emitter of the first triode Q1 is grounded;
the second circuit comprises (as shown in fig. 2): a resistor, a capacitor, a diode and a second relay LS2 (model: G6J-2P-Y-5V); wherein,
a GPOP1 (universal input/output pin 1) of the control chip is connected with one end of a fourth resistor R4, the other end of the fourth resistor R4 is connected with a base electrode of a second triode Q2, a collector electrode of the second triode Q2 is connected with a pin 8 of a second relay LS2, a pin 1 of an LS2 is connected with the other end of a second resistor R2, one end of the second resistor R2 is connected with a voltage source, an anode of a second diode D2 is connected with a collector electrode of the second triode Q2, a cathode of a second diode D2 is connected with the other end of the second resistor R2, one end of a second capacitor C2 is connected with the other end of the second resistor R2, and the other end of the second capacitor C2 is connected with a collector electrode of the second triode Q2; a pin No. 6 of a second relay LS2 is connected with a LAN1_ RXN signal end, a pin No. 3 of a second relay LS2 is connected with a LAN1_ RXP signal end, a pin No. 7 of the second relay LS2 is connected with a LAN2_ RXN signal end, a pin No. 2 of a second relay LS2 is connected with a LAN2_ RXP signal end, a pin No. 5 of the second relay LS2 is connected with a PA _ RXN signal end, and a pin No. 4 of the second relay LS2 is connected with a PA _ RXN signal end; one end of the sixth resistor R6 is connected with the other end of the fourth resistor R4, the other end of the sixth resistor R6 is grounded, and the emitter of the second triode Q2 is grounded;
the third circuit comprises (as shown in fig. 3): a resistor, a capacitor, a diode and a third relay LS3 (model: G6J-2P-Y-5V); wherein,
a GPOP2 (No. 2 universal input/output pin) of the control chip is connected with one end of a ninth resistor R9, the other end of the ninth resistor R9 is connected with a base electrode of a third triode Q3, a collector electrode of a third triode Q3 is connected with a No. 8 pin of a third relay LS3, a No. 1 pin of an LS3 is connected with the other end of a seventh resistor R7, one end of the seventh resistor R7 is connected with a voltage source, an anode of a fourth diode D4 is connected with a collector electrode of the third triode Q3, a cathode of a fourth diode D4 is connected with the other end of the seventh resistor R7, one end of a fourth capacitor C4 is connected with the other end of the seventh resistor R7, and the other end of the fourth capacitor C4 is connected with a collector electrode of the third triode Q39; pin 6 of the third relay LS3 is connected with a PA _ TXN signal end, pin 3 of the third relay LS3 is connected with a PA _ TXP signal end, pin 7 of the third relay LS3 is disconnected, pin 2 of the third relay LS3 is disconnected, pin 5 of the third relay LS3 is connected with a LAN2_ TXN signal end, and pin 4 of the third relay LS3 is connected with a LAN2_ TXP signal end; one end of an eleventh resistor R11 is connected with the other end of the ninth resistor R9, the other end of the eleventh resistor R11 is grounded, and the emitter of the third triode Q3 is grounded;
the fourth circuit comprises (as shown in fig. 4): a resistor, a capacitor, a diode and a fourth relay LS4 (model: G6J-2P-Y-5V); wherein,
a GPOP2 (universal input/output pin No. 2) of the control chip is connected with one end of a tenth resistor R10, the other end of the tenth resistor R10 is connected with a base of a fourth triode Q4, a collector of the fourth triode Q4 is connected with a pin No. 8 of a fourth relay LS4, a pin No. 1 of an LS4 is connected with the other end of a tenth resistor R10, one end of the tenth resistor R10 is connected with a voltage source, an anode of a third diode D3 is connected with a collector of a fourth triode Q4, a cathode of a third diode D3 is connected with the other end of a tenth resistor R10, one end of a third capacitor C3 is connected with the other end of an eighth resistor R8, and the other end of a fourth capacitor C4 is connected with a collector of a third triode Q3; pin 6 of the fourth relay LS4 is connected to a PA _ RXN signal terminal, pin 3 of the fourth relay LS4 is connected to a PA _ RXP signal terminal, pin 7 of the fourth relay LS4 is disconnected, pin 2 of the fourth relay LS4 is disconnected, pin 5 of the fourth relay LS4 is connected to a LAN2_ RXN signal terminal, pin 4 of the fourth relay LS4 is connected to a LAN2_ RXP signal terminal, one end of a twelfth resistor R12 is connected to the other end of a tenth resistor R10, the other end of the twelfth resistor R12 is grounded, and an emitter of a fourth triode Q4 is grounded.
The above device has the following 2 states:
the 1 st: when the client control board normally works, the 5V power supply in the circuit is normal, the control chip (for example, a CPU (Central processing Unit) possibly differs for different devices according to the type of the CPU) sets high level for the control pins of the GPIO1 and the GPIO2, the four triodes are conducted, the four relays enter a working state, the 3 pins and the 4 pins in the four relays are conducted, and the 5 pins and the 6 pins are conducted. The externally accessed network signal LAN1 enters the mainboard through PA _ TXN, PA _ TXP and PA _ RXN respectively, and the PA _ RXP exchanges data with the network chip (such as KSZ8863) of the mainboard; while cascading to the next level of network through LAN 2.
The 2 nd: when the mainboard of the client side has faults of crash, short circuit and the like, the 5V output of the power supply is abnormal, or the GPIO pin does not work after the CPU crashes, so that the triode is cut off. The relay stops working. The 3 pin and the 4 pin in the relay are disconnected, and the 5 pin and the 6 pin are disconnected; and the pin 2 is connected with the pin 3, and the pin 6 is connected with the pin 7. At this time, the external network signal is disconnected from the internal network chip of the motherboard, and the LAN1 is directly connected to the LAN2 and then enters the next-level network. The scheme avoids the influence on other clients when any one client on the line fails.
To sum up, the utility model provides a technical scheme has the stability of communication, reliable advantage.
The application also provides a network device, which comprises the network cascade failure control device.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (2)
1. A network cascade failure control apparatus, comprising: the circuit comprises a first circuit, a second circuit, a third circuit, a fourth circuit and a control chip; wherein
The first circuit includes: a resistor, a capacitor, a diode, a first relay LS 1; wherein,
the GPOP1 of the control chip is connected with one end of a third resistor, the other end of the third resistor is connected with the base electrode of a first triode, the emitting electrode of the first triode is connected with the No. 8 pin of a first relay LS1, the No. 1 pin of LS1 is connected with the other end of a first resistor, one end of the first resistor is connected with a voltage source, the anode of the first diode is connected with the collector electrode of the first triode, the cathode of the first diode is connected with the other end of the first resistor, one end of a first capacitor is connected with the other end of the first resistor, and the other end of the first capacitor is connected with the collector electrode of the first triode; no. 6 pin of the first relay LS1 is connected with a LAN1_ TXN signal end, No. 3 pin of the first relay LS1 is connected with a LAN1_ TXP signal end, No. 7 pin of the first relay LS1 is connected with a LAN2_ TXN signal end, No. 2 pin of the first relay LS1 is connected with a LAN2_ TXP signal end, No. 5 pin of the first relay LS1 is connected with a PA _ TXN signal end, and No. 4 pin of the first relay LS1 is connected with a PA _ TXN signal end; one end of the fifth resistor is connected with the other end of the third resistor, the other end of the fifth resistor is grounded, and the emitting electrode of the first triode Q1 is grounded;
the second circuit includes: a resistor, a capacitor, a diode, a second relay LS 2; wherein,
the GPOP1 of the control chip is connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the base electrode of a second triode, the collector electrode of the second triode is connected with the pin No. 8 of the second relay LS2, the pin No. 1 of the LS2 is connected with the other end of the second resistor, one end of the second resistor is connected with a voltage source, the anode of a second diode is connected with the collector electrode of the second triode, the cathode of the second diode is connected with the other end of the second resistor, one end of a second capacitor is connected with the other end of the second resistor, and the other end of the second capacitor is connected with the collector electrode of the second triode; a pin No. 6 of a second relay LS2 is connected with a LAN1_ RXN signal end, a pin No. 3 of a second relay LS2 is connected with a LAN1_ RXP signal end, a pin No. 7 of the second relay LS2 is connected with a LAN2_ RXN signal end, a pin No. 2 of a second relay LS2 is connected with a LAN2_ RXP signal end, a pin No. 5 of the second relay LS2 is connected with a PA _ RXN signal end, and a pin No. 4 of the second relay LS2 is connected with a PA _ RXN signal end; one end of the sixth resistor is connected with the other end of the fourth resistor, the other end of the sixth resistor is grounded, and an emitting electrode of the second triode is grounded;
the third circuit includes: a resistor, a capacitor, a diode, a third relay LS 3; wherein,
the GPOP2 of the control chip is connected with one end of a ninth resistor, the other end of the ninth resistor is connected with the base electrode of a third triode, the collector electrode of the third triode is connected with the pin No. 8 of a third relay LS3, the pin No. 1 of LS3 is connected with the other end of a seventh resistor, one end of the seventh resistor is connected with a voltage source, the anode of a fourth diode is connected with the collector electrode of the third triode, the cathode of the fourth diode is connected with the other end of the seventh resistor, one end of a fourth capacitor is connected with the other end of the seventh resistor, and the other end of the fourth capacitor is connected with the collector electrode of the third triode; pin 6 of the third relay LS3 is connected with a PA _ TXN signal end, pin 3 of the third relay LS3 is connected with a PA _ TXP signal end, pin 7 of the third relay LS3 is disconnected, pin 2 of the third relay LS3 is disconnected, pin 5 of the third relay LS3 is connected with a LAN2_ TXN signal end, and pin 4 of the third relay LS3 is connected with a LAN2_ TXP signal end; one end of an eleventh resistor R11 is connected with the other end of the ninth resistor, the other end of the eleventh resistor is grounded, and an emitting electrode of the third triode is grounded;
the fourth circuit includes: a resistor, a capacitor, a diode, a fourth relay LS 4; wherein,
the GPOP2 of the control chip is connected with one end of a tenth resistor, the other end of the tenth resistor is connected with the base electrode of a fourth triode, the collector electrode of the fourth triode is connected with the pin No. 8 of a fourth relay LS4, the pin No. 1 of LS4 is connected with the other end of the tenth resistor, one end of the tenth resistor is connected with a voltage source, the anode of a third diode is connected with the collector electrode of the fourth triode, the cathode of the third diode is connected with the other end of the tenth resistor, one end of a third capacitor is connected with the other end of an eighth resistor, and the other end of the fourth capacitor is connected with the collector electrode of the third triode; no. 6 pin of the fourth relay LS4 is connected with a PA _ RXN signal end, No. 3 pin of the fourth relay LS4 is connected with a PA _ RXP signal end, No. 7 pin of the fourth relay LS4 is disconnected, No. 2 pin of the fourth relay LS4 is disconnected, No. 5 pin of the fourth relay LS4 is connected with a LAN2_ RXN signal end, No. 4 pin of the fourth relay LS4 is connected with a LAN2_ RXP signal end, one end of a twelfth resistor is connected with the other end of a tenth resistor, the other end of the twelfth resistor is grounded, and an emitter of a fourth triode is grounded.
2. A network device, characterized in that it comprises a network cascade of failure control means according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620885452.7U CN205880554U (en) | 2016-08-15 | 2016-08-15 | Network cascades inefficacy control circuit and equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620885452.7U CN205880554U (en) | 2016-08-15 | 2016-08-15 | Network cascades inefficacy control circuit and equipment |
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| Publication Number | Publication Date |
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| CN205880554U true CN205880554U (en) | 2017-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201620885452.7U Ceased CN205880554U (en) | 2016-08-15 | 2016-08-15 | Network cascades inefficacy control circuit and equipment |
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| CN (1) | CN205880554U (en) |
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