CN205879203U - A digital integrator for superconducting cyclotron magnetic -field measurement - Google Patents
A digital integrator for superconducting cyclotron magnetic -field measurement Download PDFInfo
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- CN205879203U CN205879203U CN201620819475.8U CN201620819475U CN205879203U CN 205879203 U CN205879203 U CN 205879203U CN 201620819475 U CN201620819475 U CN 201620819475U CN 205879203 U CN205879203 U CN 205879203U
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Abstract
The utility model relates to a digital integrator for superconducting cyclotron magnetic -field measurement, through the size that suitable preamp circuit PGA adjusted incoming signal, the signal after enlargeing is in the active integrator upper integral of simulation, the output voltage of integrator sets for a set of door electricity limiting and presses on being connected to a window comparator, in case electric capacity reaches the threshold value, then output signal gives FPGA, FPGA judges this signal to control repid discharge circuit, the voltage repid discharge that makes the electric capacity both ends are to 0, and the new integration period of beginning. Through the discharge number that fills who acquires electric capacity to utilize AD to acquire the residual voltage, pass through scale conversion, can obtain incoming signal's size. The utility model is suitable for an environment such as magnetic field and electric current are measured to coil class and other long signal output type sensor, have the characteristics of high efficiency, high accuracy, low cost.
Description
Technical field
This utility model relates to a kind of digital integrator for superconducting cyclotron magnetic-field measurement.Belong to electronic circuit
Technical field.
Background technology
Using coil class method such as: search coil, revolving coil, flip coils, Luo-coil, long line and magnetic probe
Deng, during measuring electric current, magnetic field etc., integrator is receiving and the key modules processed of its output signal.Common is long-pending
Point device includes that simulation, numeral and digital-to-analogue combine three major types: digital integrator uses at a high speed, high-precision ADC samples, with
Shi Peihe many algorithms, carries out numerical computations in the processor such as high speed FPGA or high-speed dsp.Its hardware is with software cost relatively
Height, and the existence of high speed, high-precision adc is abroad to condition restrictions such as domestic embargoes.By contrast, analogue integrator is due to circuit knot
Structure is simple and with low cost and is widely used in a variety of applications, but analogue integrator is vulnerable to the factor such as temperature, capacity fall off resistance
Impact, makes analogue integrator in use receive a lot of restriction.The integrator using digital-to-analogue to combine, can both obtain
The advantage that numeric type integrator precision is high, can take into account again the defect such as cost, chip acquisition, overcomes the analogue integrator cannot simultaneously
Solve the defect of capacity fall off resistance.
The ohmic leakage of non-zero points symmetry, integrator drift and the electric capacity of circuit itself is the master causing analogue integrator error
Want factor.Although there being the drift of substantial amounts of scholar's research analogue integrator, and improve the size that capacity fall off hinders, but
These factors do not eliminate, and are only merely and are suppressed.In the case of current certainty of measurement requires day by day to improve, traditional
Analogue integrator cannot meet demand.All there is the hidden danger that integration overflows in traditional analog integrator simultaneously, and great majority simulation is long-pending
Parallel circuit all adds input protection, or input limits, and this also limits the range of integrator, decreases range of application.
The integrator using digital-to-analogue to combine is to be simulated by digital compensation mostly, gathers voltage deviation by AD, then
By DA by charge compensation to electric capacity.The effect of this compensation way is preferable, but still cannot be fully solved drift, the most also
The capacitance size restriction to range cannot be solved.
Utility model content
The purpose of this utility model is to solve to cause integrator to there is the problem of integration leakage due to capacity fall off resistance,
By improving the operation principle of digital analogue type integrator, it is proposed that a kind of digital integrator.
For overcoming drift that traditional analog integrator exists and voltage to keep, and meet wanting of high accuracy integrator
Ask, the integration of the completeest pair signals of digital integrator of the present utility model.
First, use PGA the signal that coil (or other) produces is amplified to a suitable value (choose certainty of measurement with
Measurement scope), coordinate LEMO transmission line, enter integrator.
Then, sent manually by communication interface or periodic measurement instructs that (this step does not change the break-make of integrator
State, simply FPGA count internal resets, to obtain relative value).
When coil (or other sensors) produces signal, electric capacity both end voltage value changes, when capacitance voltage reaches default
During threshold value, FPGA control electric capacity repid discharge is to zero, and now electric capacity is still in integrating state.If signal still exists, then
Electric capacity continues integration.
When coil no longer moves, or when reaching measurement demand, read the value of FPGA, and read capacitor residual voltage by AD, i.e.
Integrated value can be obtained.
A kind of digital integrator that this utility model provides, overcomes the shadow of the capacitance leakage resistance of traditional analog integrator
Ring, and overcome the problem that analogue integrator exists upper limit of integral.Other digital integrators relatively, the number that this utility model provides
Word analogue integrator, it is not necessary to High Speed High Precision ADC, reduces the cost of integrator, and do not embargoed by ADC is affected simultaneously, and
Reach identical effect.
Accompanying drawing explanation
Fig. 1 is the system block diagram of this utility model digital integrator；
Fig. 2 is the digital processing part block diagram of digital integrator；
Fig. 3 is the principle of simulation figure of digital integrator.
Detailed description of the invention
With embodiment, this utility model is described in detail below in conjunction with the accompanying drawings.
As it is shown in figure 1, digital integrator of the present utility model includes: frontend amplifying circuit PGA (1), analogue active integration
Circuit (2), window comparator circuit (3), quick discharging circuit (4), balancing circuit (5), AD/DA digital to analog conversion circuit (6),
FPGA digital programmable gate circuit (7), 50MHz high speed crystal oscillator and 10MHz High Precision Crystal Oscillator circuit (8), RS232 serial port communication line
Road (9).
Signal initially enters frontend amplifying circuit PGA (1)；The output signal of frontend amplifying circuit PGA (1) enters simulation to be had
Source integration circuit (2)；The outfan of balancing circuit (5) and quick discharging circuit (4) accesses analogue active integration circuit (2)；
Window comparator circuit (3) is connected on the outfan of analogue active integration circuit (2), it is judged that whether electric capacity both end voltage value is limiting
Within；The output signal of window comparator circuit (3) enters FPGA digital programmable gate circuit (7)；FPGA digital programmable door
Circuit (7) controls quick discharging circuit (4)；50MHz high speed crystal oscillator and 10MHz High Precision Crystal Oscillator circuit (8), and RS232 serial ports
Communication line (9) connects FPGA digital programmable gate circuit (7)；AD/DA digital to analog conversion circuit (6) connects FPGA digital programmable
Gate circuit (7), and connect analogue active integration circuit (2), the output of DA is as the input of balancing circuit (5).
Frontend amplifying circuit PGA (1) comprises: use the fixed gain amplifying circuit that instrumentation amplifier is made, as first
Level amplifying circuit；Use the variable gain amplifying circuit that program control programmable amplifier is made, as second level amplifying circuit, pass through
FPGA digital programmable gate circuit (7) can regulate amplification.
Analogue active integration circuit (2) is conventional active integration circuit, and its principle is as it is shown on figure 3, comprise a high accuracy
Operational amplifier and an electric capacity with high bleeder resistance.
Window comparator circuit (3) is made up of the comparator of two Symmetricals, and generating positive and negative voltage threshold value is by high accuracy
Resistance collocation regulation；The output voltage values of window comparator passes through voltage conversion circuit, incoming FPGA digital programmable gate circuit
(7)。
Quick discharging circuit (4) comprises positive and negative high accuracy Ref power supply, with high speed, high disconnection impedance, the mould of low conduction impedance
Intending on-off circuit to constitute, controlled by the signal of FPGA digital programmable gate circuit (7), clock signal source is in 10MHz high accuracy
Crystal oscillating circuit；Output signal acts on analogue active integration circuit (2).
Balancing circuit (5) comprises two-way regulative mode, and a road is to consist of with potentiometer, as balance Ref power supply
Coarse adjustment；Another road is to consist of AD/DA digital to analog conversion circuit (6), as the fine tuning of balance.
AD/DA digital to analog conversion circuit (6) comprises, and 16, a road ADC and 16, road DAC:ADC gathers analogue active integration
The terminal voltage value of circuit (2) electric capacity, result incoming FPGA digital programmable gate circuit (7)；DAC is by FPGA digital programmable door electricity
Road (7) controls, and its output result inputs as the voltage of balancing circuit (5) fine tuning mode.
FPGA digital programmable gate circuit (7) comprises a piece of high speed FPGA, and it is the most brilliant that its clock signal derives from 50MHz
Shake, and utilize its internal frequency multiplication of phase locked loop, as the main control chip of digital integrator, and by RS232 serial communication circuit
(9) communication with host computer is realized.
AD/DA digital to analog conversion circuit (6) also achieves the closed loop feedback of circuit and controls: by FPGA digital programmable door electricity
The internal algorithm on road (7), it is achieved circuit self-balancing, the long-time output measured compensates.
The internal self-balancing regulation algorithm achieving circuit of FPGA digital programmable gate circuit (7), long-time measurement is dynamically
Voltage Compensation Control Method.
As shown in Figure 1, signal initially enters PGA, to improve signal magnitude and to improve to-noise ratio SNR, and the signal of PGA output
Entering in active integrator, the schematic diagram of active integrator is as shown in Figure 3.Signal is accumulated on active integrator, when simulation has
When voltage on the electric capacity of source integrator reaches certain value, control a rapid discharge circuit by FPGA, carry out repid discharge
(as shown in Figure 2), by the voltage electrical generation at electric capacity two ends to zero, discharge rate signal the to be far above input of repid discharge produces long-pending
The speed divided.
Signal is obtained by coil or other sensors, enters PGA:PGA by a piece of instrumentation amplifier and a piece of controlled increasing
Benefit amplifier is constituted, and instrumentation amplifier provides the first order to amplify, for fixing amplification.Controllable gain amplifier provides the second level to put
Greatly, its amplification can be controlled by FPGA.
Active integrator: by high-precision amplifying, form with the electric capacity with high bleeder resistance.For ensureing the work of electric capacity
Make in stable condition, choose the electric capacity that capacitance is less, and make the voltage at electric capacity two ends will not excessive (being hundreds of millivolt to the maximum).
Repid discharge module, the reference voltage source using magnitude of voltage higher is made with analog gate circuit.Analog gate has one
Fixed switching frequency, high shutoff impedance, with extremely low conduction impedance.
As in figure 2 it is shown, FPGA uses the higher type of frequency, uses two kinds of frequencies inputs, a kind of be the work of 50MHz frequently
Rate, another kind is the clock frequency (being provided by OCXO crystal oscillator) of high-precision 10MHz.
The debugging for FPGA of JTAG and code programming.
Flash is the supporting peripheral hardware of FPGA.
12 PXI interfaces are used for debugging and developing additional functionality: when exploitation, by 12 PXI interfaces and 4 oscilloscope channels
It is connected, or is connected with logic analyser, i.e. would know that the ruuning situation within FPGA；Meanwhile, extra port is later to be
System upgrading leaves leeway.
AD/DA uses frequency relatively low, and resolution is AD and DA of 16, and cost is relatively low.
Upper machine communication uses standard 232 interface, matching standard serial port communicating protocol.
Obviously, those skilled in the art can carry out various change and modification without deviating from this practicality to this utility model
Novel spirit and scope.So, if these amendments of the present utility model and modification are belonged to this utility model claim
And within the scope of equivalent technology, then this utility model is also intended to comprise these change and modification.
Claims (10)
1. the digital integrator for superconducting cyclotron magnetic-field measurement, it is characterised in that described digital integrator bag
Contain: frontend amplifying circuit PGA (1), analogue active integration circuit (2), window comparator circuit (3), quick discharging circuit (4),
Balancing circuit (5), AD/DA digital to analog conversion circuit (6), FPGA digital programmable gate circuit (7), 50MHz high speed crystal oscillator with
10MHz High Precision Crystal Oscillator circuit (8), RS232 serial communication circuit (9)；
Signal initially enters the output signal entrance analogue active of frontend amplifying circuit PGA (1), frontend amplifying circuit PGA (1) and amasss
Separated time road (2), the outfan of balancing circuit (5) and quick discharging circuit (4) accesses analogue active integration circuit (2)；Window
Comparator circuit (3) is connected on the outfan of analogue active integration circuit (2), it is judged that whether electric capacity both end voltage value is in restriction
In, the output signal of window comparator circuit (3) enters FPGA digital programmable gate circuit (7)；FPGA digital programmable door electricity
Road (7) controls quick discharging circuit (4)；50MHz high speed crystal oscillator and 10MHz High Precision Crystal Oscillator circuit (8), and RS232 serial ports is logical
News circuit (9) connect FPGA digital programmable gate circuit (7)；AD/DA digital to analog conversion circuit (6) connects FPGA digital programmable door
Circuit (7), and connect analogue active integration circuit (2), the output of AD/DA digital to analog conversion circuit (6) is as balancing circuit (5)
Input.
A kind of digital integrator the most according to claim 1, it is characterised in that described frontend amplifying circuit PGA (1) is wrapped
Contain: use the fixed gain amplifying circuit that instrumentation amplifier is made, as first order amplifying circuit；Use program control amplification able to programme
The variable gain amplifying circuit that device is made, as second level amplifying circuit, can be adjusted by FPGA digital programmable gate circuit (7)
Joint amplification.
A kind of digital integrator the most according to claim 1, it is characterised in that described analogue active integration circuit (2) is wrapped
Containing a high precision operating amplifier and an electric capacity with high bleeder resistance.
A kind of digital integrator the most according to claim 1, it is characterised in that described window comparator circuit (3) includes
The window comparator of two Symmetricals, generating positive and negative voltage threshold value is by precision resister collocation regulation；Two window comparators
Output voltage values by voltage conversion circuit, incoming FPGA digital programmable gate circuit (7).
A kind of digital integrator the most according to claim 1, it is characterised in that described quick discharging circuit (4) just comprises
Negative high accuracy Ref power supply, disconnects impedance, the analog switching circuit of low conduction impedance, by FPGA digital programmable door with high speed, height
The signal of circuit (7) controls, and clock signal source is in 10MHz High Precision Crystal Oscillator circuit；The output of described quick discharging circuit (4)
Signal function is in analogue active integration circuit (2).
A kind of digital integrator the most according to claim 1, it is characterised in that described balancing circuit (5) comprises two-way
Regulative mode, a road is to consist of with potentiometer Ref power supply, as the coarse adjustment of balance；Another road is to be become by AD/DA digital-to-analogue
Thread-changing road (6), as the fine tuning of balance.
A kind of digital integrator the most according to claim 1, it is characterised in that described AD/DA digital to analog conversion circuit (6) is wrapped
Gather the terminal voltage value of analogue active integration circuit (2) electric capacity containing 16, road ADC and 16, road DAC:ADC, result is incoming
FPGA digital programmable gate circuit (7)；DAC is controlled by FPGA digital programmable gate circuit (7), and its output result is as balancing
The voltage input of circuit (5) fine tuning mode.
A kind of digital integrator the most according to claim 1, it is characterised in that described FPGA digital programmable gate circuit
(7) comprising a piece of high speed FPGA, its clock signal derives from 50MHz high speed crystal oscillator, and utilizes its internal frequency multiplication of phase locked loop, makees
For the main control chip of digital integrator, and realize the communication with host computer by RS232 serial communication circuit (9).
9. according to a kind of digital integrator described in claim 1 or 7, it is characterised in that described AD/DA digital to analog conversion circuit
(6) possess closed loop feedback and control function.
A kind of digital integrator the most according to claim 9, it is characterised in that described FPGA digital programmable gate circuit
(7) the internal self-balancing regulation algorithm achieving circuit, and long-time measurement dynamic voltage compensation algorithm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620819475.8U CN205879203U (en) | 2016-07-29 | 2016-07-29 | A digital integrator for superconducting cyclotron magnetic -field measurement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620819475.8U CN205879203U (en) | 2016-07-29 | 2016-07-29 | A digital integrator for superconducting cyclotron magnetic -field measurement |
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| Publication Number | Publication Date |
|---|---|
| CN205879203U true CN205879203U (en) | 2017-01-11 |
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ID=57699597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620819475.8U Withdrawn - After Issue CN205879203U (en) | 2016-07-29 | 2016-07-29 | A digital integrator for superconducting cyclotron magnetic -field measurement |
Country Status (1)
| Country | Link |
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| CN (1) | CN205879203U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106092147A (en) * | 2016-07-29 | 2016-11-09 | 中国原子能科学研究院 | A kind of digital integrator for superconducting cyclotron magnetic-field measurement |
| CN109298356A (en) * | 2018-09-20 | 2019-02-01 | 中国原子能科学研究院 | High-precision magnetic-field measurement induction coil probe in a kind of superconducting cyclotron |
-
2016
- 2016-07-29 CN CN201620819475.8U patent/CN205879203U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106092147A (en) * | 2016-07-29 | 2016-11-09 | 中国原子能科学研究院 | A kind of digital integrator for superconducting cyclotron magnetic-field measurement |
| CN106092147B (en) * | 2016-07-29 | 2018-04-20 | 中国原子能科学研究院 | A kind of digital integrator for superconducting cyclotron magnetic-field measurement |
| CN109298356A (en) * | 2018-09-20 | 2019-02-01 | 中国原子能科学研究院 | High-precision magnetic-field measurement induction coil probe in a kind of superconducting cyclotron |
| CN109298356B (en) * | 2018-09-20 | 2024-05-14 | 中国原子能科学研究院 | High-precision magnetic field measurement induction coil probe in superconducting cyclotron |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20170111 Effective date of abandoning: 20180420 |