CN205754272U

CN205754272U - A kind of digital technology experimental system pulse signal generation module based on CPLD

Info

Publication number: CN205754272U
Application number: CN201620489608.XU
Authority: CN
Inventors: 王用鑫
Original assignee: Chongqing College of Electronic Engineering
Current assignee: Chongqing College of Electronic Engineering
Priority date: 2016-05-16
Filing date: 2016-05-16
Publication date: 2016-11-30
Anticipated expiration: 2026-05-16

Abstract

The utility model discloses a kind of digital technology experimental system pulse signal generation module based on CPLD, including CPLD controller；CPLD controller includes single pulse generation module, two divided-frequency signal generation unit, ten fractional frequency signal generation units and data selector unit；Single pulse generation module is mainly made up of rest-set flip-flop；Two divided-frequency signal generation unit includes the first d type flip flop, the second d type flip flop and 3d flip-flop；Ten fractional frequency signal generation units include N number of decade computer；Wherein N is the natural number more than 3；The signal input of ten fractional frequency signal generation units is connected with the 3rd signal output of two divided-frequency signal generation unit.This utility model has use, and number of devices is few, circuit structure is simple, cheap and beneficially digital technology experimental system overhaul of the equipments advantage.

Description

A kind of digital technology experimental system pulse signal generation module based on CPLD

Technical field

This utility model relates to the key modules of a kind of Experiment of Electronic Technology device, specifically a kind of employing The pulse signal generation module for digital technology experimental system that CPLD technology realizes, belongs to experimental provision With equipment design field.

Background technology

" Fundamental Digital Electronic Technique " is important specialized courses, either an e-mail of electric specialty Breath class specialty, Computer Specialty or Automation Specialty all offer this course, the most self-evident, The most extremely important with the experimental teaching that " Fundamental Digital Electronic Technique " matches.The schools of various levels and categories at present Widely used Digital Electronics Experiment system (i.e. digital technology experimental box) generally volume is relatively big, Its circuit board length and width size is usually 40-60CM；And digital electronic technology experimental box price is the most high Expensive.Due to experimental box volume two major features big, expensive so that cannot be as single-chip microcomputer after students in class Experimental box is equally taken back dormitory and is learnt voluntarily by developed target board, but the study of electronic technology is again needs From the superficial to the deep, continually strengthening practice, the experiment that classroom can complete is typically the confirmatory reality on basis Test, student have no chance deep cognition circuit theory and be extended design.

Cause that digital technology experimental box volume is the most expensive be main reason is that: digital technology experimental box Circuit board on substantial amounts of signal generator module would generally be set, such as single pulse signal generator module, Each frequency range continuous impulse produces signal, binary-coded decimal signal generator module.And in prior art, these signals Generation module all by substantial amounts of, on a small scale digital integrated electronic circuit be that core realizes, such as produce BCD The signal generator module of code typically requires use multi-disc 74161 medium scale integration (MSI) and other small-scale devices Part, will realize the output of pulse signal of each frequency then needs multi-disc d type flip flop chip (to realize repeatedly two Frequency dividing) and multi-disc ten divide device, which results in needed for experimental system integrated circuit quantity relatively greatly, this Directly results in experimental system circuit board size big, and placement-and-routing is complicated, cost is high.Additionally, learn Life is likely to damage related integrated device due to reasons such as maloperations in experimental implementation, but owing to making With in substantial amounts of, on a small scale digital device will also result in overhaul of the equipments difficulty, this is also numeral skill at present Art experimental facilities spoilage is high, one of reason affecting teaching efficiency.

Utility model content

For deficiencies of the prior art, the purpose of this utility model is: how to provide one to make Few by number of devices, circuit structure is simple, cheap and beneficially overhaul of the equipments for numeral skill The pulse signal generation module of art experimental system.

To achieve these goals, this utility model have employed following technical scheme.

A kind of digital technology experimental system pulse signal generation module based on CPLD, it is characterised in that: Including CPLD controller；

Described CPLD controller includes single pulse generation module, two divided-frequency signal generation unit, very Frequently signal generation unit and data selector unit；

Described single pulse generation module is mainly made up of rest-set flip-flop, the set end of described rest-set flip-flop Fix end with the first of single-pole double throw key switch to be connected, the reset terminal of rest-set flip-flop and single-pole double throw The second of key switch is fixed end and is connected, the movable end ground connection of single-pole double throw key switch, and RS triggers The set end of device is all connected with positive source VCC with reset terminal, and the signal output part of rest-set flip-flop is The outfan of single pulse generation module；

Described two divided-frequency signal generation unit includes that the first d type flip flop, the second d type flip flop and the 3rd D touch Sending out device, the reversed-phase output of described first d type flip flop and the data terminal of the first d type flip flop are connected, institute The data terminal of the reversed-phase output and the second d type flip flop of stating the second d type flip flop is connected, described 3rd D The reversed-phase output of trigger and the data terminal of 3d flip-flop are connected；Described first d type flip flop The clock end of outfan and the second d type flip flop is connected, the outfan and the 3rd of described second d type flip flop The clock end of d type flip flop is connected；The outfan of described first d type flip flop is that described two divided-frequency signal produces First signal output of raw unit, the outfan of described second d type flip flop is that described two divided-frequency signal produces The secondary signal delivery outlet of raw unit, the outfan of described 3d flip-flop is that described two divided-frequency signal produces 3rd signal output of raw unit, the clock end of described first d type flip flop is that described two divided-frequency signal produces The signal input of raw unit；

Described ten fractional frequency signal generation units include N number of decade computer；Described decade counter utensil Having counting clock input and carry output, described N number of decade computer is according to signal flow direction order Connect, be arranged in signal and flow to enumerator headed by decade computer foremost, be arranged in signal and flow to The decade computer of least significant end is tail enumerator；The counting clock input of described first enumerator is very Frequently the signal input of signal generation unit；The carry output of described N number of decade computer structure respectively Become N number of signal output of ten fractional frequency signal generation units；Wherein N is the natural number more than 3；

The signal input of described ten fractional frequency signal generation units is believed with the 3rd of two divided-frequency signal generation unit Number delivery outlet is connected；

The signal input of described two divided-frequency signal generation unit and the outfan phase of alternative data selector Connect, an input of described alternative data selector and the delivery outlet phase of first crystal oscillating circuit Connecting, another input of alternative data selector and the delivery outlet of the second crystal oscillating circuit are connected Connecing, the data of alternative data selector select end to be connected with toggle switch.

Further, the frequency of described first crystal oscillating circuit output signal is 4MHZ, described second The frequency of crystal oscillating circuit output signal is 8MHZ.

Compared to existing technology, this utility model has the advantage that

Multi-disc medium scale integration (MSI) and other small scale integrations is used just by prior art needs The pulse signal generation module that can realize is completely integrated in CPLD controller, due in CPLD chip Powerful abundant Digital Logic resource is contained in portion, therefore has only to piece of CPLD chip and just can realize one The pulse signal generating function of road or multichannel, this utility model will make digital and electronic compared to existing technology The size of technology experiment device is substantially reduced, and relatively low by CPLD chip price, the most also can The cost enough making Digital Electronics Experiment device is reduced.Additionally, compared to existing technology owing to making Reducing by number of devices, the placement-and-routing of experimental provision integrated circuit also can simplify, and this is conducive to testing dress The maintenance put so that experimental facilities can be effectively utilized.

Accompanying drawing explanation

Fig. 1 is structure chart of the present utility model；

Fig. 2 is the two divided-frequency signal generation unit circuit structure diagram in this utility model；

Fig. 3 is ten fractional frequency signal generation unit circuit structure diagrams in this utility model；

Detailed description of the invention

With detailed description of the invention, this utility model is described in further detail below in conjunction with the accompanying drawings.

As it is shown in figure 1, a kind of digital technology experimental system pulse signal based on CPLD of this utility model Generation module is the important component part of Digital Electronics Experiment Circuits System.

Digital technology experimental system pulse signal generation module typically requires the following three types of pulse of generation Each continuous two divided-frequency signal of signal (1) crystal oscillator output signal, such as crystal oscillator output Signal frequency is 8MHZ, then pulse signal generation module need produce 4MHZ, 2MHZ, 1MHZ, The signals such as 500KHZ, 250KHZ；(2) 100KHZ, 10KHZ are produced until signals such as 1HZ.(3) Produce single pulse signal.

One, for realizing above-mentioned functions, this utility model uses following circuit structure.

Core devices of the present utility model is: CPLD controller, the most also includes outside CPLD controller Enclose clock circuit and power circuit.

(1) single pulse generation module it is provided with in CPLD controller；(2) two divided-frequency signal produces Unit；(3) ten fractional frequency signal generation units.Three big formant and data selector unit；

(1) single pulse generation module

Single pulse generation module is mainly made up of rest-set flip-flop, the set end of rest-set flip-flop be arranged on The first of the single-pole double throw key switch of CPLD chip exterior is fixed end and is connected, the reset of rest-set flip-flop End is fixed end with the second of single-pole double throw key switch and is connected, the movable termination of single-pole double throw key switch Ground, the set end of rest-set flip-flop is all connected with positive source VCC with reset terminal and (certainly can lead to respectively Cross the resistance being arranged on outside CPLD to be connected with positive source VCC), the letter of rest-set flip-flop Number outfan is the outfan of single pulse generation module.

(2) two divided-frequency signal generation unit

As in figure 2 it is shown, two divided-frequency signal generation unit include the first d type flip flop, the second d type flip flop and 3d flip-flop.The reversed-phase output of each d type flip flop is connected with its data terminal, it is clear that this is with regard to structure Having become a frequency-halving circuit, three frequency-halving circuits flow to be sequentially connected according to signal, form three grade two Frequency dividing circuit, the signal input that clock end is two divided-frequency signal generation unit of the first d type flip flop, from The signal that the signal input of this two divided-frequency signal generation unit enters will be carried out three two divided-frequencies and be processed, The signal frequency such as entered from the signal input of this two divided-frequency signal generation unit is 8MHZ, then From from three signal outputs of this two divided-frequency signal generation unit will be sequentially generated 4MHZ, 2MHZ and 1MHZ signal, can also call more d type flip flop the most as required and realize the frequency dividing of more stages.

Each port name is enumerated as follows: the outfan of the first d type flip flop is two divided-frequency signal generation unit First signal output, the outfan of the second d type flip flop is the second of described two divided-frequency signal generation unit Signal output, the outfan of 3d flip-flop is the 3rd signal of described two divided-frequency signal generation unit Delivery outlet, the clock end of the first d type flip flop is the signal input of described two divided-frequency signal generation unit.

(3) ten fractional frequency signal generation units

Ten fractional frequency signal generation units include N number of decade computer as shown in Figure 3；Decade computer Having digital clock input and carry output, N number of decade computer flows to be linked in sequence according to signal, It is arranged in signal and flows to enumerator headed by decade computer foremost, be arranged in signal and flow to least significant end Decade computer be tail enumerator；The counting clock input of first enumerator is that ten fractional frequency signals produce The signal input of unit；The carry output of N number of decade computer respectively constitutes ten fractional frequency signals and produces N number of signal output of raw unit；Wherein N is the natural number more than 3.Obvious each decade counter Device all constitutes ten frequency dividing circuits, and N number of decade computer constitutes 10 grade of ten frequency dividing.

Certainly additive method can also be used here to realize ten frequency dividing circuits, such as, use hardware description language Modeling realizes ten frequency division modules (and dutycycle could be arranged to 1: 1), is then created as one Individual schematic symbol calls for top design design document.But whether use designed by which kind of mode Circuit all can be integrated into instrument and be converted to the circuit meshwork list file of reality.

The signal input of ten fractional frequency signal generation units is defeated with the 3rd signal of two divided-frequency signal generation unit Outlet is connected；Therefore 1MHZ signal will be made n times ten frequency dividing, obtain 100KHZ, 10KHZ successively, 1KHZ, 100HZ are until 1HZ.

It is pointed out that decade computer module in this utility model, data selector module, D Trigger and rest-set flip-flop all can call existing module by principle diagram design mode and realize, concrete, QUARTUS 2 IDE just can call by the way of principle diagram design various substantially Digital module, such as can search to call in period storehouse and be numbered the module of 74192 and just can realize Decade computer module, but this module and medium scale integration (MSI) 74192 chip have again essential difference, (ten enter 74192 modules called by principle diagram design mode in QUARTUS 2 IDE Counter module processed) it is a module with the medium scale integration (MSI) 74192 all functional characteristics of chip, Being substantially to use CPLD internal " with or " array to realize, QUARTUS 2 can be based on " with or " Decade computer module is converted to an actual circuit realiration by array principle, between certain each module Circuit connecting relation also can be converted into concrete circuit and connect.The exploitation belonging to CPLD discussed above Know-why, the most too much illustrates.

Two, operation principle of the present utility model is as follows:

(1) single pulse generation module operation principle

Single-pole double throw key switch is a kind of single-pole double-throw switch (SPDT) with flexible keypad work characteristics, does not has Movable end and the second fixing end stable contact when being pressed, after being pressed, movable end and the first fixing end are stable Contact, unclamps rear movable end and is returned to again contact stable with the second fixing end.Therefore when single-pole double throw button The level that when switch is not pressed, the set end of rest-set flip-flop module obtains is high level, rest-set flip-flop The level that the reset terminal of module obtains is that (the set end of rest-set flip-flop module and reset terminal are all with low for low level Level is useful signal), now, the signal output part output low level of rest-set flip-flop module, work as hilted broadsword After double-throw key switch is pressed, it is clear that rest-set flip-flop module signal output part output high level, and And it is returned to again contact stable with the second fixing end, the signal of rest-set flip-flop module along with unclamping rear movable end The high level of outfan output disappears, and therefore, to sum up, single-pole double throw toggle switch is pushed once, RS The signal output part of igniter module sends out a single pulse.

(2) two divided-frequency signal generation unit operation principle

The reversed-phase output of each d type flip flop is connected with its data terminal, when the clock of d type flip flop brings out During existing rising edge, its data terminal collection signal, and the reversed-phase output signal that this signal is d type flip flop, Therefore the next state of d type flip flop is necessarily the inverted signal of Last status, and this change is to occur At each rising edge of clock, that is to say that a cycle negates once, it is achieved that frequency-halving circuit.

Three frequency-halving circuits flow to be sequentially connected according to signal, form three grades of frequency-halving circuits, a D The signal input that clock end is two divided-frequency signal generation unit of trigger, produces from this two divided-frequency signal The signal that the signal input of unit enters will be carried out three two divided-frequencies and be processed, and concrete example is tied at circuit Structure description part has been described above, and is not repeated herein.

Additionally, the signal input of two divided-frequency signal generation unit and the outfan of alternative data selector Being connected, an input of alternative data selector is connected with the delivery outlet of first crystal oscillating circuit Connecing, another input of alternative data selector and the delivery outlet of the second crystal oscillating circuit are connected, The data of alternative data selector select end to be connected with toggle switch.Based on this circuit connecting relation originally The original clock signal frequency of input can be selected (by the high electricity of toggle switch input by utility model Flat or low level realizes selecting output signal or second crystal oscillating circuit of first crystal oscillating circuit Output signal), in order to the more flexible clock pulses producing multi-frequency.

In this utility model, the frequency configuration of first crystal oscillating circuit output signal is 4MHZ, and second is brilliant The frequency configuration of oscillation body circuit output signal is 8MHZ.

(3) ten fractional frequency signal generation unit operation principles

Decade computer has counting clock input and carry output, former according to decade computer Reason, each decade computer constitutes ten frequency dividing circuits, and counting clock input is that signal is defeated Entering end, carry output is signal output part, and N number of decade computer flows to be linked in sequence according to signal (that is to say that the outfan of the 1st decade computer and the input of the 2nd decade computer are connected Connecing, the input of the outfan of the 2nd decade computer and the 3rd decade computer is connected, Until all decade computers have connected), it is clear that N number of decade computer constitutes 10 grades very Frequently.The signal input of ten fractional frequency signal generation units is defeated with the 3rd signal of two divided-frequency signal generation unit Outlet is connected；Therefore 1MHZ signal will be made n times ten frequency dividing, obtain 100KHZ, 10KHZ successively, 1KHZ, 100HZ are until 1HZ.

Three, occupation mode of the present utility model

Functional module as digital technology experimental system is used, it is contemplated that the number that CPLD chip is powerful Word logic realization ability, can also arrange other function mould in the CPLD controller in this utility model Block, such as binary-coded decimal signal generating module, nixie decoder module etc., most former numeral skills The functional module using middle and small scale digital integrated electronic circuit to realize on art pilot system circuit board all can be integrated In CPLD controller of the present utility model.This utility model is except may apply to digital technology experiment System can also be applied to the pilot system of other hardware designs courses such as such as single-chip microcomputer experiment system In.

Certainly it may be noted that, this utility model also has a data download module, and CPLD controls Device can be connected with computer by data download module, in order to circuit data is downloaded to by computer CPLD make CPLD realize circuit structure described in the utility model.Simultaneously according to programmable logic device Part principle, when digital technology experimental facilities needs upgrading or updates, just may be used by data download module Realize CPLD internal circuit to update and upgrading, can easily realize CPLD the most as required built-in multiple Pulse signal generation module disclosed in this utility model, this is also an important feature of the present utility model.

Finally illustrate, above example only in order to the technical solution of the utility model to be described and unrestricted, Although this utility model being described in detail with reference to preferred embodiment, those of ordinary skill in the art Should be appreciated that and the technical solution of the utility model can be modified or equivalent, without deviating from The objective of technical solutions of the utility model and scope, it all should be contained at claim model of the present utility model In the middle of enclosing.

Claims

1. a digital technology experimental system pulse signal generation module based on CPLD, it is characterised in that: Including CPLD controller；

A kind of digital technology experimental system pulse based on CPLD the most according to claim 1 is believed Number generation module, it is characterised in that the frequency of described first crystal oscillating circuit output signal is 4MHZ, The frequency of described second crystal oscillating circuit output signal is 8MHZ.