CN205750772U - Electronic equipment - Google Patents
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- CN205750772U CN205750772U CN201620479199.5U CN201620479199U CN205750772U CN 205750772 U CN205750772 U CN 205750772U CN 201620479199 U CN201620479199 U CN 201620479199U CN 205750772 U CN205750772 U CN 205750772U
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Abstract
This utility model is about a kind of electronic equipment, relates to electronics field, and main purpose is to reduce design space and the cost of electronic equipment.The technical scheme used is: electronic equipment includes that chipset and first connects interface.Chipset has bus signals outfan, and bus signals outfan is multiplexed with SATA signal output part or PCIE signal outfan；First connection interface is input/output interface, and first connects the electrical connection of Interface & Bus signal output part, and the first connection interface duplex is SATA interface or PCIE interface；When the first connection interface duplex is SATA interface, bus signals outfan is multiplexed with SATA signal output part, and chipset connects interface by bus signals outfan to first and sends SATA signal；When the first connection interface duplex is PCIE interface, bus signals outfan is multiplexed with PCIE signal outfan, and chipset connects interface by bus signals outfan to first and sends PCIE signal.This utility model electronic equipment can be notebook computer, desktop computer or server etc..
Description
Technical field
This utility model relates to technical field of electronic products, particularly relates to a kind of electronic equipment.
Background technology
At present, the mainboard of computer having many spare interface, these spare interface include SATA (Serial
The abbreviation of Advanced Technology Attachment, Chinese name: Serial Advanced Technology Attachment) interface and PCIE
(abbreviation of Peripheral Component Interconnect Express, Chinese name: Peripheral Component Interconnect standard extension,
It is up-to-date bus and interface standard, and original name is " 3GIO ") interface.SATA interface and PCIE interface are the most frequently used interface class
Type.Computer can connect SATA device by SATA interface, connects PCIE device by PCIE interface.
During stating technical scheme in realization, inventor finds that in prior art, at least there are the following problems: computer
On mainboard, the design of this number of different types interface directly increases design space and the cost of computer.How to reduce computer
Design space and cost become the emphasis of those skilled in the art's research.
Utility model content
In view of this, this utility model provides a kind of electronic equipment, and main purpose is that the design reducing electronic equipment is empty
Between and cost.
For reaching above-mentioned purpose, this utility model mainly provides following technical scheme:
Embodiment of the present utility model provides a kind of electronic equipment, including:
Chipset, it has bus signals outfan, described bus signals outfan be multiplexed with SATA signal output part or
PCIE signal outfan；
First connect interface, described first connect interface be input/output interface, described first connect interface with described always
Line signal output part electrically connects, and described first connection interface duplex is SATA interface or PCIE interface；
Wherein, when described first connection interface duplex is SATA interface, described bus signals outfan is multiplexed with SATA
Signal output part, described chipset connects interface by described bus signals outfan to described first and sends SATA signal；
When described first connection interface duplex is PCIE interface, it is defeated that described bus signals outfan is multiplexed with PCIE signal
Going out end, described chipset connects interface by described bus signals outfan to described first and sends PCIE signal.
The purpose of this utility model and solve its technical problem and also can be applied to the following technical measures to achieve further.
Aforesaid electronic equipment, wherein, described chipset is provided with signal input part in place and the input of equipment identification signal
End；
Described signal input part in place and described equipment identification signal input part are connected interface with described first respectively and are electrically connected
Connect；
Described chipset is received from first by described signal input part in place and described equipment identification signal input part
Connect signal in place and the equipment identification signal of interface, and according to the first rule set, by described bus signals outfan
Interface output SATA signal or PCIE signal is connected to described first.
Aforesaid electronic equipment, wherein, described first rule meets:
When described signal in place and described equipment identification signal are low level signal, described bus signals outfan is multiple
With for SATA signal output part, described chipset connects interface output SATA by described bus signals outfan to described first
Signal；
When described signal in place is low level signal, when described equipment identification signal is high level signal, described bus is believed
Number outfan is multiplexed with PCIE signal outfan, and described chipset is connect to described first by described bus signals outfan
Mouth output PCIE signal.
Aforesaid electronic equipment, wherein, described first rule meets:
When described signal in place and described equipment identification signal are low level signal, described bus signals outfan is multiple
With for PCIE signal outfan, described chipset connects interface output PCIE by described bus signals outfan to described first
Signal；
When described signal in place is low level signal, when described equipment identification signal is high level signal, described bus is believed
Number outfan is multiplexed with SATA signal output part, and described chipset is connect to described first by described bus signals outfan
Mouth output SATA signal.
Aforesaid electronic equipment, also includes:
SATA device adnexa, it has SATA interface and second and connects interface, and described second connects interface has letter in place
Number lead-out terminal, equipment identification signal output terminal and bus signals input terminal；
Wherein, described SATA device adnexa is electrically connected with outside SATA device by described SATA interface；Described second even
The signal output terminal in place of connection interface, equipment identification signal output terminal and bus signals input terminal are respectively by described the
One signal input part in place connecting interface and described chipset, identify signal input part and bus signals outfan one a pair
Should electrically connect；
Described SATA device accessory configuration is to connect interface by second to export signal in place and equipment identification signal, and uses
In connecting the adnexa of transmission SATA signal between interface and outside SATA device first.
Aforesaid electronic equipment, wherein, described first connection interface is insertion slot type interface, and described second connection interface is slotting
Hair style interface；
Or, described first connection interface is plug-type interface, and described second connection interface is insertion slot type interface.
Aforesaid electronic equipment, also includes:
PCIE device adnexa, it has PCIE interface and the 3rd and connects interface, and the described 3rd connects interface has letter in place
Number lead-out terminal, equipment identification signal output terminal and bus signals input terminal；
Wherein, described PCIE device adnexa is electrically connected with outside PCIE device by described PCIE interface；Described 3rd even
The signal output terminal in place of connection interface, equipment identification signal output terminal and bus signals input terminal are respectively by described the
One signal input part in place connecting interface and described chipset, identify signal input part and bus signals outfan one a pair
Should electrically connect；
Described PCIE device accessory configuration is to connect interface by the 3rd to export signal in place and equipment identification signal, and uses
In the adnexa transmitting PCIE signal between the first connection interface and outside PCIE device.
Aforesaid electronic equipment, wherein, described first connection interface is insertion slot type interface, and described 3rd connection interface is slotting
Hair style interface；
Or, described first connection interface is plug-type interface, and described 3rd connection interface is insertion slot type interface.
Aforesaid electronic equipment is notebook computer, desktop computer or server.
By technique scheme, this utility model electronic equipment at least has the advantages that
In the technical scheme that this utility model provides, because first connects interface duplex and is SATA interface or PCIE connects
Mouthful, when first connects interface duplex to be SATA interface be connected with outside SATA device, chipset is by bus signals outfan
Connect interface to first and send SATA signal, thus realize the signal transmission between chipset and outside SATA device；When first
When connecting interface duplex to be PCIE interface is connected with outside PCIE device, chipset passes through bus signals outfan to the first connection
Interface sends PCIE signal, thus realizes the signal transmission between chipset and outside PCIE device.Wherein, same connecing is used
Mouth is multiplexed with SATA interface or PCIE interface, relative to prior art needs individually designed two different types of interfaces, this
The technical scheme that utility model provides can effectively reduce design space and the cost of electronic equipment.
Described above is only the general introduction of technical solutions of the utility model, in order to better understand skill of the present utility model
Art means, and can being practiced according to the content of description, below with preferred embodiment of the present utility model and coordinate accompanying drawing detailed
Describe in detail bright as after.
Accompanying drawing explanation
Fig. 1 is that the first connection interface of a kind of electronic equipment that an embodiment of the present utility model provides is connected with chipset
Structured flowchart；
Fig. 2 is that the another kind of electronic equipment that an embodiment of the present utility model provides is set with SATA by SATA device adnexa
The standby structured flowchart connected；
Fig. 3 is that the another kind of electronic equipment that an embodiment of the present utility model provides is set with PCIE by PCIE device adnexa
The standby structured flowchart connected.
Detailed description of the invention
By further illustrating the technological means and effect that this utility model taked by reaching predetermined utility model purpose,
Below in conjunction with accompanying drawing and preferred embodiment, to according to the detailed description of the invention of this utility model application, structure, feature and merit thereof
Effect, after describing in detail such as.In the following description, what different " embodiments " or " embodiment " referred to is not necessarily same enforcement
Example.Additionally, special characteristic, structure or feature in one or more embodiment can be combined by any suitable form.
As it is shown in figure 1, a kind of electronic equipment that an embodiment of the present utility model proposes, including chipset 1 and first
Connect interface 2.
As it is shown in figure 1, chipset 1 has bus signals outfan 11.This bus signals outfan 11 is multiplexed with SATA letter
Number outfan or PCIE signal outfan, in other words: this bus signals outfan 11 both can be used to export SATA signal, also
Can be used to export PCIE signal.
As it is shown in figure 1, the first connection interface 2 is input/output interface.First connects interface 2 has bus signals outfan
Son 21.The first bus signals lead-out terminal 21 connecting interface 2 electrically connects with the bus signals outfan 11 of chipset 1.First
Connect interface 2 and be multiplexed with SATA interface or PCIE interface, in other words: this first connection interface 2 both can be used to transmit SATA
Signal, it is also possible to be used for transmitting PCIE signal.
Wherein, when first connect interface 2 be multiplexed with SATA interface time, this utility model electronic equipment can by this first
Connecting interface 2 to be connected with outside SATA device 10, now bus signals outfan 11 is multiplexed with SATA signal output part, chipset
1 connects interface 2 by bus signals outfan 11 to first sends SATA signal, and by the first connection interface 2 by this SATA
Signal is transferred to outside SATA device 10, thus realizes the signal transmission between chipset 1 and outside SATA device 10.
When above-mentioned first connection interface 2 is multiplexed with PCIE interface, this utility model electronic equipment can by this
One connects interface 2 is connected with outside PCIE device 20, and now bus signals outfan 11 is multiplexed with PCIE signal outfan, chip
Group 1 connects interface 2 by bus signals outfan 11 to first and sends PCIE signal, and should by the first connection interface 2
PCIE signal is transferred to outside PCIE device 20, thus realizes the signal transmission between chipset 1 and outside PCIE device 20.
In the technical scheme of above-mentioned offer, because the first connection interface 2 both can be multiplexed with SATA interface, it is also possible to multiple
With for PCIE interface, thus this same interface both can serve as SATA interface and be connected with outside SATA device 10, can fill again
When PCIE interface is connected with outside PCIE device 20, different types of connect relative to prior art needs individually designed two
Mouthful, the technical scheme that this utility model provides can effectively reduce design space and the cost of electronic equipment.
Needing exist for explanation: in a concrete application example, aforesaid chipset 1 and first connects interface 2
It is arranged on the mainboard of electronic equipment.
The chipset 1 of above-mentioned electronic equipment should have automatic identification function, with identify the first connection interface 2 connection is
SATA device 10 or PCIE device 20, and the type connecting the connected peripheral hardware of interface 2 according to first, exported by bus signals
The end 11 corresponding bus signals of output.In order to realize this function, the embodiment that electronic equipment of the present utility model offer is following:
As it is shown in figure 1, aforesaid chipset 1 is provided with signal input part 12 in place and equipment identification signal input part 13.Aforesaid
There is on one connection interface 2 corresponding signal input terminal 22 in place and equipment identification signal input terminal 23.On chipset 1
The signal input terminal in place 22 that signal input part 12 in place is connected interface 2 with first electrically connects.Equipment identification on chipset 1
Signal input part 13 is connected the equipment identification signal input terminal 23 of interface 2 and electrically connects with first.Wherein, chipset 1 passes through
Position signal input part 12 and equipment identification signal input part 13 receive from the first signal in place connecting interface 2 and equipment identification
Signal, and according to the first rule set, by bus signals outfan 11 to the first bus signals outfan connecting interface 2
Son 21 output SATA signal or PCIE signal.
During the technical scheme specifically stated on the implementation, aforesaid SATA device 10 or the adnexa being connected with SATA device 10 should
Signal in place and equipment identification signal can be exported, when SATA device 10 or the adnexa and first that is connected with SATA device 10 connect
When mouth 2 connects, can be by the signal input terminal in place 22 of the first connection interface 2 to the signal input part in place of chipset 1
12 input signal in place, it is possible to connect the equipment identification signal input terminal 23 of interface 2 to the equipment of chipset 1 by first
Identify signal input part 13 input equipment identification signal.Wherein, chipset 1 is believed by signal input part 12 in place and equipment identification
After number input 13 receives signal in place and the equipment identification signal of SATA device 10 input, according to the first rule set,
SATA signal is exported to the first bus signals lead-out terminal 21 connecting interface 2 by bus signals outfan 11.
Same, aforesaid PCIE device 20 or the adnexa being connected with PCIE device 20 also should be able to export signal in place and set
Standby identify signal, when PCIE device 20 or the adnexa that is connected with PCIE device 20 and the first connection interface 2 connect, can pass through
First signal input terminal in place 22 connecting interface 2 inputs signal in place to the signal input part in place 12 of chipset 1, and can
Defeated to the equipment identification signal input part 13 of chipset 1 to connect the equipment identification signal input terminal 23 of interface 2 by first
Enter equipment identification signal.Wherein, chipset 1 is received by signal input part 12 in place and equipment identification signal input part 13
After the signal in place of PCIE device 20 input and equipment identification signal, according to the first rule set, exported by bus signals
End 11 exports PCIE signal to the first bus signals lead-out terminal 21 connecting interface 2.
In a concrete application example, aforesaid first rule should meet: when signal in place and equipment identification signal
When being low level signal, bus signals outfan 11 is multiplexed with SATA signal output part, and chipset 1 is exported by bus signals
End 11 exports SATA signal to the first bus signals lead-out terminal 21 connecting interface 2.When signal in place is low level signal, if
When standby identification signal is high level signal, bus signals outfan 11 is multiplexed with PCIE signal outfan, and chipset 1 passes through bus
Signal output part 11 exports PCIE signal to the first bus signals lead-out terminal 21 connecting interface 2.
Need exist for explanation: when using the in above-mentioned example first rule, SATA device 10 or and SATA device
10 adnexaes connected should be able to output low level signal in place and low level equipment identification signal.PCIE device 20 or and PCIE device
20 adnexaes connected should be able to output low level signal in place and level equipment identification signal.
Certainly, in an alternative embodiment, aforesaid first rule can also replace by other rule.?
In this alternative embodiment, aforesaid first rule meets: when signal in place and equipment identification signal are low level signal,
Bus signals outfan 11 is multiplexed with PCIE signal outfan, and chipset 1 is connect to first by bus signals outfan 11
The bus signals lead-out terminal 21 of mouth 2 exports PCIE signal.When signal in place is low level signal, equipment identification signal is high electricity
During ordinary mail, bus signals outfan 11 is multiplexed with SATA signal output part, chipset 1 by bus signals outfan 11 to the
The one bus signals lead-out terminal 21 connecting interface 2 exports SATA signal.
Need exist for explanation: when using the in above-mentioned alternative exemplary first rule, accordingly, SATA device 10 or
The adnexa being connected with SATA device 10 should be able to output low level signal in place and level equipment identification signal.PCIE device 20 or
The adnexa being connected with PCIE device 20 should be able to output low level signal in place and low level equipment identification signal.
In order to reduce as far as possible, outside SATA device 10 is modified, as in figure 2 it is shown, outside SATA device 10 is the most logical
Cross SATA device adnexa 3 to be connected interface 2 with first and connect.This SATA device adnexa 3 has SATA interface 32 and second and connects
Mouth 31.Second connects interface 31 has signal output terminal 312 in place, equipment identification signal output terminal 313 and bus signals
Input terminal 311.SATA device adnexa 3 is electrically connected with outside SATA device 10 by SATA interface 32.SATA device adnexa 3 leads to
Cross the second connection interface 31 to be connected interface 2 with first and electrically connect.And second connect the signal output terminal in place 312 of interface 31 with
First signal input terminal in place 22 connecting interface 2 electrically connects, so that second connects the signal output terminal in place of interface 31
312 are electrically connected with the signal input part in place 12 of chipset 1 by the first connection interface 2.Second equipment connecting interface 31 is known
Level signal lead-out terminal 313 is connected the equipment identification signal input terminal 23 of interface 2 and electrically connects, so that second connects with first
The equipment identification signal output terminal 313 of mouth 31 is by the equipment identification signal input part 13 of the first connection interface 2 with chipset 1
Electrical connection.The second bus signals input terminal 311 connecting interface 31 is connected the bus signals lead-out terminal 21 of interface 2 with first
Electrical connection, so that second connects total by the first connection interface 2 and chipset 1 of the bus signals input terminal 311 of interface 31
Line signal output part 11 electrically connects.Wherein, the SATA device adnexa 3 in the present embodiment is configured to connect interface 31 by second
Export signal in place and equipment identification signal, and transmit SATA for connecting first between interface 2 and outside SATA device 10
The adnexa of signal.The technology implementing this SATA device adnexa 3 function is common technology of the prior art, can be according to need
To choose in the prior art, not repeat them here.
Same, in order to reduce as far as possible, outside PCIE device 20 is modified, as it is shown on figure 3, outside PCIE device 20
It is connected interface 2 preferably through PCIE device adnexa 4 with first to connect.This PCIE device adnexa 4 has PCIE interface 42 and
Three connect interface 41.3rd connects interface 41 has signal output terminal 412 in place, equipment identification signal output terminal 413 and
Bus signals input terminal 411.PCIE device adnexa 4 is electrically connected with outside PCIE device 20 by PCIE interface 42.PCIE sets
Standby adnexa 4 is connected interface 2 by the 3rd connection interface 41 with first and electrically connects.And the 3rd connect interface 41 signal in place output
Terminal 412 is connected the signal input terminal in place 22 of interface 2 and electrically connects with first, so that the 3rd connects the signal in place of interface 41
Lead-out terminal 412 is electrically connected with the signal input part in place 12 of chipset 1 by the first connection interface 2.3rd connects interface 41
Equipment identification signal output terminal 413 be connected the equipment identification signal input terminal 23 of interface 2 with first and electrically connect, so that
The three equipment identification signal output terminal 413 equipment identification signals by the first connection interface 2 with chipset 1 connecting interface 41
Input 13 electrically connects.The bus signals that the 3rd bus signals input terminal 411 connecting interface 41 is connected interface 2 with first is defeated
Go out terminal 21 to electrically connect, so that the 3rd connects the bus signals input terminal 411 of interface 41 by the first connection interface 2 and chip
The bus signals outfan 11 of group 1 electrically connects.Wherein, the PCIE device adnexa 4 in the present embodiment is configured to by the 3rd even
Connection interface 41 exports signal in place and equipment identification signal, and for connecting between interface 2 and outside PCIE device 20 first
The adnexa of transmission PCIE signal.The technology implementing this PCIE device adnexa 4 function is common technology of the prior art, can
To choose the most in the prior art, do not repeat them here.
In a concrete application example, aforesaid first connection interface 2 is insertion slot type interface, and accordingly, second even
Connection interface 31 and the 3rd connection interface 41 are plug-type interface.
But, in an example substituted, it is also possible to be aforesaid first to connect interface 2 for plug-type interface, second
Connect interface 31 and the 3rd connection interface 41 is insertion slot type interface.
The electronic equipment that this utility model embodiment provides can be notebook computer, desktop computer or server, ability
Territory it will be appreciated by the skilled person that notebook computer, desktop computer or server are merely illustrative, be not used to the present embodiment
Technical scheme limits, and other kinds of electronic equipment is also all suitable for.
The above, be only preferred embodiment of the present utility model, not this utility model is made any in form
Restriction, any simple modification, equivalent variations and modification above example made according to technical spirit of the present utility model,
All still fall within the range of technical solutions of the utility model.
Claims (9)
1. an electronic equipment, it is characterised in that including:
Chipset, it has bus signals outfan, and described bus signals outfan is multiplexed with SATA signal output part or PCIE
Signal output part；
First connects interface, and described first connection interface is input/output interface, and described first connects interface believes with described bus
The electrical connection of number outfan, described first to connect interface duplex be SATA interface or PCIE interface；
Wherein, when described first connection interface duplex is SATA interface, described bus signals outfan is multiplexed with SATA signal
Outfan, described chipset connects interface by described bus signals outfan to described first and sends SATA signal；
When described first connection interface duplex is PCIE interface, described bus signals outfan is multiplexed with PCIE signal output
End, described chipset connects interface by described bus signals outfan to described first and sends PCIE signal.
2. electronic equipment as claimed in claim 1, it is characterised in that
Described chipset is provided with signal input part in place and equipment identification signal input part；
Described signal input part in place and described equipment identification signal input part are connected interface electrical connection respectively with described first；
Described chipset is received by described signal input part in place and described equipment identification signal input part and connects from first
The signal in place of interface and equipment identification signal, and according to the first rule set, by described bus signals outfan to institute
State the first connection interface output SATA signal or PCIE signal.
3. electronic equipment as claimed in claim 2, it is characterised in that
Described first rule meets:
When described signal in place and described equipment identification signal are low level signal, described bus signals outfan is multiplexed with
SATA signal output part, described chipset connects interface output SATA by described bus signals outfan to described first to be believed
Number；
When described signal in place is low level signal, when described equipment identification signal is high level signal, described bus signals is defeated
Going out end and be multiplexed with PCIE signal outfan, it is defeated that described chipset connects interface by described bus signals outfan to described first
Go out PCIE signal.
4. electronic equipment as claimed in claim 2, it is characterised in that
Described first rule meets:
When described signal in place and described equipment identification signal are low level signal, described bus signals outfan is multiplexed with
PCIE signal outfan, described chipset connects interface output PCIE by described bus signals outfan to described first to be believed
Number；
When described signal in place is low level signal, when described equipment identification signal is high level signal, described bus signals is defeated
Going out end and be multiplexed with SATA signal output part, it is defeated that described chipset connects interface by described bus signals outfan to described first
Go out SATA signal.
5. electronic equipment as claimed in claim 2, it is characterised in that also include:
SATA device adnexa, it has SATA interface and second and connects interface, and described second connects interface, and to have signal in place defeated
Go out terminal, equipment identification signal output terminal and bus signals input terminal；
Wherein, described SATA device adnexa is electrically connected with outside SATA device by described SATA interface；Described second connects
Signal output terminal in place, equipment identification signal output terminal and the bus signals input terminal of mouth is respectively by described first even
Connection interface is electric with the signal input part in place of described chipset, identification signal input part and bus signals outfan one_to_one corresponding
Connect；
Described SATA device accessory configuration is to connect interface by second to export signal in place and equipment identification signal, and is used for
First connects the adnexa transmitting SATA signal between interface and outside SATA device.
6. electronic equipment as claimed in claim 5, it is characterised in that
Described first connection interface is insertion slot type interface, and described second connection interface is plug-type interface；
Or, described first connection interface is plug-type interface, and described second connection interface is insertion slot type interface.
7. electronic equipment as claimed in claim 2, it is characterised in that also include:
PCIE device adnexa, it has PCIE interface and the 3rd and connects interface, and the described 3rd connects interface, and to have signal in place defeated
Go out terminal, equipment identification signal output terminal and bus signals input terminal；
Wherein, described PCIE device adnexa is electrically connected with outside PCIE device by described PCIE interface；Described 3rd connects
Signal output terminal in place, equipment identification signal output terminal and the bus signals input terminal of mouth is respectively by described first even
Connection interface is electric with the signal input part in place of described chipset, identification signal input part and bus signals outfan one_to_one corresponding
Connect；
Described PCIE device accessory configuration is to connect interface by the 3rd to export signal in place and equipment identification signal, and is used for
First connects the adnexa transmitting PCIE signal between interface and outside PCIE device.
8. electronic equipment as claimed in claim 7, it is characterised in that
Described first connection interface is insertion slot type interface, and described 3rd connection interface is plug-type interface；
Or, described first connection interface is plug-type interface, and described 3rd connection interface is insertion slot type interface.
9. the electronic equipment as according to any one of claim 1 to 8, it is characterised in that
Described electronic equipment is notebook computer, desktop computer or server.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620479199.5U CN205750772U (en) | 2016-05-24 | 2016-05-24 | Electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620479199.5U CN205750772U (en) | 2016-05-24 | 2016-05-24 | Electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205750772U true CN205750772U (en) | 2016-11-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620479199.5U Active CN205750772U (en) | 2016-05-24 | 2016-05-24 | Electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253891A (en) * | 2021-12-15 | 2022-03-29 | 北京云迹科技股份有限公司 | Configuration method, device, equipment and storage medium |
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2016
- 2016-05-24 CN CN201620479199.5U patent/CN205750772U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253891A (en) * | 2021-12-15 | 2022-03-29 | 北京云迹科技股份有限公司 | Configuration method, device, equipment and storage medium |
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