CN205722746U - LCD TV intelligent eyes protecting system based on FPGA - Google Patents
LCD TV intelligent eyes protecting system based on FPGA Download PDFInfo
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- CN205722746U CN205722746U CN201620310684.XU CN201620310684U CN205722746U CN 205722746 U CN205722746 U CN 205722746U CN 201620310684 U CN201620310684 U CN 201620310684U CN 205722746 U CN205722746 U CN 205722746U
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Abstract
Based on the LCD TV intelligent eyes protecting system of FPGA, belong to Smart Home field.The problems such as the non adaptive of solution available liquid crystal display device brightness regulation, low autgmentability, low operating efficiency.Composition of the present utility model includes that FPGA control circuit connects clock circuit, ambient light detection circuit, LED luminance regulation circuit respectively；Fpga chip is internally integrated I2C decoding circuit, CLK clock circuit, SRAM control circuit, light Comparison Circuit and pwm circuit, SRAM control circuit connects SRAM storage chip；Wherein I2C decoding circuit, CLK clock circuit, SRAM control circuit, light Comparison Circuit and pwm circuit are connected to FPGA internal bus；Power circuit provides operating voltage for other circuit；The utility model has the advantage of Automatic adjusument, can reduce the vision impairment to user for the screen light to greatest extent, reduces energy resource consumption.Use the system-on-chip technology based on FPGA (programmable gate array) to realize LED-backlit brightness regulation, improve the system speed of response, strengthen product autgmentability, reduce product development cost.
Description
Technical field
The utility model relates to a kind of LCD TV intelligent eyes protecting system based on FPGA.
Background technology
As the requirements such as environmental protection, ultra-thin, image quality are improved constantly by consumer, in recent years, LCD TV with its large scale,
Fine definition, high-contrast and increasingly cheaper price, defeat CRT, rear-projection, PDP, becomes the absolute main flow of existing market.
And LED has been applied to different types of display device as backlight.Relative to the luminous cold-cathode tube of traditional CCFL() come
Saying, the colour gamut of LED is wider, color is more rich, the far super CCFL of dynamic contrast；Secondly LED-backlit brightness is high, and service life is long,
Power saving and radiate lower；The liquid crystal display device fuselage simultaneously using LED-backlit is thinner, and profile is also more attractive.How more preferable
The advantage of performance LED-backlit so that it is in image quality, energy consumption, especially reduce user's vision impairment etc. aspect be more intelligent and have
Important meaning.
The screen intensity of usual liquid crystal display device is set with the mode of manually setting and method for automatically programing two kinds.Usual hand
Dynamic setting screen brightness makes display device can not change with environmental light brightness, and user needs frequently according to current environment light
Screen intensity is manually regulated by degree, causes unnecessary energy resource consumption, and shortens the life-span of display device.If user is not
De-regulation screen intensity, can cause vision impairment because environmental light brightness is not mated with screen intensity again, affect visual experience.
Existing screen intensity method for automatically programing relies on detection environmental light brightness, is adjusted by single-chip microcomputer or picture processing chip
Joint.Owing to both chip communication modes are all serial mode, the therefore raising of the speed of response has bottleneck, is unfavorable for drawing in high definition
Under matter, backlight illumination is adjusted.And both chip autgmentabilities are not high, model change needs display device manufacturer pair
Backlight drive carries out brand-new design, and the product piece construction cycle is long, and cost increases.
Content of the invention
The purpose of this utility model is to solve the non adaptive of available liquid crystal display device brightness regulation, low extension
Property, the problem such as low operating efficiency, and a kind of LCD TV intelligent eyeshield system based on FPGA (programmable gate array) is proposed
System.
A kind of LCD TV intelligent eyes protecting system based on FPGA, this system includes:
Power circuit, clock circuit, ambient light detection circuit, FPGA control circuit, LED luminance regulation circuit, wherein,
FPGA control circuit includes fpga chip and SRAM storage chip；
Fpga chip is internally integrated I2C decoding circuit, CLK clock circuit, SRAM control circuit, light Comparison Circuit and
Pwm circuit, SRAM control circuit connects SRAM storage chip；Wherein I2C decoding circuit, CLK clock circuit, SRAM control electricity
Road, light Comparison Circuit and pwm circuit are connected to FPGA internal bus.
The beneficial effects of the utility model are:
The hardware components of the Intelligent eyeshield system that the utility model proposes can be divided into power circuit, clock electricity according to function
Road, ambient light detection circuit, FPGA control circuit, LED luminance regulation circuit；Light Comparison Circuit is integrated in FPGA control circuit
In.Ambient light detection circuit is used for detecting environmental light brightness, passes through I2C bus realizes communicating with fpga chip, by ambient light number
According to being transferred to FPGA control circuit；The ambient light data receiving is carried out threshold value by the bright Comparison Circuit in FPGA control circuit
Contrast, determines a need for sending pwm signal according to the result of contrast；LED luminance regulation circuit is electric according to receiving FPGA control
The pwm signal that road sends, regulates LED-backlit brightness.
The Intelligent eyeshield system based on FPGA that the utility model proposes, compared with the mode of manual regulation screen intensity,
The advantage with Automatic adjusument, can reduce the vision impairment to user for the screen light to greatest extent, reduces energy resource consumption.With
Existing method for automatically programing is compared, and uses the system-on-chip technology based on FPGA (programmable gate array) to realize that LED carries on the back
Brightness is regulated, and improves the system speed of response, strengthens product autgmentability, reduces product development cost.
Brief description
Fig. 1 is the LCD TV intelligent eyes protecting system composition structure chart based on FPGA that the utility model relates to；
Fig. 2 is the circuit diagram of annexation between the SRAM storage chip that relates to of the utility model and fpga chip；
Fig. 3 is the circuit diagram of the power circuit that the utility model relates to；
Fig. 4 is the circuit diagram of the clock circuit that relates to of the utility model and fpga chip annexation；
Fig. 5 is the circuit diagram of the ambient light detection circuit that relates to of the utility model and fpga chip annexation；
Fig. 6 is the circuit diagram that the LED luminance that the utility model relates to regulates annexation between circuit and fpga chip；
Detailed description of the invention
Detailed description of the invention one: the LCD TV intelligent eyes protecting system based on FPGA of present embodiment, in conjunction with Fig. 1 institute
Showing, this Intelligent eyeshield system includes:
FPGA control circuit, processes the ambient light data receiving, compares the threshold value of ambient light data and setting,
Determine whether to adjust LED-backlit brightness；
Power circuit, for providing 5.0V, 3.3V and 1.2V operating voltage respectively to the device in system；
Clock circuit, for providing work clock for the device in system；
Ambient light detection circuit, is used for detecting environmental light brightness, and ambient light data is passed through I2C bus transfer is to FPGA
Chip；
LED luminance regulates circuit, the result processing according to fpga chip data, adjusts the brightness of LED backlight array；
FPGA control circuit includes fpga chip and sram chip；
SRAM storage chip, is used for storing the algorithm required for fpga chip and program file；
Fpga chip, is used for receiving ambient light data, data process, it is determined whether adjust LED-backlit brightness；
Fpga chip connects clock circuit, ambient light detection circuit, LED luminance regulation circuit respectively；Wherein, fpga chip
It is internally integrated I2C decoding circuit, CLK clock circuit, SRAM control circuit, light Comparison Circuit and pwm circuit；SRAM controls electricity
Road connects SRAM storage chip；Wherein I2C decoding circuit, CLK clock circuit, SRAM control circuit, light Comparison Circuit and PWM
Circuit is connected to FPGA internal bus.
Detailed description of the invention two: from unlike detailed description of the invention one, the liquid crystal based on FPGA of present embodiment is electric
Depending on Intelligent eyeshield system, described FPGA control circuit includes: fpga chip and SRAM storage chip；And fpga chip is internally integrated
Light contrast circuit and SRAM control circuit, SRAM storage chip connects fpga chip by SRAM control circuit；
SRAM storage chip, is used for storing the algorithm required for fpga chip and program file；
Fpga chip, for light comparing, it is determined whether adjust LED-backlit brightness；
Wherein, as in figure 2 it is shown,
The nSCO pin of fpga chip connects the S# pin of sram chip；
The DCLK pin of fpga chip connects the C pin of sram chip by resistance R25；
The ASDO pin of fpga chip connects the DQ0 pin of sram chip；
The DATA0 pin of fpga chip connects the DQ1 pin of sram chip by resistance R26；
The VCCIO pin of fpga chip accesses 3.3V power input；VCCINT pin accesses 1.2V power input；
The VSS pin ground connection of sram chip；HOLD# pin and W# pins in parallel access 3.3V power input；VCC pin
Being simultaneously connected with 3.3V power input and electric capacity C36, the electric capacity C36 other end is grounded.
Detailed description of the invention three: from unlike detailed description of the invention one or two, the liquid based on FPGA of present embodiment
Brilliant television set intelligently eyes protecting system, described power circuit includes: two models are voltage conversion chip VR1 and the VR2 of MP2144, point
It is not used for generating 1.2V operating voltage and 3.3V operating voltage；
Wherein, as it is shown on figure 3, external 5V_INPUT positive source accesses the input of 5.0V power supply by electric current relay F1
End, minus earth；Voltage-stabiliser tube D1 reversed pole accesses 5.0V power input, and forward pole is grounded；
It is sequentially connected in series power conversion chip VR1 and inductance L1, electricity between 5.0V power input and 3.3V power input
Sense L1 two ends are connected with SW pin and the 3.3V power input of VR1 respectively；Electrochemical capacitor C1 is in parallel in the same direction with electrochemical capacitor C2,
The VIN pin of positive polarity termination VR1, negative polarity end is grounded；Resistance R1 mono-terminates the VIN pin of VR1, and the other end accesses VR1's
PG pin；Resistance R2 mono-terminates the VIN pin of VR1, the EN pin of another termination VR1；Resistance R3 mono-terminates the FB pin of VR1,
The other end is grounded；Resistance R4 mono-terminates the FB pin of VR1, and another terminates 3.3V power input；Electrochemical capacitor C3 and electric capacity C4
Parallel connection, C3 positive polarity terminates 3.3V power input, and negative polarity end is grounded；Two GND pin ground connection of VR1, OUT pin connects
3.3V power input；
It is sequentially connected in series power conversion chip VR2 and inductance L2, electricity between 5.0V power input and 1.2V power input
Sense L2 two ends are connected with SW pin and the 1.2V power input of VR2 respectively；Electrochemical capacitor C5 is in parallel in the same direction with electrochemical capacitor C6,
The VIN pin of positive polarity termination VR2, negative polarity end is grounded；Resistance R5 mono-terminates the VIN pin of VR2, and the other end accesses VR2's
PG pin；Resistance R6 mono-terminates the VIN pin of VR2, the EN pin of another termination VR2；Resistance R8 mono-terminates the FB pin of VR1,
The other end is grounded；Resistance R7 mono-terminates the FB pin of VR1, and another terminates 1.2V power input；Electrochemical capacitor C7 and electric capacity C8
Parallel connection, C7 positive polarity terminates 1.2V power input, and negative polarity end is grounded；Two GND pin ground connection of VR2, OUT pin connects
1.2V power input.
Detailed description of the invention four: from unlike detailed description of the invention one or three, the liquid based on FPGA of present embodiment
Brilliant television set intelligently eyes protecting system, described clock circuit includes: crystal oscillator Y1, provides the oscillation frequency required for clock chip
Rate；Model is the clock chip CLOCK of DS1302, for providing clock to fpga chip；Share in FPGA control circuit
Fpga chip, is used for receiving the clock that clock circuit provides, and provides work clock to other circuit；Fpga chip is internally integrated
CLK clock circuit, clock circuit connects fpga chip by CLK clock circuit；
Wherein, as shown in Figure 4, clock chip CLOCK and fpga chip junction circuit relationships are: the SCLK of fpga chip
Pin is connected with the SCLK pin of clock chip, the nRST pin of fpga chip and clock chipPin connects, FPGA
The DATA pin of chip is connected with the I/O pin of clock chip；
The SCLK pin of fpga chip connects 3.3V power input by pull-up resistor R22；
The nRST pin of fpga chip connects 3.3V power input by pull-up resistor R23；
The DATA pin of fpga chip connects 3.3V power input by pull-up resistor R24；
Crystal oscillator Y1 two ends connect X1 and the X2 pin of clock chip CLOCK respectively；
The VCC1 pin of clock chip is empty；VCC2 pin is simultaneously connected with 3.3V power input and electric capacity C35, electric capacity
The C35 other end is grounded.
Detailed description of the invention five: from unlike detailed description of the invention four, the liquid crystal based on FPGA of present embodiment is electric
Depending on Intelligent eyeshield system, described ambient light detection circuit includes: two models be MAX44009 bright detection chip SEN1 and
SEN2, is used for detecting environmental light brightness, and brightness data is passed through I2C bus transfer is to fpga chip；Share FPGA control electricity
The fpga chip on road, for receiving the bright data that light detection chip transmits；Fpga chip is internally integrated I2C decoding circuit,
I2C decoding circuit is simultaneously connected with light detection chip SEN1 and SEN2；
Wherein, as it is shown in figure 5, fpga chip with SEN1 chip junction circuit relationships is: the SDA pin of fpga chip with
The SDA pin of SEN1 chip connects, fpga chipPin and SEN1 chipPin connects, the SCL of fpga chip
Pin is connected with the SCL pin of SEN1 chip；
Fpga chip with SEN2 chip junction circuit relationships is: the SDA pin of fpga chip and the SDA of SEN2 chip draw
Pin connects, fpga chipPin and SEN2 chipPin connects, the SCL pin of fpga chip and SEN2 core
The SCL pin of piece connects；
The SDA pin of fpga chip is connected with 3.3V power input by pull-up resistor R9,Pin is by pull-up
Resistance R11 is connected with 3.3V power input, and SCL pin is connected with 3.3V power input by pull-up resistor R10；
5.0V power input is simultaneously connected with the VCC pin of SEN1, the VCC pin of SEN2 and electric capacity C9, electric capacity C9 another
End ground connection；
The GND pin of SEN1 chip is grounded with A0 pin；
The GND pin of SEN2 chip is grounded with A0 pin.
Detailed description of the invention six: from unlike detailed description of the invention four, the liquid crystal based on FPGA of present embodiment is electric
Depending on Intelligent eyeshield system, described LED luminance regulation circuit includes: model is LED drive chip LEDDR of MAX16814, is used for
Control LED luminance；4 road series LED backlight array, luminous for back light member；Share the fpga chip of FPGA control circuit, use
In sending LED luminance regulating command；Fpga chip is internally integrated pwm circuit, and pwm circuit connects LED drive chip LEDDR,
LEDDR chip connects 4 road series LED arrays；
Wherein, as shown in Figure 6, fpga chip and LEDDR chip junction circuit relationships are: fpga chipPin
With LEDDR chipPin connects, and the DIM pin of fpga chip is connected with the DIM pin of LEDDR chip, fpga chip
EN pin is connected with the EN pin of LEDDR chip；
External 40V_INPUT positive source accesses the IN pin of LEDDR chip, minus earth by electric current relay F2；
The VCC pin of LEDDR chip is concurrently accessed 5.0V power input and electric capacity C16, and the electric capacity C16 other end is grounded；
The RT pin of LEDDR chip is grounded by resistance R16；
The ISET pin of LEDDR chip is grounded by resistance R17；
Resistance R21 and the electric capacity C17 ground connection by series connection for the COMP pin of LEDDR chip；
The RSDT pin of LEDDR chip is simultaneously connected with resistance R20 and resistance R19, and the resistance R20 other end is grounded, resistance R19
The other end connects 5.0V voltage input end；
The DRV pin of LEDDR chip is simultaneously connected with resistance R18 and electric capacity C18, and the electric capacity C18 other end is grounded, resistance R18
The other end connects 5.0V voltage input end；
The OUT1 pin of LEDDR chip connects the reversed pole of the 1st road series LED array；
The OUT2 pin of LEDDR chip connects the reversed pole of the 2nd road series LED array；
The OUT3 pin of LEDDR chip connects the reversed pole of the 3rd road series LED array；
The OUT4 pin of LEDDR chip connects the reversed pole of the 4th road series LED array；
The IN pin of LEDDR chip is simultaneously connected with electric capacity C11, electric capacity C13 and inductance L3, the electric capacity C11 other end and electric capacity
The C13 other end is grounded, and the inductance L3 other end is simultaneously connected with electric capacity C12 and inductance L4, and the electric capacity C12 other end is grounded, and inductance L4 is another
One end is concurrently accessed gate pole and the drain electrode of the NDRV pin of LEDDR chip, the forward pole of diode D2 and FET Q1, and two
Pole pipe D2 reversed pole connects the forward pole of 4 road series LED arrays in parallel；
The CS pin of LEDDR chip connects resistance R12, the resistance R12 other end be simultaneously connected with FET Q1 source electrode and
Resistance R15, the resistance R15 other end is grounded；
The OVP pin of LEDDR chip is simultaneously connected with resistance R13, electric capacity R14 and electric capacity C15, and resistance R14 and electric capacity C15 is simultaneously
Other end ground connection after connection, the resistance R13 other end is simultaneously connected with diode D2 reversed pole and electric capacity C14, another termination of electric capacity C14
Ground.
Claims (5)
1. the LCD TV intelligent eyes protecting system based on FPGA, it is characterised in that: protect based on the LCD TV intelligent of FPGA
Eye system includes:
Power circuit, clock circuit, ambient light detection circuit, FPGA control circuit, LED luminance regulation circuit；Wherein,
FPGA control circuit includes fpga chip and SRAM storage chip；
Fpga chip is internally integrated I2C decoding circuit, CLK clock circuit, SRAM control circuit, light Comparison Circuit and PWM electricity
Road, SRAM control circuit connects SRAM storage chip；Wherein I2C decoding circuit, CLK clock circuit, SRAM control circuit, light
Comparison Circuit and pwm circuit are connected to FPGA internal bus,
Wherein: the nSCO pin of fpga chip connects the S# pin of sram chip；
The DCLK pin of fpga chip connects the C pin of sram chip by resistance R25；
The ASDO pin of fpga chip connects the DQ0 pin of sram chip；
The DATA0 pin of fpga chip connects the DQ1 pin of sram chip by resistance R26；
The VCCIO pin of fpga chip accesses 3.3V power input；VCCINT pin accesses 1.2V power input；
The VSS pin ground connection of sram chip；HOLD# pin and W# pins in parallel access 3.3V power input；VCC pin is simultaneously
Connecting 3.3V power input and electric capacity C36, the electric capacity C36 other end is grounded.
2. according to claim 1 based on the LCD TV intelligent eyes protecting system of FPGA, it is characterised in that: described power circuit
Including:
Two models are voltage conversion chip VR1 and the VR2 of MP2144, wherein:
External 5V_INPUT positive source accesses 5.0V power input, minus earth by electric current relay F1；Voltage-stabiliser tube D1
Reversed pole accesses 5.0V power input, and forward pole is grounded；
It is sequentially connected in series power conversion chip VR1 and inductance L1, inductance L1 between 5.0V power input and 3.3V power input
Two ends are connected with SW pin and the 3.3V power input of VR1 respectively；Electrochemical capacitor C1 is in parallel in the same direction with electrochemical capacitor C2, positive pole
Property termination VR1 VIN pin, negative polarity end be grounded；Resistance R1 mono-terminates the VIN pin of VR1, and the PG that the other end accesses VR1 draws
Pin；Resistance R2 mono-terminates the VIN pin of VR1, the EN pin of another termination VR1；Resistance R3 mono-terminates the FB pin of VR1, another
End ground connection；Resistance R4 mono-terminates the FB pin of VR1, and another terminates 3.3V power input；Electrochemical capacitor C3 is in parallel with electric capacity C4,
C3 positive polarity terminates 3.3V power input, and negative polarity end is grounded；Two GND pin ground connection of VR1, OUT pin connects 3.3V electricity
Source input；
It is sequentially connected in series power conversion chip VR2 and inductance L2, inductance L2 between 5.0V power input and 1.2V power input
Two ends are connected with SW pin and the 1.2V power input of VR2 respectively；Electrochemical capacitor C5 is in parallel in the same direction with electrochemical capacitor C6, positive pole
Property termination VR2 VIN pin, negative polarity end be grounded；Resistance R5 mono-terminates the VIN pin of VR2, and the PG that the other end accesses VR2 draws
Pin；Resistance R6 mono-terminates the VIN pin of VR2, the EN pin of another termination VR2；Resistance R8 mono-terminates the FB pin of VR1, another
End ground connection；Resistance R7 mono-terminates the FB pin of VR1, and another terminates 1.2V power input；Electrochemical capacitor C7 is in parallel with electric capacity C8,
C7 positive polarity terminates 1.2V power input, and negative polarity end is grounded；Two GND pin ground connection of VR2, OUT pin connects 1.2V electricity
Source input.
3. according to claim 1 based on the LCD TV intelligent eyes protecting system of FPGA, it is characterised in that: described clock circuit
Including:
Model is the fpga chip of the clock chip CLOCK of DS1302, crystal oscillator Y1 and shared FPGA control circuit,
Fpga chip is internally integrated CLK clock circuit, and CLK clock circuit connects clock chip CLOCK；
Wherein, clock chip CLOCK and fpga chip junction circuit relationships are: the SCLK pin of fpga chip and clock chip
SCLK pin connect, the nRST pin of fpga chip and clock chipPin connects, the DATA pin of fpga chip
It is connected with the I/O pin of clock chip；
The SCLK pin of fpga chip connects 3.3V power input by pull-up resistor R22；
The nRST pin of fpga chip connects 3.3V power input by pull-up resistor R23；
The DATA pin of fpga chip connects 3.3V power input by pull-up resistor R24；
Crystal oscillator Y1 two ends connect X1 and the X2 pin of clock chip CLOCK respectively；
The VCC1 pin of clock chip is empty；VCC2 pin is simultaneously connected with 3.3V power input and electric capacity C35, and electric capacity C35 is another
One end is grounded.
4. according to claim 1 based on the LCD TV intelligent eyes protecting system of FPGA, it is characterised in that: described ambient light is examined
Slowdown monitoring circuit includes:
Two models are bright detection chip SEN1 and SEN2, the fpga chip sharing FPGA control circuit of MAX44009,
Fpga chip is internally integrated I2C decoding circuit, I2C decoding circuit is simultaneously connected with light detection chip SEN1 and SEN2；
Fpga chip with SEN1 chip junction circuit relationships is: the SDA pin of fpga chip connects with the SDA pin of SEN1 chip
Connect, fpga chipPin and SEN1 chipPin connects, the SCL pin of fpga chip and SEN1 chip
SCL pin connects；
Fpga chip with SEN2 chip junction circuit relationships is: the SDA pin of fpga chip connects with the SDA pin of SEN2 chip
Connect, fpga chipPin and SEN2 chipPin connects, the SCL pin of fpga chip and SEN2 chip
SCL pin connects；
The SDA pin of fpga chip is connected with 3.3V power input by pull-up resistor R9,Pin passes through pull-up resistor
R11 is connected with 3.3V power input, and SCL pin is connected with 3.3V power input by pull-up resistor R10；
5.0V power input is simultaneously connected with the VCC pin of SEN1, the VCC pin of SEN2 and electric capacity C9, another termination of electric capacity C9
Ground；
The GND pin of SEN1 chip is grounded with A0 pin；
The GND pin of SEN2 chip is grounded with A0 pin.
5. according to claim 1 based on the LCD TV intelligent eyes protecting system of FPGA, it is characterised in that: described LED luminance
Regulation circuit includes:
Model is LED drive chip LEDDR of MAX16814,4 road series LED backlight array and shared FPGA control circuit
Fpga chip, fpga chip is internally integrated pwm circuit, and pwm circuit connects LED drive chip LEDDR, and LEDDR chip connects 4 tunnels
Series LED array；
Fpga chip with LEDDR chip junction circuit relationships is: fpga chipPin and LEDDR chipDraw
Pin connects, and the DIM pin of fpga chip is connected with the DIM pin of LEDDR chip, the EN pin of fpga chip and LEDDR chip
EN pin connect；
External 40V_INPUT positive source accesses the IN pin of LEDDR chip, minus earth by electric current relay F2；
The VCC pin of LEDDR chip is concurrently accessed 5.0V power input and electric capacity C16, and the electric capacity C16 other end is grounded；
The RT pin of LEDDR chip is grounded by resistance R16；
The ISET pin of LEDDR chip is grounded by resistance R17；
Resistance R21 and the electric capacity C17 ground connection by series connection for the COMP pin of LEDDR chip；
The RSDT pin of LEDDR chip is simultaneously connected with resistance R20 and resistance R19, and the resistance R20 other end is grounded, resistance R19 another
End connects 5.0V voltage input end；
The DRV pin of LEDDR chip is simultaneously connected with resistance R18 and electric capacity C18, and the electric capacity C18 other end is grounded, resistance R18 another
End connects 5.0V voltage input end；
The OUT1 pin of LEDDR chip connects the reversed pole of the 1st road series LED array；
The OUT2 pin of LEDDR chip connects the reversed pole of the 2nd road series LED array；
The OUT3 pin of LEDDR chip connects the reversed pole of the 3rd road series LED array；
The OUT4 pin of LEDDR chip connects the reversed pole of the 4th road series LED array；
The IN pin of LEDDR chip is simultaneously connected with electric capacity C11, electric capacity C13 and inductance L3, and the electric capacity C11 other end and electric capacity C13 are another
One end is grounded, and the inductance L3 other end is simultaneously connected with electric capacity C12 and inductance L4, and the electric capacity C12 other end is grounded, and the inductance L4 other end is same
When access gate pole and drain electrode, the diode D2 of the NDRV pin of LEDDR chip, the forward pole of diode D2 and FET Q1
Reversed pole connects the forward pole of 4 road series LED arrays in parallel；
The CS pin of LEDDR chip connects resistance R12, and the resistance R12 other end is simultaneously connected with source electrode and the resistance of FET Q1
R15, the resistance R15 other end is grounded；
The OVP pin of LEDDR chip is simultaneously connected with resistance R13, electric capacity R14 and electric capacity C15, after resistance R14 and electric capacity C15 is in parallel
The other end is grounded, and the resistance R13 other end is simultaneously connected with diode D2 reversed pole and electric capacity C14, and the electric capacity C14 other end is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620310684.XU CN205722746U (en) | 2016-04-14 | 2016-04-14 | LCD TV intelligent eyes protecting system based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620310684.XU CN205722746U (en) | 2016-04-14 | 2016-04-14 | LCD TV intelligent eyes protecting system based on FPGA |
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| Publication Number | Publication Date |
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| CN205722746U true CN205722746U (en) | 2016-11-23 |
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| CN201620310684.XU Expired - Fee Related CN205722746U (en) | 2016-04-14 | 2016-04-14 | LCD TV intelligent eyes protecting system based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380167A (en) * | 2021-06-15 | 2021-09-10 | 西安微电子技术研究所 | Aerospace-grade nixie tube display driving circuit and application thereof |
-
2016
- 2016-04-14 CN CN201620310684.XU patent/CN205722746U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380167A (en) * | 2021-06-15 | 2021-09-10 | 西安微电子技术研究所 | Aerospace-grade nixie tube display driving circuit and application thereof |
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