CN205721497U - A kind of DEBUG circuit - Google Patents
A kind of DEBUG circuit Download PDFInfo
- Publication number
- CN205721497U CN205721497U CN201620275328.9U CN201620275328U CN205721497U CN 205721497 U CN205721497 U CN 205721497U CN 201620275328 U CN201620275328 U CN 201620275328U CN 205721497 U CN205721497 U CN 205721497U
- Authority
- CN
- China
- Prior art keywords
- debug
- interface
- circuit
- stitch
- mini pci
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
A kind of DEBUG circuit, including mini PCI E interface (J2) and South Bridge chip (U1)；This miniPCI E interface (J2) has one group of DEBUG stitch needing to be connected with South Bridge chip (U1) when mini PCI E interface (J2) connects DEBUG card, part stitch in this group DEBUG stitch is additionally operable to when expanding the 3G/4G function of mainboard connect SIM, wherein, each stitch in this group DEBUG stitch is all connected to the corresponding pin of this South Bridge chip (U1) each via an on-off circuit；When this mini PCI E interface (J2) is connected DEBUG card, all of on-off circuit is connected；When this mini PCI E interface (J2) is connected with the dismounting of DEBUG card, all of on-off circuit is disconnected.Can directly plug the DEBUG card of band MINIPCIE interface linkage function on the market after using circuit of the present utility model, convenient mainboard debugged and keeps in repair, can the most reasonably utilize the slack resources on mini PCI E interface simultaneously.
Description
Technical field
This utility model relates to computer motherboard technical field, particularly relates to a kind of DEBUG circuit.
Background technology
The card that DEBUG card computer realm uses R&D process or subsequent maintenance mainboard when, permissible
The general abort situation positioning mainboard.Mainboard runs the most forward a step, has a corresponding code, DEBUG
Card is i.e. to be shown by this code, main board failure position, convenient location.Have on the market and much need to use
The DEBUG card of mini PCI-E interface, makes if individually making a MINIPCIE socket supply DEBUG card
If with, it will cause the biggest waste.
Mini PCI-E interface is the interface of Based PC I-E bus, can extend on mainboard WIFI,
3G/4G, MSATA, bluetooth equipment etc..Connect as it is shown in figure 1, illustrate mini PCI-E interface
One SIM does 3/4G function, and in figure, J1 represents mini PCI-E interface, and SIM1 represents SIM.
Visible, the when of connecting SIM, 8,10,12,14,16 pins of mini PCI-E interface are the use of,
But when not carrying out 3/4G functions expanding, these pins are the most idle, and these pins belong to just
Being used for time mini PCI-E interface connects DEBUG card connects the part stitch of South Bridge chip.
Utility model content
The technical problems to be solved in the utility model is, for the drawbacks described above of prior art, it is provided that a kind of
DEBUG circuit.
This utility model solves its technical problem and be the technical scheme is that a kind of DEBUG circuit of structure,
Including mini PCI-E interface and South Bridge chip；This mini PCI-E interface has one group at mini PCI-E
The DEBUG stitch being connected with South Bridge chip is needed, in this group DEBUG stitch when interface connects DEBUG card
Part stitch is additionally operable to when expanding the 3G/4G function of mainboard connect SIM, wherein, this group DEBUG
Each stitch in stitch is all connected to the corresponding pin of this South Bridge chip each via an on-off circuit；When
When this mini PCI-E interface is connected DEBUG card, all of on-off circuit is connected；When by this mini
PCI-E interface is removed with DEBUG card when being connected, and is disconnected by all of on-off circuit.
In DEBUG circuit described in the utility model, this on-off circuit is the resistance of zero ohm.
In DEBUG circuit described in the utility model, this on-off circuit is electrical switch.
In DEBUG circuit described in the utility model, the model of this South Bridge chip is Intel 8 series core
Sheet group, this group DEBUG stitch is the 8 of mini PCI-E interface, 10,12,14,16,17, No. 19
Stitch number, wherein, the 8 of this mini PCI-E interface, 10,12,14, No. 16 stitch one a pair respectively
Answer by this on-off circuit connect this South Bridge chip for export LPC_FRAME_N signal,
LPC_AD3 signal, LPC_AD2 signal, LPC_AD1 signal, 5 pins of LPC_AD0 signal, should
No. 17 stitch of mini PCI-E interface connect the flat for exporting of this South Bridge chip by an on-off circuit
The pin of platform reset signal, No. 19 stitch of this mini PCI-E interface are connected by an on-off circuit should
The pin for exporting 33MHZ clock signal of South Bridge chip.
Implement DEBUG circuit of the present utility model, have the advantages that this utility model directly utilizes
Mini PCI-E interface for expanding mainboard 3G/4G function of the prior art realizes connecting DEBUG card,
Because mini PCI-E interface have one group when it connects DEBUG card needs be connected with South Bridge chip
DEBUG stitch, the part stitch in this group DEBUG stitch is additionally operable to when expanding the 3G/4G function of mainboard
Connect SIM, this utility model by each stitch in this group DEBUG stitch all each via a switch
Circuit is connected to the corresponding pin of this South Bridge chip；Therefore, when this mini PCI-E interface is connected DEBUG
During card, all of on-off circuit is connected；It is connected when this mini PCI-E interface is removed with DEBUG card
Time, all of on-off circuit is disconnected, SIM can be connected after disconnection and expand the 3G/4G function of mainboard.
Therefore, the DEBUG of band MINIPCIE interface linkage function on the market can directly be plugged after using this circuit
Card, conveniently debugs mainboard and keeps in repair, and can the most reasonably utilize mini PCI-E interface simultaneously
On slack resources.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is described in further detail, in accompanying drawing:
Fig. 1 is the structural representation that mini PCI-E interface connects SIM；
Fig. 2 is the structural representation of DEBUG circuit of the present utility model.
Detailed description of the invention
In order to technical characteristic of the present utility model, purpose and effect are more clearly understood from, now compare attached
Figure describes detailed description of the invention of the present utility model in detail.
As in figure 2 it is shown, be the structural representation of DEBUG circuit of the present utility model.
DEBUG circuit of the present utility model includes mini PCI-E interface J2 and South Bridge chip U1；This mini
PCI-E interface J2 has one group to be needed and south bridge core when mini PCI-E interface J2 connects DEBUG card
The DEBUG stitch that sheet U1 connects, the part stitch in this group DEBUG stitch is additionally operable to expanding mainboard
Connecting SIM during 3G/4G function, wherein, each stitch in this group DEBUG stitch is all each via one
Individual on-off circuit is connected to the corresponding pin of this South Bridge chip U1；When by this mini PCI-E interface J2 even
When connecing DEBUG card, all of on-off circuit is connected；When by this mini PCI-E interface J2 and DEBUG
Card is removed when connecting, and is disconnected by all of on-off circuit.
South Bridge chip (South Bridge) is the important component part of board chip set, is normally at mainboard
On from CPU slot lower section farther out.South Bridge chip is responsible for the communication between I/O bus, as pci bus,
USB, LAN, ATA, SATA, Audio Controller, KBC, real-time clock controller, senior electricity
Source control etc..
When utilizing the fault of DEBUG card location mainboard, connect south bridge core if, with mini PCI-E interface
Sheet U1, then by after mini PCI-E interface and DEBUG card grafting, need mini PCI-E interface
DEBUG stitch is connected with South Bridge chip.The stitch of mini PCI-E interface is all unified definition, this group
DEBUG stitch is exactly the 8 of mini PCI-E interface J2,10,12,14,16,17, No. 19 stitch number.
Wherein, 8,10,12,14, No. 16 stitch number are also that mini PCI-E interface J2 expands 3G/4G function
Time be used for connecting the stitch of SIM.
In specific embodiment, the model of this South Bridge chip U1 is Intel 8 family chip group, this mini
The 8 of PCI-E interface J2,10,12,14, No. 16 stitch are the most one to one by this switch
Circuit connect this South Bridge chip U1 for exporting LPC_FRAME_N signal, LPC_AD3 signal, LPC_AD2
Signal, LPC_AD1 signal, 5 pins of LPC_AD0 signal, the 17 of this mini PCI-E interface J2
Number stitch by an on-off circuit connect this South Bridge chip U1 for output stage reset signal
The pin of PLTRST_N, No. 19 stitch of this mini PCI-E interface J2 are connected by an on-off circuit
The pin for exporting 33MHZ clock signal LPC_33M_CLK of this South Bridge chip U1, is summarized as follows table
Shown in 1:
Table 1
Wherein, this on-off circuit is the resistance of zero ohm, it is also possible to for electrical switch.From the angle saving resource
Degree considers, preferably uses the resistance of zero ohm.
As No. 16 stitch of the J2 in Fig. 2 are connected to the AN24 pin of U1 by resistance R816, J2's
No. 14 stitch are connected to the AN26 pin of U1 by resistance R817, and No. 12 stitch of J2 pass through resistance R818
Being connected to the AJ24 pin of U1, the AN26 that No. 10 stitch of J2 are connected to U1 by resistance R820 draws
Foot, No. 8 stitch of J2 are connected to the AP24 pin of U1 by resistance R821, and No. 17 stitch of J2 lead to
Crossing resistance R808 and be connected to the AA37 pin of U1, No. 19 stitch of J2 are connected to U1 by resistance R807
AV5 pin.
Resistance R816, R817, R818, R820, R821, R808, R807 are 0 ohm, at needs
During disconnection, directly the connection of one end of resistance is laid down, use resistance as switch, low cost, reality
Now facilitate.
In Fig. 2, LPC_AD0, LPC_AD1, LPC_AD2, LPC_AD3, LPC_FRAME_N signal is corresponding
Pin be all slaves to LPC (the Low Pin Count) interface of South Bridge chip.LPC interface is Intel
In a kind of new interface specification of a replacement tradition ISA BUS of JIUYUE in 1997 announcement on the 29th, and
In the way of the mandate that opens for free, use for industry.LPC interface defined in intel, by conventional ISA BUS
Address/data separate decoding, make the decoded mode that the address/data signal line of similar PCI is shared, letter into
Number line quantity is greatly reduced, and operating rate is driven by pci bus synchronization of rate, although improved LPC
Interface equally maintains maximum transmitted value 16MB/s, but required signal pins figure place is greatly reduced 25～30
Individual, pin number minimizing, body can be enjoyed with Super I/O chip, the Flash chip of LPC Interface design
The benefit of long-pending micro, the design of mainboard can also simplify, and this is namely named LPC Low Pin Count
Reason.
In sum, implement DEBUG circuit of the present utility model, have the advantages that this practicality is new
Type directly utilizes the mini PCI-E interface for expanding mainboard 3G/4G function of the prior art and realizes even
Connect DEBUG card, need and south bridge when it connects DEBUG card because mini PCI-E interface has one group
The DEBUG stitch that chip connects, the part stitch in this group DEBUG stitch is additionally operable to expanding mainboard
Connecting SIM during 3G/4G function, this utility model is by the most respective for each stitch in this group DEBUG stitch
The corresponding pin of this South Bridge chip it is connected to by an on-off circuit；Therefore, when by this mini PCI-E
When interface connects DEBUG card, all of on-off circuit is connected；When by this mini PCI-E interface and DEBUG
Card is removed when connecting, and is disconnected by all of on-off circuit, can connect SIM and expand mainboard after disconnection
3G/4G function.Therefore, band MINIPCIE interface on the market can directly be plugged after using this circuit even
The DEBUG card of connection function, conveniently debugs mainboard and keeps in repair, and can the most reasonably utilize simultaneously
Slack resources in mini PCI-E interface.
Above in conjunction with accompanying drawing, embodiment of the present utility model is described, but this utility model not office
Being limited to above-mentioned detailed description of the invention, above-mentioned detailed description of the invention is only schematically rather than to limit
Property, those of ordinary skill in the art is under enlightenment of the present utility model, without departing from this utility model ancestor
In the case of purport and scope of the claimed protection, it may also be made that a lot of form, it is new that these belong to this practicality
Within the protection of type.
Claims (4)
1. a DEBUG circuit, it is characterised in that include mini PCI-E interface (J2) and south bridge core
Sheet (U1)；This mini PCI-E interface (J2) has one group and connects in mini PCI-E interface (J2)
The DEBUG stitch being connected with South Bridge chip (U1), the portion in this group DEBUG stitch is needed during DEBUG card
Minute hand foot is additionally operable to when expanding the 3G/4G function of mainboard connect SIM, wherein, this group DEBUG stitch
In each stitch be all connected to the corresponding pin of this South Bridge chip (U1) each via an on-off circuit；
When this mini PCI-E interface (J2) is connected DEBUG card, all of on-off circuit is connected；When
When this mini PCI-E interface (J2) is connected with the dismounting of DEBUG card, all of on-off circuit is disconnected.
DEBUG circuit the most according to claim 1, it is characterised in that this on-off circuit is zero Europe
The resistance of nurse.
DEBUG circuit the most according to claim 1, it is characterised in that this on-off circuit is electronics
Switch.
DEBUG circuit the most according to claim 1, it is characterised in that this South Bridge chip (U1)
Model be Intel 8 family chip group, this group DEBUG stitch is mini PCI-E interface (J2)
8,10,12,14,16,17, No. 19 stitch number, wherein, this mini PCI-E interface (J2) 8,
10,12,14, No. 16 stitch connect this South Bridge chip by this on-off circuit the most one to one
(U1) be used for exports LPC_FRAME_N signal, LPC_AD3 signal, LPC_AD2 signal, LPC_AD1
Signal, 5 pins of LPC_AD0 signal, No. 17 stitch of this mini PCI-E interface (J2) pass through
One on-off circuit connects the pin for output stage reset signal of this South Bridge chip (U1), this mini
No. 19 stitch of PCI-E interface (J2) connect the use of this South Bridge chip (U1) by an on-off circuit
Pin in output 33MHZ clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620275328.9U CN205721497U (en) | 2016-04-05 | 2016-04-05 | A kind of DEBUG circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620275328.9U CN205721497U (en) | 2016-04-05 | 2016-04-05 | A kind of DEBUG circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205721497U true CN205721497U (en) | 2016-11-23 |
Family
ID=57312219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620275328.9U Expired - Fee Related CN205721497U (en) | 2016-04-05 | 2016-04-05 | A kind of DEBUG circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205721497U (en) |
-
2016
- 2016-04-05 CN CN201620275328.9U patent/CN205721497U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161123 Termination date: 20200405 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |