CN205681381U - Two-stage calculation amplifier - Google Patents

Abstract

The utility model discloses a kind of two-stage calculation amplifier, including: bias voltage signal generating unit, first order operation amplifier unit and second level operation amplifier unit, wherein first order operation amplifier unit includes: Foldable cascade amplifying circuit and cross-couplings load, cross-couplings load with the load differential in Foldable cascade amplifying circuit to being connected, cross-couplings load includes two transistors, two transistors in cross-couplings load constitute two current-mirror structure with two transistors of corresponding load differential centering respectively, and two current-mirror structure cross-couplings.The technical solution of the utility model by load differential in Foldable cascade amplifying circuit on increase cross-couplings load, to realize the gain taking positive feedback negative conductance gain suppression technology to increase two-stage calculation amplifier；Meanwhile, by the parameter of the mos pipe in Foldable cascade amplifying circuit is rationally arranged, it is possible to decrease the noise of two-stage calculation amplifier.

Description

Two-stage calculation amplifier

Technical field

The utility model relates to circuit design field, particularly to a kind of two-stage calculation amplifier.

Background technology

Operational amplifier is many one of simulation system and mixed-signal system piths, high DC current gain without It is suspected to be the important design objective of operational amplifier.Owing to operational amplifier is generally used to realize a reponse system, its open loop is straight The size of flow enhancement determines the precision of the reponse system using operational amplifier.

At present, the two-stage calculation amplifier based on Foldable cascade structure, it can provide the same of higher gain When, may also provide bigger output voltage swing.Specifically, first order amplifier is used for realizing high-gain and provides suitably pendulum Width, second level amplifier is used for increasing output voltage swing.But, though existing two-stage calculation amplifier is with being provided that high-gain, but It is that himself noise (flicker noise and thermal noise) is bigger so that the overall performance of amplifier promotes and is restricted.

From foregoing, provide the two-stage calculation amplifier of a kind of high-gain, low noise, be that this area is needed badly solution Technical problem certainly.

Utility model content

The utility model provides a kind of two-stage calculation amplifier, it is intended at least solve prior art exists technical problem it One.

For achieving the above object, the utility model provides a kind of two-stage calculation amplifier, comprising: bias voltage generates single Unit, first order operation amplifier unit and second level operation amplifier unit；

Described bias voltage signal generating unit, with described first order operation amplifier unit and described second level operation amplifier unit It is all connected with, for providing corresponding biased electrical to described first order operation amplifier unit and described second level operation amplifier unit Pressure；

Described first order operation amplifier unit, is connected with described second level operation amplifier unit, is used for providing large gain, bag Include: Foldable cascade amplifying circuit and cross-couplings load, the load of described cross-couplings and described Foldable cascade Load differential in amplifying circuit is to connection, and the load of described cross-couplings includes two transistors, in the load of described cross-couplings Two transistors, two transistor one_to_one corresponding with corresponding described load differential centering respectively, and constitute two current mirrors Structure, two described current-mirror structure cross-couplings；

Second level operation amplifier unit, for increasing the output pendulum of described first order operation amplifier unit institute output signal Width.

Alternatively, described Foldable cascade amplifying circuit includes:

The first transistor, its grid is connected with the 4th bias voltage output of described bias voltage signal generating unit, source Pole is connected with the first power end；

Transistor seconds, its grid and the first signal input part connect, and source electrode is connected with the drain electrode of described the first transistor；

Third transistor, its grid is connected with secondary signal input, and source electrode is connected with the drain electrode of described the first transistor；

4th transistor, its grid is connected with described 4th bias voltage output, and source electrode is connected with second source end, leakage Pole is connected with the drain electrode of described transistor seconds；

5th transistor, its grid is connected with described 4th bias voltage output, and source electrode is with described second source end even Connecing, drain electrode is connected with the drain electrode of described third transistor；

6th transistor, its grid is connected with the 3rd bias voltage output of described bias voltage signal generating unit, source electrode Drain electrode with described 4th transistor is connected；

7th transistor, its grid is connected with described 3rd bias voltage output, source electrode and described 5th transistor Drain electrode connects, and drain electrode is connected with described second level operation amplifier unit；

8th transistor, its grid is connected with the second bias voltage output of described bias voltage signal generating unit, drain electrode Drain electrode with described 6th transistor is connected；

9th transistor, its grid is connected with described second bias voltage output, drain electrode and described 7th transistor Drain electrode connects；

Tenth transistor, its grid is connected with the source electrode of described 8th transistor, the source of drain electrode and described 8th transistor Pole connects, and source electrode is connected with described first power end；

11st transistor, its grid is connected with the source electrode of described 9th transistor, drain electrode and described 9th transistor Source electrode connects, and described in source electrode, the first power end connects；

Described tenth transistor and the 11st transistor constitute described load differential pair.

Alternatively, described cross-couplings load includes:

Tenth two-transistor, its grid is connected with the source electrode of described 8th transistor, drain electrode and described 9th transistor Source electrode connects, and source electrode is connected with described first power end；

13rd transistor, its grid is connected with the source electrode of described 9th transistor, drain electrode and described 8th transistor Source electrode connects, and source electrode is connected with described first power end；

Described tenth two-transistor constitutes current-mirror structure with described tenth transistor, described in described 13rd transistor AND gate 11st transistor constitutes current-mirror structure.

Alternatively, described the first transistor, described transistor seconds, described third transistor, described 8th transistor, institute State the 9th transistor, described tenth transistor, described 11st transistor, described tenth two-transistor and described 13rd crystal Pipe is N-type mos pipe；

Described 4th transistor, described 5th transistor, described 6th transistor and described 7th transistor are p-type Mos manages.

Alternatively, the width of the raceway groove of described the first transistor is 1um, a length of 600nm；

The width of the raceway groove of described transistor seconds and described third transistor is 1.2um, and length is 600nm；

The width of the raceway groove of described 4th transistor and described 5th transistor is 1um, and length is 5um；

The width of the raceway groove of described 6th transistor and described 7th transistor is 1um, and length is 2.5um；

The width of the raceway groove of described 8th transistor and described 9th transistor is 1um, and length is 8um；

The width of the raceway groove of described tenth transistor and described 11st transistor is 600nm, and length is 600nm；

The width of the raceway groove of described tenth two-transistor and described 13rd transistor is 600nm, and length is 600nm。

Alternatively, described bias voltage signal generating unit includes:

14th transistor, its grid and the first bias current inputs and the second bias voltage output connect, drain electrode It is connected with described first bias current inputs；

15th transistor, its grid is connected with described second bias voltage output, drain electrode and described second biased electrical Stream input connects；

16th transistor, its grid is connected with described second bias voltage output, drain electrode and described 14th crystal The source electrode of pipe connects, and source electrode and the first power end connect；

17th transistor, its grid is connected with source electrode and the 3rd bias voltage output of described 15th transistor, Source electrode is connected with described first power end；

18th transistor, its grid and the first bias voltage output connect, and source electrode is connected with second source end；

19th transistor, its grid and the 4th bias voltage output connect, and source electrode is connected with described second source end, Drain electrode is connected with described 4th bias voltage output；

20th transistor, its grid is connected with described first bias voltage output, source electrode and described 18th crystal The drain electrode of pipe connects, and drain electrode is connected with described first bias voltage output；

21st transistor, its grid is connected with described first bias voltage output, source electrode and described 19th crystalline substance The drain electrode of body pipe connects；

20th two-transistor, its grid is connected with described second bias voltage output, drain electrode and described 20th crystalline substance The drain electrode of body pipe connects；

23rd transistor, its grid is connected with described second bias voltage output, drain electrode and the described 21st Transistor drain connects；

24th transistor, its grid is connected with described 3rd bias voltage output, drain electrode and the described 22nd The source electrode of transistor connects, and source electrode is connected with described first power end；

25th transistor, its grid is connected with described 3rd bias voltage output, drain electrode and the described 23rd The source electrode of transistor connects, and source electrode is connected with described first power end.

Alternatively, described 14th transistor, described 15th transistor, described 16th transistor, the described 17th Transistor, described 20th two-transistor, described 23rd transistor, described 24th transistor and the described 25th Transistor is N-type mos pipe；

Described 18th transistor, described 19th transistor, described 20th transistor and described 21st crystal Pipe is p-type mos pipe.

Alternatively, the width of the raceway groove of described 14th transistor is 910nm, a length of 10um；

The width of the raceway groove of described 15th transistor is 1um, a length of 7.5um；

The width of the raceway groove of described 16th transistor and described 17th transistor is 600nm, and length is 10um；

The width of the raceway groove of described 18th transistor is 750nm, a length of 10um；

The width of the raceway groove of described 19th transistor is 600nm, a length of 10um；

The width of the raceway groove of described 20th transistor is 1.65um, a length of 10um；

The width of the raceway groove of described 21st transistor is 10um, a length of 500nm；

The width of the raceway groove of described 20th two-transistor is 3.2um, a length of 1um；

The width of the raceway groove of described 23rd transistor is 1um, a length of 10um；

The width of the raceway groove of described 24th transistor is 5um, a length of 4um；

The width of the raceway groove of described 25th transistor is 600nm, a length of 10um.

Alternatively, operation amplifier unit in the second level includes:

26th transistor, its grid is connected with described first order operation amplifier unit, and source electrode is with second source end even Connect, drain electrode and signal output part；

27th transistor, its grid is connected with the first bias voltage output of described bias voltage signal generating unit, Drain electrode is connected with described signal output part, and source electrode is connected with described first power end.

Alternatively, described 26th transistor is p-type mos pipe, and described 27th transistor is N-type mos pipe.

Alternatively, the width of the raceway groove of described 26th transistor is 9um, a length of 1um；

The width of the raceway groove of described 27th transistor is 8um, a length of 800nm.

Alternatively, also including: miller compensation unit, described miller compensation unit includes: resistance and electric capacity；

First end of described electric capacity is connected with the output of described first order operation amplifier unit, the second end of described electric capacity It is connected with the first end of described resistance；

Second end of described resistance is connected with the signal output part of described two-stage calculation amplifier.

The utility model has the advantages that

The utility model provides a kind of two-stage calculation amplifier, by bearing in Foldable cascade amplifying circuit Carry and on differential pair, increase cross-couplings load, to realize that taking positive feedback negative conductance gain suppression technology to increase two-stage calculation puts The gain of big device；Meanwhile, by the parameter of the mos pipe in Foldable cascade amplifying circuit is rationally arranged, To reduce the noise of two-stage calculation amplifier, so that high-gain meets with low-noise performance simultaneously；Additionally, by circuit Carry out miller compensation, can effectively ensure that the stability of circuit.

Brief description

The structural representation of a kind of two-stage calculation amplifier that Fig. 1 provides for the utility model embodiment；

Fig. 2 is the schematic diagram of the noise characteristic curve of two-stage calculation amplifier of the prior art；

Fig. 3 is the schematic diagram of the AC response curve of two-stage calculation amplifier of the prior art；

The schematic diagram of the noise characteristic curve of the two-stage calculation amplifier that Fig. 4 provides for the utility model embodiment；

The schematic diagram of the AC response curve of the two-stage calculation amplifier that Fig. 5 provides for the utility model embodiment.

Detailed description of the invention

For making those skilled in the art be more fully understood that the technical solution of the utility model, below in conjunction with the accompanying drawings to this reality It is described in detail with a kind of two-stage calculation amplifier of novel offer.

The structural representation of a kind of two-stage calculation amplifier that Fig. 1 provides for the utility model embodiment, as it is shown in figure 1, This two-stage calculation amplifier includes: bias voltage signal generating unit the 1st, first order operation amplifier unit and second level operation amplifier list Unit.

Wherein, bias voltage signal generating unit 1 and first order operation amplifier unit 2 and second level operation amplifier unit 4 all connect Connect, for providing corresponding bias voltage to first order operation amplifier unit 2 and second level operation amplifier unit 4.

First order operation amplifier unit 2 is connected with second level operation amplifier unit 4, is used for providing large gain, comprising: fold Formula cascade amplifying circuit and cross-couplings load 3, cross-couplings load 3 and bearing in Foldable cascade amplifying circuit Carrying differential pair to connect, cross-couplings load 3 includes two transistors, two transistors in cross-couplings load 3 respectively with right Two transistors of the load differential centering answered constitute two current-mirror structure, and two current-mirror structure cross-couplings.

Second level operation amplifier unit 4 is for increasing the output voltage swing of the first order 1 output signal of operation amplifier unit.

In the utility model, by the load differential in Foldable cascade amplifying circuit on increase intersect coupling Close load 3 (being also called-gm to compensate), to constitute two cross-linked current-mirror structure, now two current-mirror structure (totally four Individual transistor) equivalent output impedance be equal to the inverse of difference of mutual conductance of two current-mirror structure.In the present embodiment, it is preferable that Cross-couplings can be loaded the performance parameter (for example, the breadth length ratio of raceway groove) of two transistors in 3 be arranged and load differential Two transistors of centering are identical, now may make up two very same current mirror structures, two current-mirror structure The difference of mutual conductance is equal to 0 (in actual applications, the difference of the mutual conductance of two current-mirror structure level off to 0), two current-mirror structure Equivalent output impedance can be infinitely great, and now total output impedance phase strain of first order operation amplifier unit is big, first order computing The gain of amplifying unit promotes accordingly, and the two-stage calculation amplifier that i.e. the present embodiment provides can realize high-gain.

As concrete scheme a kind of in the present embodiment, alternatively, Foldable cascade amplifying circuit includes:

The first transistor M1, its grid and bias voltage signal generating unit 1 the 4th bias voltage output Vbias4 even Connecing, source electrode and the first power end 6 connect.

Transistor seconds M2, its grid and the first signal input part Vin1 connect, the drain electrode of source electrode and the first transistor M1 Connect.

Third transistor M3, its grid is connected with secondary signal input Vin2, the drain electrode of source electrode and the first transistor M1 Connect.

4th transistor M4, its grid and the 4th bias voltage output Vbias4 connect, and source electrode is with second source end 7 even Connecing, drain electrode is connected with the source electrode of transistor seconds M2.

5th transistor M5, its grid and the 4th bias voltage output Vbias4 connect, and source electrode is with second source end 7 even Connecing, drain electrode is connected with the source electrode of third transistor M3.

6th transistor M6, its grid is connected with the 3rd bias voltage output Vbias3 of bias voltage signal generating unit 1, The drain electrode of source electrode the 4th transistor M4 connects.

7th transistor M7, its grid and the 3rd bias voltage output Vbias3 connect, source electrode and the 5th transistor M5 Drain electrode connect, drain electrode be connected with second level operation amplifier unit 4.

8th transistor M8, its grid is connected with the second bias voltage output Vbias2 of bias voltage signal generating unit 1, Drain electrode is connected with the drain electrode of the 6th transistor M6.

9th transistor M9, its grid and the second bias voltage output Vbias2 connect, drain electrode and the 7th transistor M7 Drain electrode connect.

Tenth transistor M10, the source electrode of its grid and the 8th transistor M8 connects, the source electrode of drain electrode and the 8th transistor M8 Connecting, source electrode and the first power end 6 connect.

11st transistor M11, the drain electrode of its grid and the 9th transistor M9 connects, the source of drain electrode and the 9th transistor M9 Pole connects, and source electrode the first power end 6 connects.

Wherein, the tenth transistor M10 and the tenth two-transistor M11 constitutes load differential pair.

Alternatively, cross-couplings load 3 includes:

Tenth two-transistor M12, the source electrode of its grid and the 8th transistor M8 connects, the source of drain electrode and the 9th transistor M9 Pole connects, and source electrode and the first power end 6 connect；

13rd transistor M13, the source electrode of its grid and the 9th transistor M9 connects, the source of drain electrode and the 8th transistor M8 Pole connects, and source electrode and the first power end 6 connect；

Tenth two-transistor M12 and the tenth transistor M10 constitutes current-mirror structure, the 13rd transistor M13 and the 11st Transistor M11 constitutes current-mirror structure.

Wherein, transistor seconds M2 is identical with third transistor M3, and the 4th transistor M4 and the 5th transistor M5 is identical, the Six transistor M6 and the 7th transistor M7 are identical, and the 8th transistor M8 and the 9th transistor M9 is identical, the tenth transistor M10 and 11 transistor M11 are identical, and the tenth two-transistor M12 and the 13rd transistor M13 is identical.

Now, all-in resistance R of first order operation amplifier unit 2_out:

Ro_ut=[(g_m6+g_mb6)*r_o6*(r_o4||r_o2)]||[(g_m8+g_mb8)*r_o8*r_{o(10,11,12,13)}]…(1)

Wherein, g_m6And g_mb6Represent substrate mutual conductance (its value one during mutual conductance and the consideration bulk effect of the 6th transistor M6 respectively As less), g_m8And g_mb8(its value is general relatively in substrate mutual conductance when representing mutual conductance and the consideration bulk effect of the 8th transistor M8 respectively Little), r_o2、r_o4、r_o6And r_o8Represent transistor seconds M2, the 4th transistor M4, the 6th transistor M6, the 8th transistor M8 respectively Output impedance, r_{o(10,11,12,13)}Represent the tenth transistor M10, the 11st transistor M11, the tenth two-transistor M12, the 13rd The equivalent output impedance of transistor M13 totally four transistors.

The gain of first order operation amplifier unit 2 | A₁|:

$\begin{array}{c}\left|A_1\right|=g_{m2}*R_{out}\\ =g_{m2}*\[(g_{m6}+g_{mb6})*r_{o6}*\left(r_{o4}\right|\left|r_{o2}\right)\]\left|\right|\[(g_{m8}+g_{mb8})*r_{o8}*r_{o(10,11,12,13)}\]\end{array}\mathrm{...}\left(2\right)$

Wherein, g_m2Represent the mutual conductance of transistor seconds M2.

Based on above formula (1) and (2), when the tenth transistor M10, the 11st transistor M11, the tenth two-transistor M12, the tenth When the equivalent output impedance of three transistor M13 totally four transistors increases, the gain of first order operation amplifier unit also can be corresponding Increase.

In the present embodiment, alternatively, bias voltage signal generating unit 1 includes:

14th transistor M14, its grid and the first bias current inputs Ibias1 and the second bias voltage output Vbias2 connects, and drain electrode is connected with the first bias current inputs Ibias1.

15th transistor M15, its grid and the second bias voltage output Vbias2 connect, drain electrode and the second biased electrical Stream input Ibias2 connects.

16th transistor M16, its grid and the second bias voltage output Vbias2 connect, drain electrode and the 14th crystal The source electrode of pipe M14 connects, and source electrode and the first power end 6 connect.

17th transistor M17, the source electrode of its grid and the 15th transistor M15 and the 3rd bias voltage output Vbias3 connects, and source electrode and the first power end 6 connect.

18th transistor M18, its grid and the first bias voltage output Vbias1 connect, source electrode and second source end 7 connect.

19th transistor M19, its grid and the 4th bias voltage output Vbias4 connect, source electrode and second source end 7 connect, and drain electrode is connected with the 4th bias voltage output Vbias4.

20th transistor M20, its grid and the first bias voltage output Vbias1 connect, source electrode and the 18th crystal The drain electrode of pipe M18 connects, and drain electrode is connected with the first bias voltage output Vbias1.

21st transistor M21, its grid and the first bias voltage output Vbias1 connect, source electrode and the 19th crystalline substance The drain electrode of body pipe M19 connects.

20th two-transistor M22, its grid and the second bias voltage output Vbias2 connect, and drain electrode is brilliant with the 20th The drain electrode of body pipe M20 connects.

23rd transistor M23, its grid and the second bias voltage output Vbias2 connect, drain electrode and the 21st Transistor M21 drains connection.

24th transistor M24, its grid and the 3rd bias voltage output Vbias3 connect, drain electrode and the 22nd The source electrode of transistor M22 connects, and source electrode and the first power end 6 connect.

25th transistor M25, its grid and the 3rd bias voltage output Vbias3 connect, drain electrode and the 23rd The source electrode of transistor M23 connects, and source electrode and the first power end 6 connect.

Second level operation amplifier unit 4 includes:

26th transistor M26, its grid is connected with first order operation amplifier unit 2, and source electrode is with second source end 7 even Connect, drain electrode and signal output part Out.

First bias voltage output Vbias1 of the 27th transistor M27, its grid and bias voltage signal generating unit 1 Connecting, drain electrode is connected with signal output part Out, and source electrode and the first power end 6 connect.

Compared with the Foldable cascade structure of the first order, the noise of second level operation amplifier unit 2 is negligible. When frequency is relatively low, transistor seconds M2, third transistor M3, the 4th transistor M4, the 5th transistor M5, the tenth crystal Pipe M10, the 11st transistor M11, the tenth two-transistor M12 and the 13rd transistor M13 are as main noise source.Now should Flicker noise V of two-stage calculation amplifier_flickerWith thermal noise V_thermalIt is respectively as follows:

$V_{flic\ker }^2=2\[\frac{K_{m2}}{{\left(WL\right)}_2{C}_{ox}f}+\frac{K_{m4}}{{\left(WL\right)}_4{C}_{ox}f}\×\frac{g_{m4}^2}{g_{m2}^2}\]+\frac{2K_{m4}}{{\left(WL\right)}_4{C}_{ox}f}\×\frac{g_{m4}^2}{g_{m2}^2}\mathrm{...}\left(3\right)$

$V_{thermal}^2=8kT(\frac{\mathrm{\γ}}{g_{m2}}+\frac{{\mathrm{\γg}}_{m4}}{g_{m2}^2}+\frac{{\mathrm{\γg}}_{m(10,11,12,13)}}{g_{m2}})\mathrm{...}\left(4\right)$

Wherein, K_m2And K_m4Represent the flicker noise coefficient of transistor seconds M2 and the 4th transistor M4, (WL) respectively₂With (WL)₄Represent the channel area (product of channel length and width) of transistor seconds M2 and the 4th transistor M4, C respectively_oxTable Showing the gate oxide capacitance of unit are, f is the frequency of pending signal, γ be constant (for long channel MOSFET, γ's Value generally 2/3, in Submicron MOSFET, γ value can be bigger, and additionally the size of γ is to a certain extent as well as leakage The change of source voltage and change), k is Boltzmann constant, and T is absolute temperature.

Based on above formula (3) and (4), by increasing the mutual conductance of transistor seconds M2 (third transistor M3) and/or reduction by the The mutual conductance of four transistor M4 (the 5th transistor M5), can make flicker noise V_flickerWith thermal noise V_thermalAll reduce.

Due to the mutual conductance g of transistor seconds M2_m2For:

$g_{m2}=\sqrt{2{\mathrm{\μ}}_{m2}{C}_{ox}{(W/L)}_2{I}_{D2}}\mathrm{...}\left(5\right)$

The mutual conductance g of the 4th transistor M4_m4For:

$g_{m4}=\sqrt{2{\mathrm{\μ}}_{m4}{C}_{ox}{(W/L)}_4{I}_{D4}}\mathrm{....}\left(6\right)$

Wherein, μ_m2And μ_m4It is respectively the carrier mobility of transistor seconds M2 and the 4th transistor M4, (W/L)₂(W/ L)₄It is respectively the breadth length ratio of the raceway groove of transistor seconds M2 and the 4th transistor M4, I_D2And I_D4Respectively distribute to the second crystal Pipe M2 and the leakage current of the 4th transistor M4.

Based on above formula (5) and (6), it is contemplated that the carrier mobility in N-type mos pipe is moved than the carrier in p-type mos pipe Shifting rate is big, and in the present embodiment, transistor seconds M2 (third transistor M3) is preferably N-type mos pipe, thus can effectively promote second The mutual conductance of transistor M2；4th transistor M4 (the 5th transistor M5) is preferably p-type mos pipe, thus it is brilliant effectively to reduce the 4th The mutual conductance of body pipe M4.Meanwhile, above formula (3) is seen, owing to the flicker noise coefficient of N-type mos pipe is less than the sudden strain of a muscle of p-type mos pipe Bright noise coefficient, thus be more beneficial for when transistor seconds M2 is N-type mos pipe reducing flicker noise V_flicker。

Additionally, visible based on above formula (3), the channel area promoting transistor seconds M2 and the 4th transistor M4 is also beneficial to Reduce flicker noise V_flicker.Meanwhile, visible based on above formula (5) and (6), promoting transistor seconds M2 and the 4th crystal While the channel area of pipe M4, in addition it is also necessary to make the breadth length ratio of the raceway groove of transistor seconds M2 (improve the second crystal greatly as far as possible The mutual conductance of pipe M2), and the breadth length ratio of the raceway groove of the 4th transistor M4 is as far as possible little (reducing the mutual conductance of the 4th transistor M4).Therefore, On the premise of ensureing that channel area is certain, the width that should make the raceway groove of transistor seconds M2 is as far as possible relatively big, and makes the 4th The length of the raceway groove of transistor M4 is tried one's best bigger.

Based on above-mentioned consideration, in the present embodiment preferably, the width of the raceway groove of transistor seconds M2 and third transistor M3 Being 1.2um, length is 600nm；The width of the raceway groove of the 4th transistor M4 and the 5th transistor M5 is 1um, and length is equal For 5um.Now, low noise can be also achieved while ensureing that two-stage calculation amplifier achieves high-gain.

Alternatively, the width of the raceway groove of the first transistor M1 is 1um, a length of 600nm, now the tool of the first transistor M1 Standby bigger channel area and bigger breadth length ratio, so that flow to the leakage current of transistor seconds M2 as far as possible big, It is thus possible to effectively promote the mutual conductance of transistor seconds M2, and then be conducive to reducing noise.

In the present embodiment, still optionally further, the first transistor M1, the 8th transistor M8, the 9th transistor M9, the tenth crystalline substance Body pipe M10, the 11st transistor M11, the tenth two-transistor M12, the 13rd transistor M13, the 14th transistor M14, the tenth Five transistor M15, the 16th transistor M16, the 17th transistor M17, the 20th two-transistor M22, the 23rd transistor M23, the 24th transistor M24, the 25th transistor M25 and the 27th transistor M27 are N-type mos pipe；6th is brilliant Body pipe M6, the 7th transistor M7, the 18th transistor M18, the 19th transistor M19, the 20th transistor M20, the 21st Crystal and the 26th transistor M26 are p-type mos pipe.

Further, the width of the raceway groove of the 6th transistor M6 and the 7th transistor M7 is 1um, and length is 2.5um；The width of the raceway groove of the 8th transistor M8 and the 9th transistor M9 is 1um, and length is 8um；Tenth transistor M10 Being 600nm with the width of the raceway groove of the 11st transistor M11, length is 600nm；Tenth two-transistor M12 and the 13rd The width of the raceway groove of transistor M13 is 600nm, and length is 600nm；The width of the raceway groove of the 14th transistor M14 is 910nm, a length of 10um；The width of the raceway groove of the 15th transistor M15 is 1um, a length of 7.5um；16th transistor M16 Being 600nm with the width of the raceway groove of the 17th transistor M17, length is 10um；The width of the raceway groove of the 18th transistor M18 Degree is 750nm, a length of 10um；The width of the raceway groove of the 19th transistor M19 is 600nm, a length of 10um；20th crystal The width of the raceway groove of pipe M20 is 1.65um, a length of 10um；The width of the raceway groove of the 21st transistor M21 is 10um, length For 500nm；The width of the raceway groove of the 20th two-transistor M22 is 3.2um, a length of 1um；The ditch of the 23rd transistor M23 The width in road is 1um, a length of 10um；The width of the raceway groove of the 24th transistor M24 is 5um, a length of 4um；20th The width of the raceway groove of five transistor M25 is 600nm, a length of 10um；The width of the raceway groove of the 26th transistor M26 is 9um, A length of 1um；The width of the raceway groove of the 27th transistor M27 is 8um, a length of 800nm.

It should be noted that the first power end 6 in the present embodiment is low level end Vss, second source end 7 is high level End Vdd, the substrate of each N-type mos pipe is all connected with low level end Vss, and the substrate of each p-type mos pipe is all connected with high level end Vdd.

Alternatively, this two-stage calculation amplifier also includes: miller compensation unit 5, miller-compensated for carrying out.Specifically Ground, miller compensation unit 5 includes: an a resistance R and electric capacity C, first end of this electric capacity C and first order operation amplifier unit 2 Output terminals A connects, and second end of this electric capacity C is connected with first end of resistance R, and second end of this resistance R amplifies with two-stage calculation The signal output part Out of device connects.In the present embodiment, by arranging miller compensation unit 5, dominant pole and non-dominant pole can be made Realizing that limit separates to low frequency and high-frequency mobile respectively, the zero point of RHP is shifted to high frequency by resistance, can reduce and even offset The impact on the stability of a system for the zero point.

Fig. 2 is the schematic diagram of the noise characteristic curve of two-stage calculation amplifier of the prior art, and Fig. 3 is in prior art The schematic diagram of AC response curve of two-stage calculation amplifier, as shown in Figures 2 and 3, by emulation tool Spectre to existing Having the two-stage calculation amplifier in technology to carry out simulation analysis, its simulation result shows, two-stage calculation of the prior art amplifies The unity gain bandwidth of device is about 10MHz, and DC current gain is 125.7dB, and phase margin is 59.2o, defeated at 1MHz frequency Entering reference noise is aboutAs can be seen here, the gain of two-stage calculation amplifier of the prior art with Noise is all very big, and high-gain can not meet with low-noise performance simultaneously.

The schematic diagram of the noise characteristic curve of the two-stage calculation amplifier that Fig. 4 provides for the utility model embodiment, Fig. 5 is The schematic diagram of the AC response curve of the two-stage calculation amplifier that the utility model embodiment provides is as shown in Figure 4 and Figure 5, logical Crossing emulation tool Spectre and carrying out simulation analysis to two-stage calculation amplifier of the prior art, its simulation result shows, this reality DC current gain with the two-stage calculation amplifier of new embodiment offer is 114.3dB, i.e. amplifying power is still very strong, at 1MHz Input reference noise at frequency is aboutCompared to existing technologies, the utility model embodiment carries Its noise of the two-stage calculation amplifier of confession declines about 2/3.As can be seen here, the two-stage calculation that the utility model embodiment provides amplifies The gain of device is little with noise greatly, and high-gain meets with low-noise performance simultaneously.

It is understood that embodiment of above be merely to illustrate that principle of the present utility model and use exemplary Embodiment, but the utility model is not limited thereto.For those skilled in the art, without departing from this In the case of the spirit of utility model and essence, can make various modification and improvement, these modification and improvement are also considered as this reality With novel protection domain.

Claims (12)

1. a two-stage calculation amplifier, it is characterised in that include: bias voltage signal generating unit, first order operation amplifier unit With second level operation amplifier unit；

Described bias voltage signal generating unit, all connects with described first order operation amplifier unit and described second level operation amplifier unit Connect, for providing corresponding bias voltage to described first order operation amplifier unit and described second level operation amplifier unit；

Described first order operation amplifier unit, is connected with described second level operation amplifier unit, is used for providing large gain, comprising: Foldable cascade amplifying circuit and cross-couplings load, the load of described cross-couplings and described Foldable cascade amplify Load differential in circuit is to connection, and the load of described cross-couplings includes two transistors, two in the load of described cross-couplings Individual transistor two transistor one_to_one corresponding with corresponding described load differential centering respectively, and constitute two current mirror knots Structure, two described current-mirror structure cross-couplings；

Second level operation amplifier unit, for increasing the output voltage swing of described first order operation amplifier unit institute output signal.

2. two-stage calculation amplifier according to claim 1, it is characterised in that described Foldable cascade amplifying circuit Including:

The first transistor, its grid is connected with the 4th bias voltage output of described bias voltage signal generating unit, source electrode with First power end connects；

Transistor seconds, its grid and the first signal input part connect, and source electrode is connected with the drain electrode of described the first transistor；

Third transistor, its grid is connected with secondary signal input, and source electrode is connected with the drain electrode of described the first transistor；

4th transistor, its grid is connected with described 4th bias voltage output, and source electrode is connected with second source end, drain electrode with The drain electrode of described transistor seconds connects；

5th transistor, its grid is connected with described 4th bias voltage output, and source electrode is connected with described second source end, leakage Pole is connected with the drain electrode of described third transistor；

6th transistor, its grid is connected with the 3rd bias voltage output of described bias voltage signal generating unit, source electrode and institute The drain electrode stating the 4th transistor connects；

7th transistor, its grid is connected with described 3rd bias voltage output, the drain electrode of source electrode and described 5th transistor Connecting, drain electrode is connected with described second level operation amplifier unit；

8th transistor, its grid is connected with the second bias voltage output of described bias voltage signal generating unit, drain electrode and institute The drain electrode stating the 6th transistor connects；

9th transistor, its grid is connected with described second bias voltage output, the drain electrode of drain electrode and described 7th transistor Connect；

Tenth transistor, its grid is connected with the source electrode of described 8th transistor, and drain electrode connects with the source electrode of described 8th transistor Connecing, source electrode is connected with described first power end；

11st transistor, its grid is connected with the source electrode of described 9th transistor, the source electrode of drain electrode and described 9th transistor Connecting, source electrode is connected with described first power end；

Described tenth transistor and the 11st transistor constitute described load differential pair.

3. two-stage calculation amplifier according to claim 2, it is characterised in that the load of described cross-couplings includes:

Tenth two-transistor, its grid is connected with the source electrode of described 8th transistor, the source electrode of drain electrode and described 9th transistor Connecting, source electrode is connected with described first power end；

13rd transistor, its grid is connected with the source electrode of described 9th transistor, the source electrode of drain electrode and described 8th transistor Connecting, source electrode is connected with described first power end；

Described tenth two-transistor constitutes current-mirror structure with described tenth transistor, described in described 13rd transistor AND gate the tenth One transistor constitutes current-mirror structure.

4. two-stage calculation amplifier according to claim 3, it is characterised in that

Described the first transistor, described transistor seconds, described third transistor, described 8th transistor, described 9th crystal Pipe, described tenth transistor, described 11st transistor, described tenth two-transistor and described 13rd transistor are N-type Mos manages；

Described 4th transistor, described 5th transistor, described 6th transistor and described 7th transistor are p-type mos pipe.

5. two-stage calculation amplifier according to claim 4, it is characterised in that

The width of the raceway groove of described the first transistor is 1um, a length of 600nm；

The width of the raceway groove of described transistor seconds and described third transistor is 1.2um, and length is 600nm；

The width of the raceway groove of described 4th transistor and described 5th transistor is 1um, and length is 5um；

The width of the raceway groove of described 6th transistor and described 7th transistor is 1um, and length is 2.5um；

The width of the raceway groove of described 8th transistor and described 9th transistor is 1um, and length is 8um；

The width of the raceway groove of described tenth transistor and described 11st transistor is 600nm, and length is 600nm；

The width of the raceway groove of described tenth two-transistor and described 13rd transistor is 600nm, and length is 600nm.

6. two-stage calculation amplifier according to claim 1, it is characterised in that described bias voltage signal generating unit includes:

14th transistor, its grid and the first bias current inputs and the second bias voltage output connect, drain electrode and institute State the first bias current inputs to connect；

15th transistor, its grid is connected with described second bias voltage output, drains defeated with described second bias current Enter end to connect；

16th transistor, its grid is connected with described second bias voltage output, drain electrode and described 14th transistor Source electrode connects, and source electrode and the first power end connect；

17th transistor, its grid is connected with source electrode and the 3rd bias voltage output of described 15th transistor, source electrode It is connected with described first power end；

18th transistor, its grid and the first bias voltage output connect, and source electrode is connected with second source end；

19th transistor, its grid and the 4th bias voltage output connect, and source electrode is connected with described second source end, drain electrode It is connected with described 4th bias voltage output；

20th transistor, its grid is connected with described first bias voltage output, source electrode and described 18th transistor Drain electrode connects, and drain electrode is connected with described first bias voltage output；

21st transistor, its grid is connected with described first bias voltage output, source electrode and described 19th transistor Drain electrode connect；

20th two-transistor, its grid is connected with described second bias voltage output, drain electrode and described 20th transistor Drain electrode connect；

23rd transistor, its grid is connected with described second bias voltage output, drain electrode and described 21st crystal Pipe drain electrode connects；

24th transistor, its grid is connected with described 3rd bias voltage output, drain electrode and described 22nd crystal The source electrode of pipe connects, and source electrode is connected with described first power end；

25th transistor, its grid is connected with described 3rd bias voltage output, drain electrode and described 23rd crystal The source electrode of pipe connects, and source electrode is connected with described first power end.

7. two-stage calculation amplifier according to claim 6, it is characterised in that

Described 14th transistor, described 15th transistor, described 16th transistor, described 17th transistor, described 20th two-transistor, described 23rd transistor, described 24th transistor and described 25th transistor are N Type mos is managed；

Described 18th transistor, described 19th transistor, described 20th transistor and described 21st transistor are equal For p-type mos pipe.

8. two-stage calculation amplifier according to claim 7, it is characterised in that

The width of the raceway groove of described 14th transistor is 910nm, a length of 10um；

The width of the raceway groove of described 15th transistor is 1um, a length of 7.5um；

The width of the raceway groove of described 16th transistor and described 17th transistor is 600nm, and length is 10um；

The width of the raceway groove of described 18th transistor is 750nm, a length of 10um；

The width of the raceway groove of described 19th transistor is 600nm, a length of 10um；

The width of the raceway groove of described 20th transistor is 1.65um, a length of 10um；

The width of the raceway groove of described 21st transistor is 10um, a length of 500nm；

The width of the raceway groove of described 20th two-transistor is 3.2um, a length of 1um；

The width of the raceway groove of described 23rd transistor is 1um, a length of 10um；

The width of the raceway groove of described 24th transistor is 5um, a length of 4um；

The width of the raceway groove of described 25th transistor is 600nm, a length of 10um.

9. two-stage calculation amplifier according to claim 1, it is characterised in that second level operation amplifier unit includes:

26th transistor, its grid is connected with described first order operation amplifier unit, and source electrode is connected with second source end, leakage Pole is connected with signal output part；

27th transistor, its grid is connected with the first bias voltage output of described bias voltage signal generating unit, drain electrode Being connected with described signal output part, source electrode is connected with described first power end.

10. two-stage calculation amplifier according to claim 9, it is characterised in that

Described 26th transistor is p-type mos pipe, and described 27th transistor is N-type mos pipe.

11. two-stage calculation amplifiers according to claim 10, it is characterised in that

The width of the raceway groove of described 26th transistor is 9um, a length of 1um；

The width of the raceway groove of described 27th transistor is 8um, a length of 800nm.

12. two-stage calculation amplifiers according to claim 9, it is characterised in that also include: miller compensation unit, described Miller compensation unit includes: resistance and electric capacity；

First end of described electric capacity is connected with the output of described first order operation amplifier unit, the second end of described electric capacity and institute The first end stating resistance connects；

Second end of described resistance is connected with the signal output part of described two-stage calculation amplifier.