CN205666804U - Power amplification circuit - Google Patents
Power amplification circuit Download PDFInfo
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- CN205666804U CN205666804U CN201620460563.3U CN201620460563U CN205666804U CN 205666804 U CN205666804 U CN 205666804U CN 201620460563 U CN201620460563 U CN 201620460563U CN 205666804 U CN205666804 U CN 205666804U
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Abstract
The utility model provides a power amplification circuit, includes: a switch circuit, an amplifier and a load. Switch circuit receives 1 the 1st mains voltage and 1 the 2nd mains voltage. This switch circuit provides a mains voltage to a first node when a first mode, provide the 2nd mains voltage to this first node when a second mode. The 1st incoming signal and 1 the 2nd incoming signal are received to an amplifier to produce 1 the 1st output signal and 1 the 2nd output signal on a first output and a second output. A load, including a first inductor and a second inductor, this first inductor is connected between this first node and this first output, and this second inductor is connected between this first node and this second output.
Description
Technical field
This utility model relates to a kind of power amplification circuit (power amplifying circuit), and particularly to one
Plant changeable in the power amplification circuit of high-power output with low-power output.
Background technology
Refer to Fig. 1, be existing emitter (transmitter) schematic diagram depicted in it.Emitter (transmitter)
10 include a digital analog converter (DAC) 12, low pass filter (LPF) 14, manipulator (modulator) 16,
Programmable gain amplifier (PGA) 18 and a power amplifier 20.
Emitter 10 can connect antenna (not illustrating), and output signal is transferred to antenna so that antenna produces wireless
Radiofrequency signal, and received by the receptor (receiver) of far-end.Substantially, programmable gain amplifier 18 and power amplifier
20 can control output (output power), to control the radiant intensity of radio frequency signal.
Utility model content
The purpose of this utility model is to propose a kind of power amplification circuit, and this power amplification circuit can be according to the actual requirements
Operate in high-output power pattern and low output power mode.
This utility model relates to a kind of power amplification circuit, including: an on-off circuit, receive one first supply voltage and
Second source voltage, wherein this on-off circuit provides this first supply voltage to a primary nodal point, Yu Yi when a first mode
There is provided this second source voltage to this primary nodal point during the second pattern；One amplifier, receives one first input signal and one second
Input signal, and on one first outfan and one second outfan, produce one first output signal and one second output signal；
And a load, including one first inducer and one second inducer, this first inducer be connected to this primary nodal point and this
Between one outfan, this second inducer is connected between this primary nodal point and this second outfan.
According to an embodiment of the present utility model, this on-off circuit includes one first switch and a second switch, and this is the years old
One switch is connected between this first supply voltage and this primary nodal point, and this second switch is connected to this second source voltage and is somebody's turn to do
Between primary nodal point.
According to an embodiment of the present utility model, this first switch is power switch with this second switch.
According to an embodiment of the present utility model, this first mode is a high-output power pattern, and this second pattern is
One low output power mode, and this first supply voltage is more than this second source voltage；And, in this high-output power pattern
Time, this first switch is a closed mode and this second switch is an off-state, and when this low output power mode, this is second years old
Switch is this off-state for this closed mode and this first switch.
According to an embodiment of the present utility model, this first outfan and this second outfan are additionally coupled to one first
Distribution network, and this first matching network is connected to an antenna so that this antenna produces a radio frequency signal.
According to an embodiment of the present utility model, this amplifier, this on-off circuit are designed at an IC chip, and this IC core
Sheet, this load, this first matching network are to be designed at a circuit board with this antenna.
According to an embodiment of the present utility model, this amplifier circuit is a differential amplifier, this differential amplifier bag
Including: a first transistor, have a source electrode and be connected to one the 3rd supply voltage, a grid, with a drain electrode；One transistor seconds,
Having a source electrode and be connected to the 3rd supply voltage, a grid, with a drain electrode；One third transistor, has a source electrode and is connected to
This drain electrode of this first transistor, a grid, it is connected to this first outfan with a drain electrode；One the 4th transistor, has a source
Pole is connected to this drain electrode of this transistor seconds, a grid, is connected to this second outfan with a drain electrode；One first bias with
Distribution road, receives this first input signal, and is connected to this grid of this first transistor and these grid of this third transistor
Pole；And one second bias and match circuit, receive this second input signal, and be connected to this grid of this transistor seconds with
And the 4th this grid of transistor.
This utility model relates to a kind of power amplification circuit, including: an on-off circuit, receive one first supply voltage and
Second source voltage, wherein this on-off circuit provides this first supply voltage to a primary nodal point, Yu Yi when a first mode
There is provided this second source voltage to this primary nodal point during the second pattern；One first amplifier, receives one first input signal and
Second input signal；One second amplifier, receives this first input signal and this second input signal；Wherein, this first amplification
Device and this second amplifier one of them be enabled, and on one first outfan and one second outfan produce one first output
Signal and one second output signal；And a load, including one first inducer and one second inducer, this first inducer company
Be connected between this primary nodal point and this first outfan, this second inducer be connected to this primary nodal point and this second outfan it
Between.
According to an embodiment of the present utility model, this on-off circuit includes one first switch and a second switch, and this is the years old
One switch is connected between this first supply voltage and this primary nodal point, and this second switch is connected to this second source voltage and is somebody's turn to do
Between primary nodal point.
According to an embodiment of the present utility model, this first switch is power switch with this second switch.
According to an embodiment of the present utility model, this first mode is a high-output power pattern, and this second pattern is
One low output power mode, and this first supply voltage is more than this second source voltage；And, in this high-output power pattern
Time, this first amplifier is enabled, this second amplifier is disabled, this first switch is a closed mode and this second switch is
One off-state, when this low output power mode, this first amplifier is disabled, this second amplifier is enabled, this second
Switch is this off-state for this closed mode and this first switch.
According to an embodiment of the present utility model, this first outfan and this second outfan are additionally coupled to one first
Distribution network, and this first matching network is connected to an antenna so that this antenna produces a radio frequency signal.
According to an embodiment of the present utility model, this first amplifier, this second amplifier, this on-off circuit are designed at
One IC chip, and this IC chip, this load, this first matching network and this antenna be to be designed at a circuit board.
According to an embodiment of the present utility model, this first amplifier includes: a first transistor, has a source electrode even
Being connected to one the 3rd supply voltage, a grid, with a drain electrode；One transistor seconds, has a source electrode and is connected to the 3rd power supply electricity
Pressure, a grid, with a drain electrode；One third transistor, has a source electrode and is connected to this drain electrode of this first transistor, a grid,
It is connected to this first outfan with a drain electrode；One the 4th transistor, has a source electrode and is connected to this drain electrode of this transistor seconds,
One grid, is connected to this second outfan with a drain electrode；One first bias and match circuit, receives this first input signal, and
It is connected to this grid of this first transistor and this grid of this third transistor；And one second bias and match circuit,
Receive this second input signal, and be connected to this grid and this grid of the 4th transistor of this transistor seconds.
According to an embodiment of the present utility model, this second amplifier includes: one the 5th transistor, has a source electrode even
Being connected to the 3rd supply voltage, a grid, with a drain electrode；One the 6th transistor, has a source electrode and is connected to the 3rd power supply electricity
Pressure, a grid, with a drain electrode；One the 7th transistor, has a source electrode and is connected to this drain electrode of the 5th transistor, a grid,
It is connected to this first outfan with a drain electrode；One the 8th transistor, has a source electrode and is connected to this drain electrode of the 6th transistor,
One grid, is connected to this second outfan with a drain electrode；One the 3rd bias and match circuit, receives this first input signal, and
It is connected to this grid and this grid of the 7th transistor of the 5th transistor；And one the 4th bias and match circuit,
Receive this second input signal, and be connected to this grid and this grid of the 8th transistor of the 6th transistor.
According to an embodiment of the present utility model, this second amplifier includes: one the 5th transistor, has a source electrode even
Being connected to the 3rd supply voltage, a grid, with a drain electrode；One the 6th transistor, has a source electrode and is connected to the 3rd power supply electricity
Pressure, a grid, with a drain electrode；One the 7th transistor, has a source electrode and is connected to this drain electrode of the 5th transistor, a grid,
With a drain electrode；One the 8th transistor, has a source electrode and is connected to this drain electrode of the 6th transistor, and a grid, with a drain electrode；One
3rd bias and match circuit, receives this first input signal, and is connected to this grid and the 7th of the 5th transistor
This grid of transistor；One the 4th bias and match circuit, receives this second input signal, and is connected to the 6th transistor
This grid and this grid of the 8th transistor；And one second matching network, it is connected to this first outfan, this is second defeated
Go out end, this drain electrode of the 7th transistor and this drain electrode of the 8th transistor.
More preferably understand in order to above-mentioned and other aspect of the present utility model is had, preferred embodiment cited below particularly, and join
Close Figure of description, be described in detail below:
Accompanying drawing explanation
Fig. 1 is depicted is existing emitter schematic diagram.
Fig. 2 is depicted is power amplifier schematic diagram.
It it is the block chart of this utility model power amplification circuit depicted in Fig. 3.
The first embodiment of the depicted circuit diagram being power amplification circuit of Fig. 4.
It it is the block chart of another power amplification circuit of this utility model depicted in Fig. 5.
Fig. 6 is the second embodiment of the circuit diagram of power amplification circuit depicted in it.
3rd embodiment of the depicted circuit diagram being power amplification circuit of Fig. 7.
It it is this utility model power amplification circuit running block schematic diagram under various patterns depicted in Fig. 8 A to Fig. 8 G.
Wherein, description of reference numerals is as follows:
10: emitter (Transmitter)
12: digital analog converter
14: low pass filter
16: manipulator
18: programmable gain amplifier
20,100: power amplifier
102,104,321,322,412,422: bias and match circuit
431,432,451,452: bias and match circuit
106,206,306,368,406: load
108,208,308,370,408,453: matching network
110,210,310,380,410: antenna
202,302,362,402: on-off circuit
204,304,364,366,420,430: differential amplifier
220,360:IC chip
230,350: circuit board
390: DC-DC power converter
Detailed description of the invention
Refer to Fig. 2, be power amplifier schematic diagram depicted in it.Power amplifier 100 includes: transistor M1～M4,
Bias and match circuit (biasing and matching circuit) 102,104 and load 106.
Transistor M1, M2 connect into a differential pair circuit (differential pair circuit), transistor M1 source electrode
Being connected to supply voltage Vss, grid receives the first input signal Vin+；Transistor M2 source electrode is connected to supply voltage Vss, grid
Receive the second input signal Vin-.Wherein, the first input signal Vin+ and the second input signal Vin-are differential input signals
(differential input signal)；Supply voltage Vss is ground voltage.
Transistor M3 source electrode is connected to transistor M1 drain electrode, and grid is connected to bias and match circuit 102, and drain electrode is connected to
Node a.Transistor M4 source electrode is connected to transistor M2 drain electrode, and grid is connected to bias and match circuit 104, and drain electrode is connected to joint
Point b.Wherein, node b is to produce the first output signal Vout+ for the first outfan of power amplifier 100；Node a is for merit
Second outfan of rate amplifier 100 produces the second output signal Vout-, and the first output signal Vout+ and the second output are believed
Number Vout-is differential output signal (differential output signal).
Load 106 includes that inducer La is connected to node a and supply voltage Vdd；Inducer Lb is connected to node b and power supply
Voltage Vdd.
Two biass have identical structure with match circuit 102,104.Explain as a example by match circuit 102, coupling
In circuit 102, back coupling electric capacity and resistance are connected between node a and transistor M1 grid, and bias voltage (bias voltage) is even
It is connected to transistor M3 grid and is connected a capacitor between transistor M3 grid and supply voltage Vss.Substantially, bias and mate
Circuit 102,104 can have various design and amendment according to the actual requirements.
Matching network (matching network) 108 receives the differential output signal of power amplifier 100, and by antenna
(antenna) 110 radio frequency signal (wireless RF signal) is produced.Wherein, matching network 108 has capacitor
With inducer, it carries out impedance matching for the output impedance (output impedance) of power amplifier 100.In like manner,
Distribution network 108 can also have various design and amendment according to the actual requirements.
Substantially, power amplifier 100 is in addition to load 106, and remaining circuit all designs in IC.And load 106,
Matching network 108 and antenna 110 are all designed on circuit board (circuit board).In actual application, in order to allow power
Amplifier 100 realizes high-output power, can be using the ceiling voltage within IC as supply voltage Vdd, and supply is to power amplifier
100。
Furthermore, under the power supply mode of Fig. 2, during as being intended to power amplifier 100 is operated in low output, need to adjust
Whole bias and match circuit 102,104 reduce the bias current (bias current) in power amplifier 100.But, this
The mode of operation of sample can reduce the power-efficient (power efficiency) of power amplifier 100.
Refer to Fig. 3, be the block chart of this utility model power amplification circuit depicted in it.Power amplification circuit includes:
Differential amplifier (differential amplifier) 204, on-off circuit 202, load 206.Wherein, differential amplifier 204,
On-off circuit 202 is to be designed at IC chip 220 inside；And IC chip 220 is designed on circuit board 230 with load 206.It addition,
Matching network 208 and antenna 210 are also designed on circuit board 230.
Substantially, a front-end circuit (front end circuit) (not illustrating) can be included in IC chip 220.Front end electricity
Road includes: digital analog converter (DAC), low pass filter (LPF), manipulator (modulator) and programmable automation controller
Device (PGA).Front-end circuit can produce the first input signal Vin+ and the second input signal Vin-to differential amplifier 204 so that
Differential amplifier 204 produces the first output signal Vout+ and the second output signal Vout-.Wherein, the first input signal Vin+ with
Second input signal Vin-is differential input signals；First output signal Vout+ and the second output signal Vout-are differential output
Signal.
Load 206 includes that inducer La is connected to node a and on-off circuit 202；Inducer Lb is connected to node b and switch
Circuit 202.
It addition, on-off circuit 202 includes switching sw1 and sw2.According to embodiment of the present utility model, when power amplification electricity
Dataway operation is when high-output power pattern, and the switch sw1 in on-off circuit 202 is closed mode (close state), switch
Sw2 is off-state (open state) so that high voltage Vddh supply is to load 206.Otherwise, when power amplification circuit operates
When low output power mode, the switch sw2 in on-off circuit 202 is closed mode, and switch sw1 is off-state so that low
Voltage Vddl supply is to load 206.
It addition, IC chip 220 more can include that a DC-DC power supply converter (DC-to-DC converter) (is not painted
Show), in order to high voltage Vddh to be converted to low-voltage Vddl, or be converted to low-voltage Vddl by another cell voltage Vbat.
Furthermore, two outfans of power amplification circuit more connect a matching network 208.Matching network 208 receives power and puts
The differential output signal (Vout+, Vout-) of big device, and produced radio frequency signal by antenna 210.It is same as Fig. 2, pair net
The capacitor having in network 208 and inducer, it carries out impedance matching for the output impedance of power amplification circuit.Matching network
208 can also have various design and amendment according to the actual requirements.
Refer to Fig. 4, be the first embodiment of power amplification circuit depicted in it.Power amplification circuit includes: differential put
Big device 304, on-off circuit 302, load 306.
In differential amplifier 304, transistor M1 source electrode is connected to supply voltage Vss, and transistor M3 source electrode is connected to crystal
Pipe M1 drains, and transistor M3 drain electrode is connected to node a；Transistor M2 source electrode is connected to supply voltage Vss, and transistor M4 source electrode is even
Being connected to transistor M2 drain electrode, transistor M4 drain electrode is connected to node b.Wherein, supply voltage Vss can be ground voltage.
Furthermore, bias and match circuit 321 receive the first input signal Vin+, and are connected to the grid of transistor M1, M3；
Bias and match circuit 322 receive the second input signal Vin-, and are connected to the grid of transistor M2, M4.In the same manner, bias with
Match circuit 321,322 is same as bias and the match circuit 102,104 of Fig. 2.Furthermore, bias is with match circuit 321,322 also
Can there be various design and amendment according to the actual requirements.
On-off circuit 302 includes switching sw1 and sw2.Switch sw1 is connected between supply voltage Vddh and node c；Switch
Sw2 is connected between supply voltage Vddl and node c.Wherein, switch sw1, sw2 is power switch (power switch).Again
Person, supply voltage Vddh is more than supply voltage Vss more than supply voltage Vddl, supply voltage Vddl.For example, supply voltage
Vddh is 3.3V, and supply voltage Vddl is 1.8V, and supply voltage Vss is 0V.
Load 306 includes that inducer La is connected between node a and node c；Inducer Lb is connected to node b and node c
Between.According to embodiment of the present utility model, when power amplification circuit operation is in high-output power pattern, on-off circuit 302
In switch sw1 be closed mode, switch sw2 is off-state so that supply voltage Vddh supply to load 306.Otherwise, when
Power amplification circuit operates when low output power mode, and the switch sw2 in on-off circuit 302 is closed mode, and switch sw1 is
Off-state so that supply voltage Vddl supply is to load 306.
Furthermore, node a and node b is two outfans of power amplification circuit, and this two outfan more connects a matching network
308.Matching network 308 receives the differential output signal (Vout+, Vout-) of power amplifier, and is produced wireless by antenna 310
Radiofrequency signal.
Refer to Fig. 5, be another block chart of this utility model power amplification circuit depicted in it.Power amplification circuit bag
Include: first differential amplifier the 364, second differential amplifier 366, on-off circuit 362, load 368.Wherein, the first differential amplification
Device the 364, second differential amplifier 366, on-off circuit 362 are to be designed at IC chip 360 inside；And IC chip 360 and load 368
It is designed on circuit board 350.It addition, matching network 370 and antenna 380 are also designed on circuit board 350.
Substantially, a front-end circuit can be included in IC chip 360.Front-end circuit includes: digital analog converter (DAC),
Low pass filter (LPF), manipulator (modulator) and programmable gain amplifier (PGA).It is defeated that front-end circuit can produce first
Enter signal Vin+ and the second input signal Vin-to the first differential amplifier 364 and the second differential amplifier 366.
Furthermore, control the first differential amplifier 364 and one of them running of the second differential amplifier 366, and produce first
Output signal Vout+ and the second output signal Vout-.Wherein, the first input signal Vin+ and the second input signal Vin-are for poor
Dynamic input signal；First output signal Vout+ and the second output signal Vout-are differential output signal.
Load 368 includes that inducer La is connected to node a and on-off circuit 362；Inducer Lb is connected to node b and switch
Circuit 362.
It addition, on-off circuit 362 includes switching sw1 and sw2.According to embodiment of the present utility model, control the first power
Switch sw1 and sw2 in amplifying circuit the 364, second power amplification circuit 366 and on-off circuit 362, can make power amplification
Circuit operation is at suitable power mode output.
Furthermore, IC chip 360 more can include that a DC-DC power supply converter (DC-to-DC converter) (is not painted
Show), in order to high voltage Vddh to be converted to low-voltage Vddl, or be converted to low-voltage Vddl by another cell voltage Vbat.
Two outfans of power amplification circuit more connect a matching network 370.Matching network 370 receives power amplifier
Differential output signal (Vout+, Vout-), and produced radio frequency signal by antenna 380.It is same as Fig. 2, in matching network 380
The capacitor having and inducer, it carries out impedance matching for the output impedance of power amplification circuit.Matching network 380 also may be used
To have various design and amendment according to the actual requirements.
Refer to Fig. 6, be the second embodiment of the circuit diagram of power amplification circuit depicted in it.Power amplification circuit bag
Include: first differential amplifier the 420, second amplifying circuit 430, on-off circuit 402, load 406.
In first differential amplifier device 420, transistor M1 source electrode is connected to supply voltage Vss, and transistor M3 source electrode connects
Draining to transistor M1, transistor M3 drain electrode is connected to node a；Transistor M2 source electrode is connected to supply voltage Vss, transistor M4
Source electrode is connected to transistor M2 drain electrode, and transistor M4 drain electrode is connected to node b.Wherein, supply voltage Vss can be ground voltage.
Furthermore, bias and match circuit 421 receive the first input signal Vin+, and are connected to the grid of transistor M1, M3；
Bias and match circuit 422 receive the second input signal Vin-, and are connected to the grid of transistor M2, M4.
In second differential amplifier 430, transistor M5 source electrode is connected to supply voltage Vss, and transistor M7 source electrode is connected to
Transistor M5 drains, and transistor M7 drain electrode is connected to node a；Transistor M6 source electrode is connected to supply voltage Vss, transistor M8 source
Pole is connected to transistor M6 drain electrode, and transistor M8 drain electrode is connected to node b.
Furthermore, bias and match circuit 431 receive the first input signal Vin+, and are connected to the grid of transistor M5, M7；
Bias and match circuit 432 receive the second input signal Vin-, and are connected to the grid of transistor M6, M8.
According to the second embodiment of the present utility model, the first differential amplifier 420 is operate within high-output power pattern, the
Two differential amplifiers 430 are operate within low output power mode.In other words, operate at high-output power mould when power amplification circuit
During formula, the first differential amplifier 420 is enabled (enabled) and the second differential amplifier 430 is disabled (disabled).Instead
It, when power amplification circuit operation is at low output power mode, the second differential amplifier 430 is enabled and the first differential amplification
Device 420 is disabled.
It addition, the bias in the first differential amplifier 420 is to be designed at high-output power mould with match circuit 421,422
Formula, the bias in the second differential amplifier 430 and match circuit 431,432 are to be designed at low output power mode.Therefore, bias
With the resistance value that the resistance value of match circuit 421,422 differs from bias and match circuit 431,432.
On-off circuit 402 includes switching sw1 and sw2.Switch sw1 is connected between supply voltage Vddh and node c；Switch
Sw2 is connected between supply voltage Vddl and node c.Wherein, switch sw1, sw2 is power switch.Furthermore, supply voltage Vddh
More than supply voltage Vddl, supply voltage Vddl more than supply voltage Vss.For example, supply voltage Vddh is 3.3V, power supply
Voltage Vddl is 1.8V, and supply voltage Vss is 0V.
Load 406 includes that inducer La is connected between node a and node c；Inducer Lb is connected to node b and node c
Between.According to embodiment of the present utility model, when power amplification circuit operation is in high-output power pattern, on-off circuit 402
In switch sw1 be closed mode, switch sw2 is off-state so that supply voltage Vddh supply to load 406.Otherwise, when
Power amplification circuit operates when low output power mode, and the switch sw2 in on-off circuit 402 is closed mode, and switch sw1 is
Off-state so that supply voltage Vddl supply is to load 706.
Furthermore, node a and node b is two outfans of power amplification circuit, and this two outfan more connects a matching network
408.Matching network 408 receives the differential output signal (Vout+, Vout-) of power amplifier, and is produced wireless by antenna 410
Radiofrequency signal.
Refer to Fig. 7, be the 3rd embodiment of the circuit diagram of power amplification circuit depicted in it.Power amplification circuit bag
Include: first differential amplifier the 420, second differential amplifier 450, on-off circuit 402, load 406.Compared to the second embodiment,
Its difference is the structure of 450 in the second differential amplifier.Hereinafter only introducing the second differential amplifier 450, remaining repeats no more.
In second differential amplifier 450, transistor M5 source electrode is connected to supply voltage Vss, and transistor M7 source electrode is connected to
Transistor M5 drains, and transistor M7 drain electrode is connected to matching network 453；Transistor M6 source electrode is connected to supply voltage Vss, crystal
Pipe M8 source electrode is connected to transistor M6 drain electrode, and transistor M8 drain electrode is connected to matching network 453.It addition, matching network 453 connects
To node a and node b.Matching network 453 enters for the output impedance (output impedance) of the second differential amplifier 450
Row impedance matching.
From above explanation, power amplification circuit of the present utility model is operable in high-output power pattern or low
Output power mode.When high-output power pattern, on-off circuit provides higher supply voltage (such as 3.3V)；Otherwise, in
During low output power mode, on-off circuit provides relatively low supply voltage (such as 1.8V).
It is known that Wi-Fi technology and Bluetooth technology (bluetooth) come under the standard of wireless technology.In Wi-Fi skill
In the utilization of art, its emitter (Transmitter) is optionally with high-output power (high power) or low-power
(low power) transmits wireless Wi-Fi signal.On the contrary, bluetooth (bluetooth is called for short BT) technology is belonging to low-power
Radio transmission techniques, its emitter is to transmit wireless BT signal with low output (low output power).Cause
This, power amplification circuit of the present utility model may be disposed in emitter (Transmitter), applies to need high-power output
Wi-Fi technology, or apply to low-power output Bluetooth technology.Or it is operated in Wi-Fi mode equally, closely
Use on, use low-power output；When remote, use high-power output.
Refer to Fig. 8 A to Fig. 8 G, show for the operation under various patterns of this utility model power amplification circuit depicted in it
It is intended to.Illustrating with the power amplification circuit of Fig. 5 below, wherein the first differential amplifier 364 is operate within high output work
Rate pattern, the second differential amplifier 366 is operate within low output power mode.
As shown in Figure 8 A, when the Wi-Fi mode of high-power output, the first differential amplifier 364 is enabled (enable),
Second differential amplifier 366 is disabled (disable), and switch sw1 is closed mode (close state), and switch sw2 is for disconnecting
State (open state).Therefore, emitter (Transmitter) is to transmit wireless Wi-Fi signal with high-output power, and
Wireless Wi-Fi signal can transmit farthest distance.
As shown in Figure 8 B, when the first Wi-Fi mode of low-power output, the first differential amplifier 364 is disabled, and second
Differential amplifier 366 is enabled, and switch sw1 is closed mode, and switch sw2 is off-state.Therefore, emitter is with low output
Power transmits wireless Wi-Fi signal, and wireless Wi-Fi signal can transmit shorter distance.
As shown in Figure 8 C, when the second Wi-Fi mode of low-power output, the first differential amplifier 364 is disabled, and second
Differential amplifier 366 is enabled, and switch sw1 is off-state, and switch sw2 is closed mode.Therefore, emitter is with low output
Power transmits wireless Wi-Fi signal, and wireless Wi-Fi signal can transmit shorter distance.
As in fig. 8d, when three Wi-Fi mode of low-power output, the first differential amplifier 364 is disabled, and second
Differential amplifier 366 is enabled, and switch sw1 is off-state, and switch sw2 is closed mode.It addition, DC-DC power supply turns
Parallel operation 390 receives cell voltage Vbat and is converted to low-voltage Vddl.Therefore, emitter is wireless to transmit with low output
Wi-Fi signal, and wireless Wi-Fi signal can transmit shorter distance.
As illustrated in fig. 8e, when a BT pattern of low-power output, the first differential amplifier 364 is disabled, and second is poor
Dynamic amplifier 366 is enabled, and switch sw1 is closed mode, and switch sw2 is off-state.Therefore, emitter is with low output work
Rate transmits wireless BT signal.
As shown in 8F schemes, when the 2nd BT pattern of low-power output, the first differential amplifier 364 is disabled, and second
Differential amplifier 366 is enabled, and switch sw1 is off-state, and switch sw2 is closed mode.Therefore, emitter is with low output
Power transmits wireless BT signal.
As shown in fig. 8g, when the 3rd BT pattern of low-power output, the first differential amplifier 364 is disabled, and second is poor
Dynamic amplifier 366 is enabled, and switch sw1 is off-state, and switch sw2 is closed mode.It addition, DC-DC power supply conversion
Device 390 receives cell voltage Vbat and is converted to low-voltage Vddl.Therefore, emitter is to transmit wireless BT with low output
Signal.
Furthermore, above-mentioned power amplification circuit all explains as a example by differential amplifier, but and is not used to limit this reality
With novel.Can also be according to above explanation the amplification utilizing single-ended point (single ended) those skilled in the art
Device forms power amplification circuit of the present utility model, and realizes above-mentioned technical characteristic of the present utility model.
In sum, although this utility model is open as above with preferred embodiment, and so it is not limited to this practicality
Novel.Technical staff in this utility model art, without departing from the spirit and scope of this utility model, when making
Various variations and retouching.Therefore, the protection domain of this utility model when depending on after attached as defined in claim be as the criterion.
Claims (16)
1. a power amplification circuit, it is characterised in that including:
One on-off circuit, receives one first supply voltage and a second source voltage, and wherein this on-off circuit is in a first mode
Time provide this first supply voltage to a primary nodal point, provide this second source voltage to this first segment when second pattern
Point；
One amplifier, receives one first input signal and one second input signal, and in one first outfan and one second output
One first output signal and one second output signal is produced on end；And
One load, including one first inducer and one second inducer, this first inducer be connected to this primary nodal point and this
Between one outfan, this second inducer is connected between this primary nodal point and this second outfan.
2. power amplification circuit as claimed in claim 1, it is characterised in that this on-off circuit includes one first switch and one the
Two switch, this first switch be connected between this first supply voltage and this primary nodal point, this second switch be connected to this second
Between supply voltage and this primary nodal point.
3. power amplification circuit as claimed in claim 2, it is characterised in that this first switch is that power is opened with this second switch
Close.
4. power amplification circuit as claimed in claim 2, it is characterised in that this first mode is a high-output power pattern,
This second pattern is a low output power mode, and this first supply voltage is more than this second source voltage；And, defeated in this height
When going out power mode, this first switch is a closed mode and this second switch is an off-state, in this low output mould
During formula, this second switch is that this closed mode and this first switch are for this off-state.
5. power amplification circuit as claimed in claim 4, it is characterised in that this first outfan also connects with this second outfan
It is connected to one first matching network, and this first matching network is connected to an antenna so that this antenna produces a radio frequency signal.
6. power amplification circuit as claimed in claim 5, it is characterised in that this amplifier, this on-off circuit are designed at an IC
Chip, and this IC chip, this load, this first matching network and this antenna be to be designed at a circuit board.
7. power amplification circuit as claimed in claim 5, it is characterised in that this amplifier circuit is a differential amplifier, should
Differential amplifier includes:
One the first transistor, has a source electrode and is connected to one the 3rd supply voltage, and a grid, with a drain electrode；
One transistor seconds, has a source electrode and is connected to the 3rd supply voltage, and a grid, with a drain electrode；
One third transistor, has a source electrode and is connected to this drain electrode of this first transistor, a grid, be connected to this with a drain electrode
First outfan；
One the 4th transistor, has a source electrode and is connected to this drain electrode of this transistor seconds, a grid, be connected to this with a drain electrode
Second outfan；
One first bias and match circuit, receives this first input signal, and be connected to this first transistor this grid and
This grid of this third transistor；And
One second bias and match circuit, receives this second input signal, and be connected to this transistor seconds this grid and
This grid of 4th transistor.
8. a power amplification circuit, it is characterised in that including:
One on-off circuit, receives one first supply voltage and a second source voltage, and wherein this on-off circuit is in a first mode
Time provide this first supply voltage to a primary nodal point, provide this second source voltage to this first segment when second pattern
Point；
One first amplifier, receives one first input signal and one second input signal；
One second amplifier, receives this first input signal and this second input signal；Wherein, this first amplifier with this second
Amplifier one of them be enabled, and on one first outfan and one second outfan, produce one first output signal and one the
Two output signals；And
One load, including one first inducer and one second inducer, this first inducer be connected to this primary nodal point and this
Between one outfan, this second inducer is connected between this primary nodal point and this second outfan.
9. power amplification circuit as claimed in claim 8, it is characterised in that this on-off circuit includes one first switch and one the
Two switch, this first switch be connected between this first supply voltage and this primary nodal point, this second switch be connected to this second
Between supply voltage and this primary nodal point.
10. power amplification circuit as claimed in claim 9, it is characterised in that this first switch is power with this second switch
Switch.
11. power amplification circuits as claimed in claim 9, it is characterised in that this first mode is a high-output power pattern,
This second pattern is a low output power mode, and this first supply voltage is more than this second source voltage；And, defeated in this height
When going out power mode, this first amplifier is enabled, this second amplifier is disabled, this first switch is a closed mode and is somebody's turn to do
Second switch is an off-state, and when this low output power mode, this first amplifier is disabled, this second amplifier is caused
Can, this second switch be that this closed mode and this first switch are for this off-state.
12. power amplification circuits as claimed in claim 10, it is characterised in that this first outfan is with this second outfan also
It is connected to one first matching network, and this first matching network is connected to an antenna so that this antenna produces a less radio-frequency letter
Number.
13. power amplification circuits as claimed in claim 12, it is characterised in that this first amplifier, this second amplifier, should
On-off circuit is designed at an IC chip, and this IC chip, this load, this first matching network are to be designed at a circuit with this antenna
Plate.
14. power amplification circuits as claimed in claim 12, it is characterised in that this first amplifier includes:
One the first transistor, has a source electrode and is connected to one the 3rd supply voltage, and a grid, with a drain electrode；
One transistor seconds, has a source electrode and is connected to the 3rd supply voltage, and a grid, with a drain electrode；
One third transistor, has a source electrode and is connected to this drain electrode of this first transistor, a grid, be connected to this with a drain electrode
First outfan；
One the 4th transistor, has a source electrode and is connected to this drain electrode of this transistor seconds, a grid, be connected to this with a drain electrode
Second outfan；
One first bias and match circuit, receives this first input signal, and be connected to this first transistor this grid and
This grid of this third transistor；And
One second bias and match circuit, receives this second input signal, and be connected to this transistor seconds this grid and
This grid of 4th transistor.
15. power amplification circuits as claimed in claim 14, it is characterised in that this second amplifier includes:
One the 5th transistor, has a source electrode and is connected to the 3rd supply voltage, and a grid, with a drain electrode；
One the 6th transistor, has a source electrode and is connected to the 3rd supply voltage, and a grid, with a drain electrode；
One the 7th transistor, has a source electrode and is connected to this drain electrode of the 5th transistor, a grid, be connected to this with a drain electrode
First outfan；
One the 8th transistor, has a source electrode and is connected to this drain electrode of the 6th transistor, a grid, be connected to this with a drain electrode
Second outfan；
One the 3rd bias and match circuit, receives this first input signal, and be connected to the 5th transistor this grid and
This grid of 7th transistor；And
One the 4th bias and match circuit, receives this second input signal, and be connected to the 6th transistor this grid and
This grid of 8th transistor.
16. power amplification circuits as claimed in claim 14, it is characterised in that this second amplifier includes:
One the 5th transistor, has a source electrode and is connected to the 3rd supply voltage, and a grid, with a drain electrode；
One the 6th transistor, has a source electrode and is connected to the 3rd supply voltage, and a grid, with a drain electrode；
One the 7th transistor, has a source electrode and is connected to this drain electrode of the 5th transistor, and a grid, with a drain electrode；
One the 8th transistor, has a source electrode and is connected to this drain electrode of the 6th transistor, and a grid, with a drain electrode；
One the 3rd bias and match circuit, receives this first input signal, and be connected to the 5th transistor this grid and
This grid of 7th transistor；
One the 4th bias and match circuit, receives this second input signal, and be connected to the 6th transistor this grid and
This grid of 8th transistor；And
One second matching network, be connected to this first outfan, this second outfan, this drain electrode of the 7th transistor and
This drain electrode of 8th transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620460563.3U CN205666804U (en) | 2016-05-19 | 2016-05-19 | Power amplification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620460563.3U CN205666804U (en) | 2016-05-19 | 2016-05-19 | Power amplification circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205666804U true CN205666804U (en) | 2016-10-26 |
Family
ID=57161485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620460563.3U Expired - Fee Related CN205666804U (en) | 2016-05-19 | 2016-05-19 | Power amplification circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205666804U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107404297A (en) * | 2016-05-19 | 2017-11-28 | 深圳市南方硅谷微电子有限公司 | Power amplification circuit |
| CN112165306A (en) * | 2020-12-02 | 2021-01-01 | 深圳市南方硅谷半导体有限公司 | Switching circuit of multiple gain low noise amplifier |
| CN114039556A (en) * | 2021-09-30 | 2022-02-11 | 锐磐微电子科技(上海)有限公司 | Radio frequency power amplifier and radio frequency power amplification system |
| CN117767965A (en) * | 2024-01-10 | 2024-03-26 | 荣耀终端有限公司 | Power supply and load switching circuit, low noise amplifier and electronic equipment |
-
2016
- 2016-05-19 CN CN201620460563.3U patent/CN205666804U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107404297A (en) * | 2016-05-19 | 2017-11-28 | 深圳市南方硅谷微电子有限公司 | Power amplification circuit |
| CN112165306A (en) * | 2020-12-02 | 2021-01-01 | 深圳市南方硅谷半导体有限公司 | Switching circuit of multiple gain low noise amplifier |
| CN112165306B (en) * | 2020-12-02 | 2021-03-05 | 深圳市南方硅谷半导体有限公司 | Switching circuit of multiple gain low noise amplifier |
| CN114039556A (en) * | 2021-09-30 | 2022-02-11 | 锐磐微电子科技(上海)有限公司 | Radio frequency power amplifier and radio frequency power amplification system |
| CN117767965A (en) * | 2024-01-10 | 2024-03-26 | 荣耀终端有限公司 | Power supply and load switching circuit, low noise amplifier and electronic equipment |
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