CN205582944U - Thin film transistor, array substrate and display device - Google Patents
Thin film transistor, array substrate and display device Download PDFInfo
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- CN205582944U CN205582944U CN201620426659.8U CN201620426659U CN205582944U CN 205582944 U CN205582944 U CN 205582944U CN 201620426659 U CN201620426659 U CN 201620426659U CN 205582944 U CN205582944 U CN 205582944U
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Abstract
The utility model provides a thin film transistor, array substrate and display device, thin film transistor includes active layer, non -crystalline silicon articulamentum and source -drain electrode layer. The active layer has channel region, source area and drain region, the formation material of channel region includes polycrystalline silicon, the non -crystalline silicon articulamentum is located one side of active layer to including separating first connecting portion and the second connecting portion that set up each other, the source -drain electrode layer is including separating source electrode and the drain electrode that sets up each other, the source electrode passes through first connecting portion with the source area electricity is connected, the drain electrode is passed through the second connecting portion with the drain region electricity is connected. This manufacture craft that openly can simplify polycrystalline siTFT.
Description
Technical field
Embodiment of the present utility model relates to a kind of thin film transistor (TFT), array base palte and display device.
Background technology
Polycrystalline SiTFT is owing to having the advantages such as higher electron mobility and stability, the most general
All over being applied in various display.
But, the making step of polycrystalline SiTFT is various, takes around 10 road exposure technologys.
As a example by low-temperature polysilicon film transistor, its manufacturing process includes: move back for forming the laser of polysilicon
Ignition technique, for forming two secondary ions with the active layer that district, heavily doped region and channel region are lightly doped
Injection technology, and dehydrogenation, be hydrogenated with and the high-temperature technology such as activation.The technique of these complexity makes low temperature many
Polycrystal silicon film transistor generally in six generation lines or following exploitation volume production, and yield is relatively low, equipment investment relatively
Greatly and poor with the product line compatibility of amorphous silicon film transistor.
Utility model content
For the problem of the complex manufacturing technology of polycrystalline SiTFT, of the present utility model at least one
Embodiment provides a kind of thin film transistor (TFT), array base palte and display device, to simplify polysilicon membrane crystal
The processing technology of pipe.
At least one embodiment of the present utility model provides a kind of thin film transistor (TFT), comprising: active layer,
Non-crystalline silicon articulamentum and source-drain electrode layer.Described active layer has channel region, source area and drain region, institute
The formation material stating channel region includes polysilicon；Described non-crystalline silicon articulamentum is positioned at the one of described active layer
Side, and include the first connecting portion and the second connecting portion being intervally installed；Described source-drain electrode layer bag
Including the source electrode and drain electrode being intervally installed, described source electrode is by described first connecting portion and described source area
Electrical connection, described drain electrode is electrically connected with described drain region by described second connecting portion.
Such as, described source area and described drain region are all undoped region.
Such as, the formation material of described source area and described drain region is undoped non-crystalline silicon or undoped
Polysilicon.
Such as, described non-crystalline silicon articulamentum includes the first amorphous silicon layer and the second non-crystalline silicon that stacking arranges
Layer, described second amorphous silicon layer is arranged between described first amorphous silicon layer and described source-drain electrode layer, and
The electrical conductivity of described second amorphous silicon layer is more than the electrical conductivity of described first amorphous silicon layer.
Such as, the formation material of described first amorphous silicon layer is undoped non-crystalline silicon.
Such as, described thin film transistor (TFT) also includes bearing substrate, and is being perpendicular to described bearing substrate
On direction, described active layer is arranged between described bearing substrate and described source-drain electrode layer.
Such as, the material of described source-drain electrode layer is metal material.
Such as, on from described source area to the direction of described drain region, the outward flange of described active layer it
Between distance equal to distance between described first connecting portion and the outward flange of described second connecting portion.
Such as, the distance between the outward flange of described source electrode and described drain electrode equal to described first connecting portion and
Distance between the outward flange of described second connecting portion.
Such as, the distance between the outward flange of described source electrode and described drain electrode equal to described first connecting portion and
Distance between the outward flange of described second connecting portion.
Such as, described thin film transistor (TFT) also includes that bearing substrate and grid, described grid have described in being arranged at
Between active layer and described bearing substrate.
At least one embodiment of the present utility model also provides for a kind of array base palte, it include multiple to each other
Every the thin film transistor (TFT) arranged, described thin film transistor (TFT) is the thin film transistor (TFT) described in any of the above item.
Such as, described array base palte also includes multiple pixel electrode being intervally installed, the plurality of picture
Element electrode respectively corresponding the plurality of thin film transistor (TFT), and each pixel electrode and corresponding film crystal
The drain electrode electrical connection of pipe.
At least one embodiment of the present utility model also provides for a kind of display device, and it includes any of the above-described item
Described array base palte.
At least one embodiment of the present utility model also provides for another kind of thin film transistor (TFT), and it includes active layer
With source-drain electrode layer.Described active layer has channel region, source area and drain region, the shape of described channel region
Becoming material to include polysilicon, the formation material of described source area and described drain region includes doped amorphous silicon；
Described source-drain electrode layer is positioned at the side of described active layer and includes source electrode and the leakage being intervally installed
Pole, described source electrode electrically connects with described source area, and described drain electrode electrically connects with described drain region.
In this utility model embodiment, the active layer of thin film transistor (TFT) has employing polycrystalline silicon material and is formed
Channel region, thus can ensure that this thin film transistor (TFT) has bigger ON state current；Additionally, active layer
Source area and drain region respectively by amorphous silicon material and source electrode with drain to electrically connect or all use and mix
Miscellaneous amorphous silicon material makes to realize and source electrode and the electrical connection of drain electrode, so can save making and be lightly doped
District and twice ion implantation technology of heavily doped region and corresponding exposure technology.Therefore, this utility model
Embodiment can simplify polycrystalline on the premise of having bigger ON state current ensureing polycrystalline SiTFT
The processing technology of silicon thin film transistor.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of this utility model embodiment, attached by embodiment below
Figure is briefly described, it should be apparent that, the accompanying drawing in describing below merely relates to of the present utility model one
A little embodiments, rather than to restriction of the present utility model.
The cross-sectional schematic of a kind of thin film transistor (TFT) that Fig. 1 provides for this utility model embodiment；
The cross-sectional schematic of the another kind of thin film transistor (TFT) that Fig. 2 provides for this utility model embodiment；
The cross-sectional schematic of a kind of array base palte that Fig. 3 provides for this utility model embodiment；
The flow chart of a kind of method making thin film transistor (TFT) that Fig. 4 provides for this utility model embodiment；
The making that Fig. 5 a to Fig. 5 c provides for this utility model embodiment thin film transistor (TFT) as shown in Figure 2
The cross-sectional schematic of each step；
The section view signal of a kind of insulating barrier making array base palte that Fig. 6 provides for this utility model embodiment
Figure；
The cross-sectional schematic of a kind of thin film transistor (TFT) that Fig. 7 provides for this utility model embodiment.
Detailed description of the invention
For making the purpose of this utility model embodiment, technical scheme and advantage clearer, below in conjunction with
The accompanying drawing of this utility model embodiment, carries out clear, complete to the technical scheme of this utility model embodiment
Ground describes.Obviously, described embodiment is a part of embodiment of the present utility model rather than all
Embodiment.Based on described embodiment of the present utility model, those of ordinary skill in the art without
The every other embodiment obtained on the premise of creative work, broadly falls into the model of this utility model protection
Enclose.
Unless otherwise defined, the disclosure uses technical term or scientific terminology should be this utility model
There is in art the ordinary meaning that the personage of general technical ability is understood.The disclosure uses " the
One ", " second " and similar word be not offered as any order, quantity or importance, and be
It is used for distinguishing different ingredients." include " or word that " comprising " etc. is similar mean to occur should
Element before word or object are contained and are occurred in the element of this word presented hereinafter or object and equivalent thereof,
And it is not excluded for other elements or object." connect " or word that " being connected " etc. is similar non-limiting
In physics or the connection of machinery, but electrical connection can be included, be no matter direct or
Connect.On " ", D score, "left", "right" etc. be only used for representing relative position relation, right when being described
After the absolute position of elephant changes, then this relative position relation is likely to correspondingly change.
This utility model embodiment provides a kind of thin film transistor (TFT), array base palte and display device.In this reality
With in new embodiment, the active layer of thin film transistor (TFT) has the channel region using polycrystalline silicon material to be formed,
Thus can ensure that this thin film transistor (TFT) has bigger ON state current；Additionally, the source area of active layer and
Drain region is electrically connected by amorphous silicon material with source electrode and drain electrode or all uses doped amorphous silicon material respectively
Material makes to realize and source electrode and the electrical connection of drain electrode, so can save making and district and heavy doping are lightly doped
Twice ion implantation technology in district and corresponding exposure technology.Therefore, this utility model embodiment is permissible
Ensureing to simplify on the premise of polycrystalline SiTFT has bigger ON state current polysilicon membrane crystal
The processing technology of pipe.
Below in conjunction with the accompanying drawings this utility model embodiment is described in detail.
As it is shown in figure 1, at least one embodiment of the present utility model provides a kind of thin film transistor (TFT) 100,
This thin film transistor (TFT) 100 includes active layer 110, non-crystalline silicon articulamentum 120 and source-drain electrode layer 130.
Active layer 110 have channel region 113 and lay respectively at channel region 113 both sides and with channel region 113
The source area 111 connected and drain region 112, the formation material of channel region 113 includes polysilicon, such as,
The formation material of source area 111 and drain region 112 can be polysilicon or non-crystalline silicon；Non-crystalline silicon articulamentum
120 sides being positioned at active layer 110, and include the first connecting portion 121 and being intervally installed
Two connecting portions 122；Source-drain electrode layer 130 includes source electrode 131 and the drain electrode 132 being intervally installed,
Source electrode 131 is electrically connected with source area 111 by the first connecting portion 121, and drain electrode 132 is by the second connection
Portion 122 electrically connects with drain region 112.
In the thin film transistor (TFT) 100 that this utility model embodiment provides, the source area 111 of active layer 110
Electrically connected with source electrode 131 and drain electrode 132 respectively by non-crystalline silicon articulamentum 120 with drain region 112.Cause
And, compared with the technique of common making polysilicon (p-Si) thin film transistor (TFT), this utility model is implemented
The processing technology of the thin film transistor (TFT) 100 that example provides can be omitted and form light, the ion implanting of heavily doped region
Technique and corresponding exposure technology, this makes, and the processing technology of this thin film transistor (TFT) 100 is simple, equipment is thrown
Provide less, be applicable to advanced lines line and the product line with non-crystalline silicon (a-Si) thin film transistor (TFT) has preferably
Compatible.Another further aspect, compared with common amorphous silicon film transistor, this utility model embodiment carries
The channel region 113 of the active layer 110 that the thin film transistor (TFT) 100 of confession includes uses polycrystalline silicon material (such as
Low-temperature polysilicon silicon materials) make, owing to polycrystalline silicon material has a bigger electron mobility, thus this reality
The thin film transistor (TFT) 100 provided by new embodiment has bigger ON state current.
Such as, the source area 111 of active layer 110 and drain region 112 can be all undoped region, such as,
The formation material of source area 111 and drain region 112 can be undoped non-crystalline silicon or undoped polycrystalline
Silicon.Source area 111 and drain region 112 by non-crystalline silicon articulamentum 120 respectively with source electrode 131 and drain electrode
132 electrical connection and be all undoped region, be conducive to the film crystal making this utility model embodiment provide
Pipe 100 has a relatively low OFF leakage current, is especially all non-mixing at source area 111 and drain region 112
In the case of miscellaneous non-crystalline silicon, compared with the common polycrystalline SiTFT including light, heavily doped region,
Thin film transistor (TFT) 100 in this utility model embodiment has lower OFF leakage current.
Electrically connect with source electrode 131 and drain electrode 132 respectively to realize source area 111 and drain region 112,
Such as, the formation material in source area 111 and drain region 112 is all undoped non-crystalline silicon or undoped
In the case of polysilicon, the first connecting portion 121 of non-crystalline silicon articulamentum 120 and the second connecting portion 122
Forming material can be doped amorphous silicon, such as p-type doped amorphous silicon or n-type doping non-crystalline silicon.
Such as, in order to improve between source area 111 and drain region 112 and source electrode 131 and drain electrode 132
Electrical connectivity, the material of source-drain electrode layer 130 can be metal material.
Such as, as it is shown in figure 1, at least one embodiment of the present utility model provide thin film transistor (TFT) 100
Also include bearing substrate 100a, and on the direction being perpendicular to bearing substrate 100a, active layer 110
Can be arranged between bearing substrate 100a and source-drain electrode layer 130.So arrange, thin film can be made
The processing technology of transistor 100 is simpler.
Common polycrystalline SiTFT is top gate structure, can in manufacturing process with grid be so
Mask carries out ion implantation doping to active layer.The thin film transistor (TFT) provided due to this utility model embodiment
The manufacturing process of 100 can omit ion implantation doping process, it is therefoie, for example, of the present utility model extremely
The thin film transistor (TFT) 100 that a few embodiment provides can be bottom grating structure, i.e. this thin film transistor (TFT) 100
Also include grid 140, between grid 140 and active layer 110, be provided with gate insulation layer 150, and grid
Pole 140 is arranged between active layer 110 and bearing substrate 100a.Certainly, in certain embodiments,
Thin film transistor (TFT) 100 can also use top gate structure.
In at least one embodiment of the present utility model, in order to simplify the making work of thin film transistor (TFT) 100
Skill, can be by making, with an exposure technology, the plural layers that this thin film transistor (TFT) 100 includes.
Such as, on from source area 111 to the direction of drain region 112, the outward flange 110a of active layer 110,
Distance between 110b may be approximately equal to the first connecting portion 121 and outward flange of the second connecting portion 122
Distance between 121a, 122a.So, active layer 110 can be by one with non-crystalline silicon articulamentum 120
Secondary exposure technology (such as half-exposure technique) is formed, to reduce the number of times of exposure technology.On this basis,
Such as, the distance between outward flange 131a, 132a of source electrode 131 and drain electrode 132 may be approximately equal to
Distance between first connecting portion 121 and outward flange 121a, 122a of the second connecting portion 122.So,
Source-drain electrode layer 130, active layer 110 can pass through single exposure technique (example with non-crystalline silicon articulamentum 120
Such as half-exposure technique) formed, to reduce the number of times of exposure technology further.
Such as, the distance between outward flange 131a, 132a of source electrode 131 and drain electrode 132 can be substantially
Equal to the distance between the first connecting portion 121 and outward flange 121a, 122a of the second connecting portion 122.
So, source-drain electrode layer 130 and non-crystalline silicon articulamentum 120 can pass through single exposure technique (such as half
Exposure technology) formed, to reduce the number of times of exposure technology.
Fig. 1 illustrates as a example by non-crystalline silicon articulamentum 120 is as single layer structure, and certainly, non-crystalline silicon connects
Layer 120 can also be multiple structure.
Such as, as in figure 2 it is shown, at least one embodiment of the present utility model provide thin film transistor (TFT)
In 100, non-crystalline silicon articulamentum 120 includes the first amorphous silicon layer 120a and the second non-crystalline silicon that stacking arranges
Layer 120b, the second amorphous silicon layer 120b are arranged at the first amorphous silicon layer 120a and source-drain electrode layer 130
Between, and the electrical conductivity that the electrical conductivity of the second amorphous silicon layer 120b is more than the first amorphous silicon layer 120a.?
In this case, the second amorphous silicon layer 120b can play the effect of ohmic contact layer, to improve first
Electrical connectivity between non-crystalline silicon articulamentum 120a and source-drain electrode layer 130.
Such as, the second amorphous silicon layer 120b can be n-type doping non-crystalline silicon or p-type doped amorphous silicon.
Such as, the first amorphous silicon layer can be undoped non-crystalline silicon.Owing to non-crystalline silicon articulamentum 120 includes
Use the first amorphous silicon layer 120a that undoped non-crystalline silicon makes, thus be more beneficial for reducing thin film transistor (TFT)
The OFF leakage current of 100.
Such as, in the embodiment shown in figure 2, the formation material of source area 111 and drain region 112
It can be all the polysilicon of undoped.Light, the polycrystalline SiTFT of heavily doped region is included with common
Compare, thin film transistor (TFT) 100 so can be made to have relatively low OFF leakage current.
As it is shown on figure 3, at least one embodiment of the present utility model also provides for a kind of array base palte 10, its
Including multiple thin film transistor (TFT)s 100 as described in above-mentioned any embodiment being intervally installed.In Fig. 3
Illustrate only the non-crystalline silicon articulamentum 120 in a thin film transistor (TFT) 100, and this thin film transistor (TFT) 100
For double-layer structure.Certainly, the array base palte that this utility model embodiment provides includes but not limited to Fig. 3 institute
The embodiment shown.
Such as, the array base palte 10 that at least one embodiment of the present utility model provides can also include many
The individual pixel electrode 101 being intervally installed, the plurality of pixel electrode 101 is the most corresponding above-mentioned multiple thin
Film transistor 100, and the drain electrode 132 of each pixel electrode 101 and corresponding thin film transistor (TFT) 100
Electrical connection.Such as, array base palte 10 can also include the insulating barrier 102 of cover film transistor 100,
Pixel electrode 101 can be by the drain electrode of the via in insulating barrier 102 with corresponding thin film transistor (TFT) 100
132 electrical connections.
Such as, pixel electrode 101 can use ITO (tin indium oxide), IZO (indium zinc oxide) or class
Make like transparent conductive material.Do not limit.
The array base palte that this utility model embodiment provides can be OLED (Organic Light Emitting Diode) battle array
Row substrate, it is also possible to for the array base palte for liquid crystal indicator.Additionally, this array base palte 10 is also
The structures such as such as public electrode wire, grid line, data wire can be included, repeat no more here.
At least one embodiment of the present utility model also provides for a kind of display device, and it includes that any of the above is real
Execute the array base palte 10 that example provides.
Such as, this display device can be: liquid crystal panel, Electronic Paper, oled panel, mobile phone, flat
Plate computer, television set, display, notebook computer, DPF, navigator etc. are any has display
The product of function or parts.
As shown in Figure 4, at least one embodiment of the present utility model also provides for the system of a kind of thin film transistor (TFT)
Make method, comprising: step S1, form the active layer with channel region, source area and drain region,
The formation material making channel region includes polysilicon；Step S2, forms non-crystalline silicon even in the side of active layer
Connect layer 120, make the first connecting portion and the second connecting portion that non-crystalline silicon articulamentum includes being intervally installed；
And step S3, form source-drain electrode layer in the side away from active layer of non-crystalline silicon articulamentum, make this
Source-drain electrode layer includes source electrode and drain electrode, and source electrode is electrically connected with source area by the first connecting portion, and drain electrode is logical
Cross the second connecting portion to electrically connect with drain region.
Such as, in above-mentioned steps S1, it is formed with active layer and may include that formation amorphous silicon membrane；With
And to the channel region to be formed of this amorphous silicon membrane or the portion of channel region to be formed, source area and drain region
Divide and carry out laser annealing process so that this part forms polysilicon.This utility model embodiment is by amorphous
Silicon thin film carries out local laser and makes annealing treatment to form polysilicon, thin to whole non-crystalline silicon with commonly use at present
Film carries out the mode of laser annealing process and compares, and is conducive to the making side making this utility model embodiment provide
Method produces line for advanced lines.
Step S1 in the manufacture method that this utility model embodiment provides does not limits to the order of step S3.
For example, it is possible to by half-exposure technique be formed active layer and non-crystalline silicon articulamentum, i.e. step S1 and
Step S2 can synchronize to carry out；Or, active layer, non-crystalline silicon can be formed with even by half-exposure technique
Connect layer and source-drain electrode layer, i.e. step S1 to step S3 can synchronize to carry out.Half-exposure technique refers to profit
It is exposed processing to the photoresist on thin film with intermediate tone mask plate or gray tone mask plate, carries out afterwards
Development and etching processing are with the technique forming the figure needed.
For example, it is possible to form non-crystalline silicon articulamentum thin film (non-crystalline silicon articulamentum the most to be formed thin of stacking
Film) and source-drain electrode layer film (thin film of source-drain electrode layer the most to be formed)；Afterwards, to non-crystalline silicon even
Connect layer film and source-drain electrode layer film carries out single exposure technique to form non-crystalline silicon articulamentum and source and drain
Electrode layer.It is to say, step S2 and step S3 can synchronize to make.
Certainly, step S1 includes but not limited to these cited orders to the order of step S3.
The method that this utility model embodiment provides may be used for making the thin of any of the above-described embodiment offer
Film transistor 100.
Such as, for thin film transistor (TFT) 100 as shown in Figure 2, at least one reality of the present utility model
Execute in the manufacture method that example provides, form non-crystalline silicon articulamentum 120 and may include that the first of formation stacking
Amorphous silicon layer 120a and the second amorphous silicon layer 120b, makes the second amorphous silicon layer 120b be formed at the first amorphous
Between silicon layer 120a and source-drain electrode layer 130, and the electrical conductivity of the second amorphous silicon layer 120b is more than first
The electrical conductivity of amorphous silicon layer 120a.So can improve the first non-crystalline silicon articulamentum 120a and source-drain electrode
Electrical connectivity between layer 130.
Such as, the second amorphous silicon layer 120b can be n-type doping non-crystalline silicon or p-type doped amorphous silicon；
Such as, the first amorphous silicon layer can be undoped non-crystalline silicon.
Below as a example by the thin film transistor (TFT) 100 shown in Fig. 2, the system that this utility model embodiment is provided
It is described in detail as method.Such as, shown as shown in Figure 5 a to 5 c, the method can include following step
Rapid S01 is to step S04.
Step S01: successively at bearing substrate 100a (such as glass substrate) upper formation grid 140, grid
Insulating barrier 150 and amorphous silicon membrane 110', as shown in Figure 5 a.
Such as, by depositing, exposing, the process such as etching form grid 140；Then deposit and such as nitrogenize
Silicon layer and silicon dioxide layer are to form gate insulation layer 150；Redeposited amorphous silicon membrane 110' afterwards.
Step S02: the bearing substrate 100a completing step S01 is carried out high-temperature dehydrogenation process, then
Active layer to be formed (channel region 113 the most to be formed, source area 111 and for amorphous silicon membrane 110'
Drain region 112) part 110 " carry out laser annealing process, so that this part 110 " form polysilicon,
As shown in Figure 5 b.
Step S03: be sequentially depositing non-crystalline silicon articulamentum on the bearing substrate 100a complete step S02
Thin film 120' and source-drain electrode layer film 130', non-crystalline silicon articulamentum thin film 120' include that be sequentially depositing treats
Form thin film (such as undoped non-crystalline silicon, the referred to as a-Si) 120a' of the first amorphous silicon layer, to be formed
Thin film (the such as doped amorphous silicon, such as n-type doping non-crystalline silicon, referred to as n+a of the second amorphous silicon layer
Si) 120b', as shown in Figure 5 c.
Step S04: the bearing substrate 100a completing step S03 is carried out half-exposure technique, then enters
Row etching, to form the first amorphous silicon layer 120a of thin film transistor (TFT) 100 as shown in Figure 2, second non-
Crystal silicon layer 120b, active layer 110 and source-drain electrode layer 130.
At least one embodiment of the present utility model also provides for the manufacture method of a kind of array base palte, its bag
Including: form multiple thin film transistor (TFT) being intervally installed, this thin film transistor (TFT) uses any of the above-described enforcement
The manufacture method that example provides makes.Such as, this thin film transistor (TFT) can with any of the above-described embodiment provide thin
Film transistor 100.
Such as, after having made thin film transistor (TFT), as shown in Figure 6, this utility model embodiment provides
Method can also include: form the insulating barrier 102 of cover film transistor 100 and be positioned at insulating barrier
Via (not marking in Fig. 6) in 102；And form pixel electrode 101, make this pixel electrode 101
Electrically connected with the drain electrode 132 of thin film transistor (TFT) 100 by the via in insulating barrier 102.
The manufacture method that this utility model embodiment provides is applicable to various display pattern, such as TN
(Twisted Nematic), VA (Vertical Alignment), IPS (In-Plane Switch) or ADS
(Advanced Super Dimension Switch) pattern.
Certainly, the manufacture method that this utility model embodiment provides also includes other step.Such as, in shape
The technique of the grid 140 of one-tenth thin film transistor (TFT) 100 can also form grid line and public electrode wire；Such as,
Data wire can also be formed in the technique of the source electrode 131 and drain electrode 132 that form thin film transistor (TFT) 100；
For example, it is also possible to formation public electrode, this public electrode is made to electrically connect with public electrode wire.Do not do
Repeat.
As it is shown in fig. 7, at least one embodiment of the present utility model also provides for a kind of thin film transistor (TFT) 200,
It includes active layer 210 and source-drain electrode layer 230.Active layer 210 has channel region 213, Yi Jifen
It is not positioned at channel region 213 both sides and the source area 211 being connected with channel region 213 and drain region 212, ditch
The formation material in road district 213 includes polysilicon, and the formation material of source area 211 and drain region 212 includes
Doped amorphous silicon (such as n-type doping non-crystalline silicon or p-type doped amorphous silicon)；230, source-drain electrode layer
The source electrode 231 being intervally installed in the side of active layer 210 and including and drain electrode 232, source electrode 231
Electrically connecting with source area 211, drain electrode 232 electrically connects with drain region 212.
Such as, the manufacture method of active layer 210 may include that formation amorphous silicon membrane；To this non-crystalline silicon
The position of the channel region to be formed 213 of thin film carries out laser annealing and processes to form polysilicon, and carries out
Exposure, etching etc. process to remove remaining amorphous silicon membrane；Afterwards, polycrystalline silicon channel district is formed
Doped amorphous silicon film (such as directly can form this doped amorphous silicon film by depositional mode), and
Be exposed it, etching etc. processes to form the source area 211 and drain region being connected with channel region 213
212, it is consequently formed active layer 210.It is of course also possible to use alternate manner to make active layer 210.
In the thin film transistor (TFT) 200 that this utility model embodiment provides, the source area 211 of active layer 210
With drain region 212 use doped amorphous silicon material make with realize respectively with source electrode 131 and drain 132
Electrical connection.Thus, compared with the technique of common making polysilicon (p-Si) thin film transistor (TFT), this reality
Can omit by the processing technology of the thin film transistor (TFT) 200 of new embodiment offer and form light, heavily doped region
Ion implantation technology and corresponding exposure technology, this makes the processing technology letter of this thin film transistor (TFT) 200
Single, equipment investment is less, be applicable to advanced lines line and with the product of non-crystalline silicon (a-Si) thin film transistor (TFT)
Line has preferable compatibility.Another further aspect, compared with common amorphous silicon film transistor, this practicality is new
The channel region 213 of the active layer 210 that the thin film transistor (TFT) 200 that type embodiment provides includes uses polysilicon
Material (such as low-temperature polysilicon silicon materials) makes, owing to polycrystalline silicon material has bigger electron mobility,
Thus the thin film transistor (TFT) 200 that this utility model embodiment provides has bigger ON state current.
Such as, thin film transistor (TFT) 200 also includes bearing substrate 200a, and is being perpendicular to bearing substrate
On the direction of 200a, channel region 213, source area 211 and source electrode 131 can overlap at same position,
Channel region 213, drain region 212 and drain electrode 132 can also overlap at same position.So can carry
Electrical connectivity between high channel region, source/drain region and source/drain.
Certainly, the thin film transistor (TFT) 200 that this utility model embodiment provides can also include bearing substrate
200a, grid 240 and the gate insulation layer 250 etc. being arranged between grid 240 and active layer 210 are tied
Structure.
In sum, thin film transistor (TFT) that this utility model embodiment provides and preparation method thereof, array base
Plate and preparation method thereof and display device have the advantage that.
1, in this utility model embodiment, it is not necessary to the active layer of thin film transistor (TFT) is carried out ion implanting
Can realize the source area of active layer and drain region respectively with source electrode and the electrical connection of drain electrode, such that it is able to save
Slightly ion implantation technology and corresponding exposure technology.
2, in this utility model embodiment, the channel region of the active layer that thin film transistor (TFT) includes uses many
Crystal silicon (such as low temperature polycrystalline silicon) material makes, thus can ensure that higher electron mobility.
3, in embodiments more of the present utility model, the source area of active layer and drain region are all non-mixing
Miscellaneous district, is connected with source electrode and drain electrode respectively by non-crystalline silicon articulamentum afterwards, thus can reduce OFF state leakage
Electric current.
4, in the manufacture method that this utility model embodiment provides, non-by polysilicon to be formed
Polycrystal silicon film carries out local laser annealing, it is ensured that annealing homogeneity and productive temp, thus has
The manufacture method being beneficial to make this utility model embodiment provide is applicable to advanced lines product line.
5, compared with the processing technology of amorphous silicon film transistor, the system that this utility model embodiment provides
Merely add high-temperature dehydrogenation and laser annealing as method to process, thus equipment investment is few, technique simple and
The product line of amorphous silicon film transistor has preferable compatibility.
Above-mentioned thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof and the reality of display device
Executing example can reference mutually.Additionally, in the case of not conflicting, embodiment of the present utility model and enforcement
Feature in example can be mutually combined.
The above, detailed description of the invention the most of the present utility model, but protection domain of the present utility model
It is not limited thereto, the technology model that any those familiar with the art discloses at this utility model
In enclosing, change can be readily occurred in or replace, all should contain within protection domain of the present utility model.Cause
This, protection domain of the present utility model should be as the criterion with described scope of the claims.
Claims (15)
1. a thin film transistor (TFT), it is characterised in that described thin film transistor (TFT) includes:
Active layer, has channel region, source area and drain region, wherein, the formation material of described channel region
Including polysilicon；
Non-crystalline silicon articulamentum, is positioned at the side of described active layer, and includes first be intervally installed
Connecting portion and the second connecting portion；And
Source-drain electrode layer, including the source electrode being intervally installed and drain electrode, wherein, described source electrode passes through institute
Stating the first connecting portion to electrically connect with described source area, described drain electrode is by described second connecting portion and described leakage
Polar region electrically connects.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that described source area and institute
Stating drain region is all undoped region.
Thin film transistor (TFT) the most according to claim 2, it is characterised in that described source area and institute
The formation material stating drain region is undoped non-crystalline silicon or un-doped polysilicon.
Thin film transistor (TFT) the most according to any one of claim 1 to 3, it is characterised in that institute
State the first amorphous silicon layer and the second amorphous silicon layer that non-crystalline silicon articulamentum includes that stacking arranges, described second non-
Crystal silicon layer is arranged between described first amorphous silicon layer and described source-drain electrode layer, and described second non-crystalline silicon
The electrical conductivity of layer is more than the electrical conductivity of described first amorphous silicon layer.
Thin film transistor (TFT) the most according to claim 4, it is characterised in that described first non-crystalline silicon
The formation material of layer is undoped non-crystalline silicon.
Thin film transistor (TFT) the most according to any one of claim 1 to 3, it is characterised in that institute
State thin film transistor (TFT) and also include bearing substrate, on the direction being perpendicular to described bearing substrate, described active
Layer is arranged between described bearing substrate and described source-drain electrode layer.
Thin film transistor (TFT) the most according to any one of claim 1 to 3, it is characterised in that institute
The material stating source-drain electrode layer is metal material.
Thin film transistor (TFT) the most according to any one of claim 1 to 3, it is characterised in that
From described source area to the direction of described drain region, the distance between the outward flange of described active layer is equal to
Distance between the outward flange of described first connecting portion and described second connecting portion.
Thin film transistor (TFT) the most according to claim 8, it is characterised in that described source electrode and described
Distance between the outward flange of drain electrode is equal to described first connecting portion and the outward flange of described second connecting portion
Between distance.
Thin film transistor (TFT) the most according to any one of claim 1 to 3, it is characterised in that institute
State the distance between the outward flange of source electrode and described drain electrode equal to described first connecting portion and described second even
Connect the distance between the outward flange in portion.
11. thin film transistor (TFT)s according to any one of claim 1 to 3, it is characterised in that institute
State thin film transistor (TFT) and also include that bearing substrate and grid, described grid are arranged at described active layer and hold with described
Between carried base board.
12. 1 kinds of array base paltes, it is characterised in that described array base palte includes multiple being intervally installed
Thin film transistor (TFT), described thin film transistor (TFT) is that thin film according to any one of claim 1 to 11 is brilliant
Body pipe.
13. array base paltes according to claim 12, it is characterised in that described array base palte is also
Including multiple pixel electrodes being intervally installed,
Wherein, the plurality of pixel electrode corresponding the plurality of thin film transistor (TFT) respectively, and each pixel
Electrode electrically connects with the drain electrode of corresponding thin film transistor (TFT).
14. 1 kinds of display devices, it is characterised in that described display device includes according to claim 12
Or the array base palte described in 13.
15. 1 kinds of thin film transistor (TFT)s, it is characterised in that described thin film transistor (TFT) includes:
Active layer, has channel region, source area and drain region, wherein, the formation material of described channel region
Including polysilicon, the formation material of described source area and described drain region includes doped amorphous silicon；And
Source-drain electrode layer, is positioned at the side of described active layer and includes source electrode and the leakage being intervally installed
Pole, wherein, described source electrode electrically connects with described source area, and described drain electrode electrically connects with described drain region.
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| CN201620426659.8U CN205582944U (en) | 2016-05-11 | 2016-05-11 | Thin film transistor, array substrate and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870198A (en) * | 2016-05-11 | 2016-08-17 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof, array substrate and manufacturing device thereof and display device |
| CN107221503A (en) * | 2017-06-02 | 2017-09-29 | 京东方科技集团股份有限公司 | A kind of preparation method of thin film transistor (TFT), thin film transistor (TFT) and display base plate |
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2016
- 2016-05-11 CN CN201620426659.8U patent/CN205582944U/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105870198A (en) * | 2016-05-11 | 2016-08-17 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof, array substrate and manufacturing device thereof and display device |
| WO2017193667A1 (en) * | 2016-05-11 | 2017-11-16 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method therefor, array substrate and manufacturing method therefor, and display apparatus |
| US10403756B2 (en) | 2016-05-11 | 2019-09-03 | Boe Technology Group Co., Ltd. | Thin-film transistor (TFT) and manufacturing method thereof, array substrate and manufacturing method thereof, and display device |
| CN105870198B (en) * | 2016-05-11 | 2020-03-31 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device |
| CN107221503A (en) * | 2017-06-02 | 2017-09-29 | 京东方科技集团股份有限公司 | A kind of preparation method of thin film transistor (TFT), thin film transistor (TFT) and display base plate |
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Inventor after: Bai Jinchao Inventor after: Guo Huibin Inventor after: Hong Yongtai Inventor before: Bai Jinchao Inventor before: Guo Huibin Inventor before: Li Shengxuan |
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